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1/** @file\r
2 Platform Hook Library instance for UART device upon coreboot.\r
3\r
4 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
d2e8b7e1 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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6\r
7**/\r
8\r
9#include <Base.h>\r
10#include <Uefi/UefiBaseType.h>\r
68f87b25 11#include <Library/PciLib.h>\r
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12#include <Library/PlatformHookLib.h>\r
13#include <Library/CbParseLib.h>\r
14#include <Library/PcdLib.h>\r
15\r
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16typedef struct {\r
17 UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
18 UINT16 DeviceId; ///< Device ID to match the PCI device\r
19 UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
20 UINT64 Offset; ///< The byte offset into to the BAR\r
21 UINT8 BarIndex; ///< Which BAR to get the UART base address\r
22 UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
23 UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
24 UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
25 UINT8 Reserved[2];\r
26} PCI_SERIAL_PARAMETER;\r
27\r
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28/**\r
29 Performs platform specific initialization required for the CPU to access\r
30 the hardware associated with a SerialPortLib instance. This function does\r
68f87b25 31 not initialize the serial port hardware itself. Instead, it initializes\r
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32 hardware devices that are required for the CPU to access the serial port\r
33 hardware. This function may be called more than once.\r
34\r
35 @retval RETURN_SUCCESS The platform specific initialization succeeded.\r
36 @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.\r
37\r
38**/\r
39RETURN_STATUS\r
40EFIAPI\r
41PlatformHookSerialPortInitialize (\r
42 VOID\r
43 )\r
44{\r
45 RETURN_STATUS Status;\r
46 UINT32 SerialRegBase;\r
47 UINT32 SerialRegAccessType;\r
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48 UINT32 BaudRate;\r
49 UINT32 RegWidth;\r
50 UINT32 InputHertz;\r
51 UINT32 PayloadParam;\r
52 UINT32 DeviceVendor;\r
53 PCI_SERIAL_PARAMETER *SerialParam;\r
54\r
55 Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType,\r
56 &RegWidth, &BaudRate, &InputHertz,\r
57 &PayloadParam);\r
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58 if (RETURN_ERROR (Status)) {\r
59 return Status;\r
60 }\r
61\r
62 if (SerialRegAccessType == 2) { //MMIO\r
53f97bdc 63 Status = PcdSetBoolS (PcdSerialUseMmio, TRUE);\r
bae5ddc0 64 } else { //IO\r
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65 Status = PcdSetBoolS (PcdSerialUseMmio, FALSE);\r
66 }\r
67 if (RETURN_ERROR (Status)) {\r
68 return Status;\r
69 }\r
70 Status = PcdSet64S (PcdSerialRegisterBase, (UINT64) SerialRegBase);\r
71 if (RETURN_ERROR (Status)) {\r
72 return Status;\r
bae5ddc0 73 }\r
bae5ddc0 74\r
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75 Status = PcdSet32S (PcdSerialRegisterStride, RegWidth);\r
76 if (RETURN_ERROR (Status)) {\r
77 return Status;\r
78 }\r
79\r
80 Status = PcdSet32S (PcdSerialBaudRate, BaudRate);\r
81 if (RETURN_ERROR (Status)) {\r
82 return Status;\r
83 }\r
84\r
85 Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate);\r
86 if (RETURN_ERROR (Status)) {\r
87 return Status;\r
88 }\r
89\r
90 Status = PcdSet32S (PcdSerialClockRate, InputHertz);\r
91 if (RETURN_ERROR (Status)) {\r
92 return Status;\r
93 }\r
94\r
95 if (PayloadParam >= 0x80000000) {\r
96 DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000);\r
97 SerialParam = PcdGetPtr(PcdPciSerialParameters);\r
98 SerialParam->VendorId = (UINT16)DeviceVendor;\r
99 SerialParam->DeviceId = DeviceVendor >> 16;\r
100 SerialParam->ClockRate = InputHertz;\r
101 SerialParam->RegisterStride = (UINT8)RegWidth;\r
102 }\r
103\r
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104 return RETURN_SUCCESS;\r
105}\r