[mirror_edk2.git] / DuetPkg / PciBusNoEnumerationDxe / PciBus.h

/*++\r
\r
Copyright (c) 2005 - 2007, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
\r
  PciBus.h\r
  \r
Abstract:\r
\r
  PCI Bus Driver\r
\r
Revision History\r
\r
--*/\r
\r
#ifndef _EFI_PCI_BUS_H\r
#define _EFI_PCI_BUS_H\r
\r
#include <PiDxe.h>\r
\r
#include <Protocol/PciIo.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/DevicePath.h>\r
#include <Protocol/Decompress.h>\r
#include <Protocol/UgaIo.h>\r
#include <Protocol/LoadedImage.h>\r
#include <Protocol/BusSpecificDriverOverride.h>\r
\r
#include <Guid/PciOptionRomTable.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/Acpi.h>\r
#include <IndustryStandard/PeImage.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PeCoffLib.h>\r
\r
//\r
// Driver Produced Protocol Prototypes\r
//\r
\r
#define VGABASE1  0x3B0\r
#define VGALIMIT1 0x3BB\r
\r
#define VGABASE2  0x3C0\r
#define VGALIMIT2 0x3DF\r
\r
#define ISABASE   0x100\r
#define ISALIMIT  0x3FF\r
\r
typedef enum {\r
  PciBarTypeUnknown = 0,\r
  PciBarTypeIo16,\r
  PciBarTypeIo32,\r
  PciBarTypeMem32,\r
  PciBarTypePMem32,\r
  PciBarTypeMem64,\r
  PciBarTypePMem64,\r
  PciBarTypeIo,\r
  PciBarTypeMem,\r
  PciBarTypeMaxType\r
} PCI_BAR_TYPE;\r
\r
typedef struct {\r
  UINT64        BaseAddress;\r
  UINT64        Length;\r
  UINT64        Alignment;\r
  PCI_BAR_TYPE  BarType;\r
  BOOLEAN       Prefetchable;\r
  UINT8         MemType;\r
  UINT8         Offset;\r
} PCI_BAR;\r
\r
#define PCI_IO_DEVICE_SIGNATURE   SIGNATURE_32 ('p','c','i','o')\r
\r
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED        0x0001 \r
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED      0x0002 \r
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED      0x0004 \r
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED        0x0008  \r
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED   0x0010  \r
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED       0x0020\r
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED       0x0040\r
\r
\r
typedef struct _PCI_IO_DEVICE {\r
  UINT32                                    Signature;\r
  EFI_HANDLE                                Handle;\r
  EFI_PCI_IO_PROTOCOL                       PciIo;\r
  LIST_ENTRY                            Link;\r
\r
  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;\r
\r
  //\r
  // PCI configuration space header type\r
  //\r
  PCI_TYPE00                                Pci;\r
\r
  //\r
  // Bus number, Device number, Function number\r
  //\r
  UINT8                                     BusNumber;\r
  UINT8                                     DeviceNumber;\r
  UINT8                                     FunctionNumber;\r
\r
  //\r
  // BAR for this PCI Device\r
  //\r
  PCI_BAR                                   PciBar[PCI_MAX_BAR];\r
\r
  //\r
  // The bridge device this pci device is subject to\r
  //\r
  struct _PCI_IO_DEVICE                     *Parent;\r
\r
  //\r
  // A linked list for children Pci Device if it is bridge device\r
  //\r
  LIST_ENTRY                            ChildList;\r
\r
  //\r
  // TRUE if the PCI bus driver creates the handle for this PCI device\r
  //\r
  BOOLEAN                                   Registered;\r
\r
  //\r
  // TRUE if the PCI bus driver successfully allocates the resource required by\r
  // this PCI device\r
  //\r
  BOOLEAN                                   Allocated;\r
\r
  //\r
  // The attribute this PCI device currently set\r
  //\r
  UINT64                                    Attributes;\r
\r
  //\r
  // The attributes this PCI device actually supports\r
  //\r
  UINT64                                    Supports;\r
\r
  //\r
  // The resource decode the bridge supports\r
  //\r
  UINT32                                    Decodes;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomSize;\r
\r
  //\r
  // TRUE if there is any EFI driver in the OptionRom\r
  //\r
  BOOLEAN                                   BusOverride;\r
\r
  //\r
  //  A list tracking reserved resource on a bridge device\r
  //\r
  LIST_ENTRY                            ReservedResourceList;\r
\r
  //\r
  // A list tracking image handle of platform specific overriding driver\r
  //\r
  LIST_ENTRY                            OptionRomDriverList;\r
\r
  BOOLEAN                                   IsPciExp;\r
\r
} PCI_IO_DEVICE;\r
\r
\r
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LINK(a) \\r
  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
\r
//\r
// Global Variables\r
//\r
extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL  gPciBusComponentName2;\r
extern EFI_DRIVER_BINDING_PROTOCOL  gPciBusDriverBinding;\r
\r
extern BOOLEAN                     gFullEnumeration;\r
extern UINT64                      gAllOne;\r
extern UINT64                      gAllZero;\r
\r
#include "PciIo.h"\r
#include "PciCommand.h"\r
#include "PciDeviceSupport.h"\r
#include "PciEnumerator.h"\r
#include "PciEnumeratorSupport.h"\r
#include "PciDriverOverride.h"\r
#include "PciRomTable.h"\r
#include "PciOptionRomSupport.h"\r
#include "PciPowerManagement.h"\r
\r
\r
#define IS_ISA_BRIDGE(_p)       IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)  \r
#define IS_INTEL_ISA_BRIDGE(_p) (IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE) && ((_p)->Hdr.VendorId == 0x8086) && ((_p)->Hdr.DeviceId == 0x7110))\r
#define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
\r
#endif\r
Commit	Line	Data
10590588	1	/*++\r
10590588	2	\r
b1f700a8 HT	3	Copyright (c) 2005 - 2007, Intel Corporation. All rights reserved.<BR>\r
b1f700a8 HT	4	This program and the accompanying materials \r
10590588	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	\r
	14	PciBus.h\r
	15	\r
	16	Abstract:\r
	17	\r
	18	PCI Bus Driver\r
	19	\r
	20	Revision History\r
	21	\r
	22	--*/\r
	23	\r
	24	#ifndef _EFI_PCI_BUS_H\r
	25	#define _EFI_PCI_BUS_H\r
	26	\r
df93b0ff	27	#include <PiDxe.h>\r
10590588	28	\r
	29	#include <Protocol/PciIo.h>\r
	30	#include <Protocol/PciRootBridgeIo.h>\r
	31	#include <Protocol/DevicePath.h>\r
	32	#include <Protocol/Decompress.h>\r
	33	#include <Protocol/UgaIo.h>\r
	34	#include <Protocol/LoadedImage.h>\r
	35	#include <Protocol/BusSpecificDriverOverride.h>\r
	36	\r
	37	#include <Guid/PciOptionRomTable.h>\r
	38	\r
a397f1b0	39	#include <IndustryStandard/Pci.h>\r
10590588	40	#include <IndustryStandard/Acpi.h>\r
	41	#include <IndustryStandard/PeImage.h>\r
	42	\r
	43	#include <Library/DebugLib.h>\r
	44	#include <Library/UefiDriverEntryPoint.h>\r
	45	#include <Library/BaseLib.h>\r
	46	#include <Library/UefiLib.h>\r
	47	#include <Library/BaseMemoryLib.h>\r
	48	#include <Library/ReportStatusCodeLib.h>\r
	49	#include <Library/MemoryAllocationLib.h>\r
	50	#include <Library/UefiBootServicesTableLib.h>\r
	51	#include <Library/DevicePathLib.h>\r
	52	#include <Library/PcdLib.h>\r
e8ba34ff	53	#include <Library/PeCoffLib.h>\r
10590588	54	\r
	55	//\r
	56	// Driver Produced Protocol Prototypes\r
	57	//\r
	58	\r
	59	#define VGABASE1 0x3B0\r
	60	#define VGALIMIT1 0x3BB\r
	61	\r
	62	#define VGABASE2 0x3C0\r
	63	#define VGALIMIT2 0x3DF\r
	64	\r
	65	#define ISABASE 0x100\r
	66	#define ISALIMIT 0x3FF\r
	67	\r
	68	typedef enum {\r
	69	PciBarTypeUnknown = 0,\r
	70	PciBarTypeIo16,\r
	71	PciBarTypeIo32,\r
	72	PciBarTypeMem32,\r
	73	PciBarTypePMem32,\r
	74	PciBarTypeMem64,\r
	75	PciBarTypePMem64,\r
	76	PciBarTypeIo,\r
	77	PciBarTypeMem,\r
	78	PciBarTypeMaxType\r
	79	} PCI_BAR_TYPE;\r
	80	\r
	81	typedef struct {\r
	82	UINT64 BaseAddress;\r
	83	UINT64 Length;\r
	84	UINT64 Alignment;\r
	85	PCI_BAR_TYPE BarType;\r
	86	BOOLEAN Prefetchable;\r
	87	UINT8 MemType;\r
	88	UINT8 Offset;\r
	89	} PCI_BAR;\r
	90	\r
eea53ce1	91	#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p','c','i','o')\r
10590588	92	\r
	93	#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001 \r
	94	#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002 \r
	95	#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004 \r
	96	#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008 \r
	97	#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010 \r
	98	#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
	99	#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
	100	\r
	101	\r
	102	typedef struct _PCI_IO_DEVICE {\r
	103	UINT32 Signature;\r
	104	EFI_HANDLE Handle;\r
	105	EFI_PCI_IO_PROTOCOL PciIo;\r
	106	LIST_ENTRY Link;\r
	107	\r
	108	EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
	109	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	110	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
	111	\r
	112	//\r
	113	// PCI configuration space header type\r
	114	//\r
	115	PCI_TYPE00 Pci;\r
	116	\r
	117	//\r
	118	// Bus number, Device number, Function number\r
	119	//\r
	120	UINT8 BusNumber;\r
	121	UINT8 DeviceNumber;\r
	122	UINT8 FunctionNumber;\r
	123	\r
	124	//\r
	125	// BAR for this PCI Device\r
	126	//\r
	127	PCI_BAR PciBar[PCI_MAX_BAR];\r
	128	\r
	129	//\r
	130	// The bridge device this pci device is subject to\r
	131	//\r
	132	struct _PCI_IO_DEVICE *Parent;\r
	133	\r
	134	//\r
	135	// A linked list for children Pci Device if it is bridge device\r
	136	//\r
	137	LIST_ENTRY ChildList;\r
	138	\r
	139	//\r
34f5c234	140	// TRUE if the PCI bus driver creates the handle for this PCI device\r
10590588	141	//\r
	142	BOOLEAN Registered;\r
	143	\r
	144	//\r
	145	// TRUE if the PCI bus driver successfully allocates the resource required by\r
	146	// this PCI device\r
	147	//\r
	148	BOOLEAN Allocated;\r
	149	\r
	150	//\r
	151	// The attribute this PCI device currently set\r
	152	//\r
	153	UINT64 Attributes;\r
	154	\r
	155	//\r
	156	// The attributes this PCI device actually supports\r
	157	//\r
	158	UINT64 Supports;\r
	159	\r
	160	//\r
	161	// The resource decode the bridge supports\r
	162	//\r
	163	UINT32 Decodes;\r
	164	\r
	165	//\r
	166	// The OptionRom Size\r
	167	//\r
	168	UINT64 RomSize;\r
	169	\r
	170	//\r
	171	// TRUE if there is any EFI driver in the OptionRom\r
	172	//\r
	173	BOOLEAN BusOverride;\r
	174	\r
	175	//\r
	176	// A list tracking reserved resource on a bridge device\r
	177	//\r
	178	LIST_ENTRY ReservedResourceList;\r
	179	\r
	180	//\r
	181	// A list tracking image handle of platform specific overriding driver\r
	182	//\r
	183	LIST_ENTRY OptionRomDriverList;\r
	184	\r
	185	BOOLEAN IsPciExp;\r
	186	\r
	187	} PCI_IO_DEVICE;\r
	188	\r
	189	\r
	190	#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
	191	CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
	192	\r
	193	#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
	194	CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
	195	\r
	196	#define PCI_IO_DEVICE_FROM_LINK(a) \\r
	197	CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
	198	\r
	199	//\r
	200	// Global Variables\r
	201	//\r
03c11053	202	extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
03c11053	203	extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
10590588	204	extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
	205	\r
	206	extern BOOLEAN gFullEnumeration;\r
e56dd2ce	207	extern UINT64 gAllOne;\r
e56dd2ce	208	extern UINT64 gAllZero;\r
10590588	209	\r
	210	#include "PciIo.h"\r
	211	#include "PciCommand.h"\r
	212	#include "PciDeviceSupport.h"\r
	213	#include "PciEnumerator.h"\r
	214	#include "PciEnumeratorSupport.h"\r
	215	#include "PciDriverOverride.h"\r
	216	#include "PciRomTable.h"\r
	217	#include "PciOptionRomSupport.h"\r
	218	#include "PciPowerManagement.h"\r
	219	\r
	220	\r
bc14bdb3	221	#define IS_ISA_BRIDGE(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA) \r
bc14bdb3	222	#define IS_INTEL_ISA_BRIDGE(_p) (IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE) && ((_p)->Hdr.VendorId == 0x8086) && ((_p)->Hdr.DeviceId == 0x7110))\r
1833218d	223	#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
10590588	224	\r
10590588	225	#endif\r