DuetPkg: Fix EFIAPI usage inconsistencies

[mirror_edk2.git] / DuetPkg / PciRootBridgeNoEnumerationDxe / PcatPciRootBridge.h

/*++\r
\r
Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
  PcatPciRootBridge.h\r
\r
Abstract:\r
\r
  The driver for the host to pci bridge (root bridge).\r
\r
--*/\r
\r
#ifndef _PCAT_PCI_ROOT_BRIDGE_H_\r
#define _PCAT_PCI_ROOT_BRIDGE_H_\r
\r
#include <PiDxe.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/DeviceIo.h>\r
#include <Protocol/CpuIo2.h>\r
\r
#include <Library/UefiLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/HobLib.h>\r
\r
#include <Guid/PciOptionRomTable.h>\r
#include <Guid/HobList.h>\r
#include <Guid/PciExpressBaseAddress.h>\r
\r
#include <IndustryStandard/Acpi.h>\r
#include <IndustryStandard/Pci.h>\r
\r
#define PCI_MAX_SEGMENT   0\r
//\r
// Driver Instance Data Prototypes\r
//\r
#define PCAT_PCI_ROOT_BRIDGE_SIGNATURE  SIGNATURE_32('p', 'c', 'r', 'b')\r
\r
typedef struct {\r
  UINT32                            Signature;\r
  EFI_HANDLE                        Handle;\r
                                    \r
  EFI_DEVICE_PATH_PROTOCOL          *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL   Io;\r
  EFI_CPU_IO2_PROTOCOL              *CpuIo;\r
\r
  UINT32                            RootBridgeNumber;\r
  UINT32                            PrimaryBus;\r
  UINT32                            SubordinateBus;\r
                                     \r
  UINT64                            MemBase;     // Offsets host to bus memory addr.\r
  UINT64                            MemLimit;    // Max allowable memory access\r
                                    \r
  UINT64                            IoBase;      // Offsets host to bus io addr.\r
  UINT64                            IoLimit;     // Max allowable io access\r
                                    \r
  UINT64                            PciAddress;\r
  UINT64                            PciData;\r
                                    \r
  UINT64                            PhysicalMemoryBase;\r
  UINT64                            PhysicalIoBase;\r
                                     \r
  EFI_LOCK                          PciLock;\r
                                    \r
  UINT64                            Attributes;\r
                                    \r
  UINT64                            Mem32Base;\r
  UINT64                            Mem32Limit;\r
  UINT64                            Pmem32Base;\r
  UINT64                            Pmem32Limit;\r
  UINT64                            Mem64Base;\r
  UINT64                            Mem64Limit;\r
  UINT64                            Pmem64Base;\r
  UINT64                            Pmem64Limit;\r
\r
  UINT64                            PciExpressBaseAddress;\r
\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
\r
  LIST_ENTRY                    MapInfo;\r
} PCAT_PCI_ROOT_BRIDGE_INSTANCE;\r
\r
//\r
// Driver Instance Data Macros\r
//\r
#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
  CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE)\r
\r
//\r
// Private data types\r
//\r
typedef union {\r
  UINT8   volatile  *buf;\r
  UINT8   volatile  *ui8;\r
  UINT16  volatile  *ui16;\r
  UINT32  volatile  *ui32;\r
  UINT64  volatile  *ui64;\r
  UINTN   volatile  ui;\r
} PTR;\r
\r
typedef struct {\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation;\r
  UINTN                                      NumberOfBytes;\r
  UINTN                                      NumberOfPages;\r
  EFI_PHYSICAL_ADDRESS                       HostAddress;\r
  EFI_PHYSICAL_ADDRESS                       MappedHostAddress;\r
} MAP_INFO;\r
\r
typedef struct {\r
  LIST_ENTRY Link;\r
  MAP_INFO * Map;  \r
} MAP_INFO_INSTANCE;\r
\r
typedef\r
VOID\r
(*EFI_PCI_BUS_SCAN_CALLBACK) (\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
  UINT16                           MinBus,\r
  UINT16                           MaxBus,\r
  UINT16                           MinDevice,\r
  UINT16                           MaxDevice,\r
  UINT16                           MinFunc,\r
  UINT16                           MaxFunc,\r
  UINT16                           Bus,\r
  UINT16                           Device,\r
  UINT16                           Func,\r
  IN VOID                          *Context\r
  );\r
\r
typedef struct {\r
  UINT16                    *CommandRegisterBuffer;\r
  UINT32                    PpbMemoryWindow;     \r
} PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT;\r
\r
typedef struct {\r
  UINT8 Register;\r
  UINT8 Function;\r
  UINT8 Device;\r
  UINT8 Bus;\r
  UINT8 Reserved[4];\r
} DEFIO_PCI_ADDR;\r
\r
//\r
// Driver Protocol Constructor Prototypes\r
//\r
EFI_STATUS \r
ConstructConfiguration(\r
  IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE  *PrivateData\r
  );\r
\r
EFI_STATUS\r
PcatPciRootBridgeParseBars (\r
  IN PCAT_PCI_ROOT_BRIDGE_INSTANCE  *PrivateData,\r
  IN UINT16                         Command,\r
  IN UINTN                          Bus,\r
  IN UINTN                          Device,\r
  IN UINTN                          Function\r
  );\r
\r
EFI_STATUS\r
ScanPciRootBridgeForRoms(\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeDevicePathConstructor (\r
  IN EFI_DEVICE_PATH_PROTOCOL  **Protocol,\r
  IN UINTN                     RootBridgeNumber,\r
  IN BOOLEAN                   IsPciExpress\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeIoConstructor (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *Protocol,\r
  IN UINTN                            SegmentNumber\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeIoGetIoPortMapping (\r
  OUT EFI_PHYSICAL_ADDRESS  *IoPortMapping,\r
  OUT EFI_PHYSICAL_ADDRESS  *MemoryPortMapping\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeIoPciRW (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN BOOLEAN                                Write,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                                 UserAddress,\r
  IN UINTN                                  Count,\r
  IN OUT VOID                               *UserBuffer\r
  );\r
\r
UINT64\r
GetPciExpressBaseAddressForRootBridge (\r
  IN UINTN    HostBridgeNumber,\r
  IN UINTN    RootBridgeNumber\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
PcatRootBridgeIoIoRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 UserAddress,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *UserBuffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
PcatRootBridgeIoIoWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 UserAddress,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *UserBuffer\r
  );\r
\r
//\r
// Driver entry point prototype\r
//\r
EFI_STATUS\r
EFIAPI\r
InitializePcatPciRootBridge (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  );\r
\r
extern EFI_CPU_IO2_PROTOCOL  *gCpuIo;\r
\r
#endif\r