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[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Cpu / Pentium / Include / CpuIA32.h
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3eb9473e 1/*++\r
2\r
f57387d5
HT		 3Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r
4This program and the accompanying materials \r
3eb9473e 5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 CpuIA32.h\r
15\r
16Abstract:\r
17\r
18--*/\r
19\r
20#ifndef _CPU_IA32_H\r
21#define _CPU_IA32_H\r
22\r
23#include "Tiano.h"\r
24\r
3eb9473e 25typedef struct {\r
26 UINT32 RegEax;\r
27 UINT32 RegEbx;\r
28 UINT32 RegEcx;\r
29 UINT32 RegEdx;\r
30} EFI_CPUID_REGISTER;\r
31\r
32typedef struct {\r
33 UINT32 HeaderVersion;\r
34 UINT32 UpdateRevision;\r
35 UINT32 Date;\r
36 UINT32 ProcessorId;\r
37 UINT32 Checksum;\r
38 UINT32 LoaderRevision;\r
39 UINT32 ProcessorFlags;\r
40 UINT32 DataSize;\r
41 UINT32 TotalSize;\r
42 UINT8 Reserved[12];\r
43} EFI_CPU_MICROCODE_HEADER;\r
44\r
45typedef struct {\r
46 UINT32 ExtendedSignatureCount;\r
47 UINT32 ExtendedTableChecksum; \r
48 UINT8 Reserved[12];\r
49} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
50\r
51typedef struct {\r
52 UINT32 ProcessorSignature;\r
53 UINT32 ProcessorFlag;\r
54 UINT32 ProcessorChecksum;\r
55} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
56\r
57typedef struct {\r
58 UINT32 Stepping : 4;\r
59 UINT32 Model : 4;\r
60 UINT32 Family : 4;\r
61 UINT32 Type : 2;\r
62 UINT32 Reserved1 : 2;\r
63 UINT32 ExtendedModel : 4;\r
64 UINT32 ExtendedFamily : 8;\r
65 UINT32 Reserved2 : 4;\r
66} EFI_CPU_VERSION;\r
67\r
68#define EFI_CPUID_SIGNATURE 0x0\r
69#define EFI_CPUID_VERSION_INFO 0x1\r
70#define EFI_CPUID_CACHE_INFO 0x2\r
71#define EFI_CPUID_SERIAL_NUMBER 0x3\r
72#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r
73#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r
74#define EFI_CPUID_BRAND_STRING1 0x80000002\r
75#define EFI_CPUID_BRAND_STRING2 0x80000003\r
76#define EFI_CPUID_BRAND_STRING3 0x80000004\r
77\r
78#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
79#define EFI_MSR_IA32_APIC_BASE 0x1B\r
80#define EFI_MSR_EBC_HARD_POWERON 0x2A\r
81#define EFI_MSR_EBC_SOFT_POWERON 0x2B\r
82#define BINIT_DRIVER_DISABLE 0x40\r
83#define INTERNAL_MCERR_DISABLE 0x20\r
84#define INITIATOR_MCERR_DISABLE 0x10\r
85#define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r
86#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
87#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r
88#define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r
89#define EFI_APIC_GLOBAL_ENABLE 0x800\r
90#define EFI_MSR_IA32_MISC_ENABLE 0x1A0\r
91#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000\r
92#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008\r
93#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004\r
94#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r
95#define FAST_STRING_ENABLE_BIT 0x00000001\r
96\r
97#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r
98#define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r
99#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r
100#define EFI_CACHE_MTRR_VALID 0x800\r
101#define EFI_CACHE_FIXED_MTRR_VALID 0x400\r
102#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
103#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
104#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r
105#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF\r
106\r
107#define EFI_IA32_MTRR_FIX64K_00000 0x250\r
108#define EFI_IA32_MTRR_FIX16K_80000 0x258\r
109#define EFI_IA32_MTRR_FIX16K_A0000 0x259\r
110#define EFI_IA32_MTRR_FIX4K_C0000 0x268\r
111#define EFI_IA32_MTRR_FIX4K_C8000 0x269\r
112#define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r
113#define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r
114#define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r
115#define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r
116#define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r
117#define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r
118\r
119#define EFI_IA32_MCG_CAP 0x179\r
120#define EFI_IA32_MCG_CTL 0x17B\r
121#define EFI_IA32_MC0_CTL 0x400\r
122#define EFI_IA32_MC0_STATUS 0x401\r
123\r
124#define EFI_IA32_PERF_STATUS 0x198\r
125#define EFI_IA32_PERF_CTL 0x199\r
126\r
127#define EFI_CACHE_UNCACHEABLE 0\r
128#define EFI_CACHE_WRITECOMBINING 1\r
129#define EFI_CACHE_WRITETHROUGH 4\r
130#define EFI_CACHE_WRITEPROTECTED 5\r
131#define EFI_CACHE_WRITEBACK 6\r
132\r
133//\r
134// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r
135//\r
136#define EfiMakeCpuVersion(f, m, s) \\r
137 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))\r
138\r
139VOID\r
4798ea5b 140EFIAPI\r
3eb9473e 141EfiHalt (\r
142 VOID\r
e00e1d46 143 );\r
3eb9473e 144\r
145/*++ \r
146Routine Description: \r
147 Halt the Cpu \r
148Arguments: \r
149 None \r
150Returns: \r
151 None \r
152--*/\r
153VOID\r
4798ea5b 154EFIAPI\r
3eb9473e 155EfiWbinvd (\r
156 VOID\r
e00e1d46 157 );\r
3eb9473e 158\r
159/*++ \r
160Routine Description: \r
161 Write back and invalidate the Cpu cache\r
162Arguments: \r
163 None \r
164Returns: \r
165 None \r
166--*/\r
167VOID\r
4798ea5b 168EFIAPI\r
3eb9473e 169EfiInvd (\r
170 VOID\r
e00e1d46 171 );\r
3eb9473e 172\r
173/*++ \r
174Routine Description: \r
175 Invalidate the Cpu cache\r
176Arguments: \r
177 None \r
178Returns: \r
179 None \r
180--*/\r
181VOID\r
4798ea5b 182EFIAPI\r
3eb9473e 183EfiCpuid (\r
184 IN UINT32 RegisterInEax,\r
185 OUT EFI_CPUID_REGISTER *Regs\r
e00e1d46 186 );\r
3eb9473e 187\r
188/*++ \r
189Routine Description: \r
190 Get the Cpu info by excute the CPUID instruction\r
191Arguments: \r
192 RegisterInEax: -The input value to put into register EAX\r
193 Regs: -The Output value \r
194Returns: \r
195 None \r
196--*/\r
197\r
198VOID\r
4798ea5b 199EFIAPI\r
3eb9473e 200EfiCpuidExt (\r
201 IN UINT32 RegisterInEax,\r
202 IN UINT32 CacheLevel,\r
203 OUT EFI_CPUID_REGISTER *Regs\r
204 )\r
205/*++ \r
206Routine Description: \r
207 When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r
208 When RegisterInEax == 4, the function return the deterministic cache\r
209 parameters by excuting the CPUID instruction\r
210Arguments: \r
211 RegisterInEax: - The input value to put into register EAX\r
212 CacheLevel: - The deterministic cache level\r
213 Regs: - The Output value \r
214Returns: \r
215 None \r
216--*/\r
217;\r
218\r
219UINT64\r
4798ea5b 220EFIAPI\r
3eb9473e 221EfiReadMsr (\r
222 IN UINT32 Index\r
e00e1d46 223 );\r
3eb9473e 224\r
225/*++ \r
226Routine Description: \r
227 Read Cpu MSR\r
228Arguments: \r
229 Index: -The index value to select the register\r
230 \r
231Returns: \r
232 Return the read data \r
233--*/\r
234VOID\r
4798ea5b 235EFIAPI\r
3eb9473e 236EfiWriteMsr (\r
237 IN UINT32 Index,\r
238 IN UINT64 Value\r
e00e1d46 239 );\r
3eb9473e 240\r
241/*++ \r
242Routine Description: \r
243 Write Cpu MSR\r
244Arguments: \r
245 Index: -The index value to select the register\r
246 Value: -The value to write to the selected register \r
247Returns: \r
248 None \r
249--*/\r
250UINT64\r
4798ea5b 251EFIAPI\r
3eb9473e 252EfiReadTsc (\r
253 VOID\r
e00e1d46 254 );\r
3eb9473e 255\r
256/*++ \r
257Routine Description: \r
258 Read Time stamp\r
259Arguments: \r
260 None \r
261Returns: \r
262 Return the read data \r
263--*/\r
264VOID\r
4798ea5b 265EFIAPI\r
3eb9473e 266EfiDisableCache (\r
267 VOID\r
e00e1d46 268 );\r
3eb9473e 269\r
270/*++ \r
271Routine Description: \r
272 Writing back and invalidate the cache,then diable it\r
273Arguments: \r
274 None \r
275Returns: \r
276 None \r
277--*/\r
278VOID\r
4798ea5b 279EFIAPI\r
3eb9473e 280EfiEnableCache (\r
281 VOID\r
e00e1d46 282 );\r
3eb9473e 283\r
284/*++ \r
285Routine Description: \r
286 Invalidate the cache,then Enable it\r
287Arguments: \r
288 None \r
289Returns: \r
290 None \r
291--*/\r
292UINT32\r
4798ea5b 293EFIAPI\r
3eb9473e 294EfiGetEflags (\r
295 VOID\r
e00e1d46 296 );\r
3eb9473e 297\r
298/*++ \r
299Routine Description: \r
300 Get Eflags\r
301Arguments: \r
302 None \r
303Returns: \r
304 Return the Eflags value \r
305--*/\r
306VOID\r
4798ea5b 307EFIAPI\r
3eb9473e 308EfiDisableInterrupts (\r
309 VOID\r
e00e1d46 310 );\r
3eb9473e 311\r
312/*++ \r
313Routine Description: \r
314 Disable Interrupts\r
315Arguments: \r
316 None \r
317Returns: \r
318 None\r
319--*/\r
320VOID\r
4798ea5b 321EFIAPI\r
3eb9473e 322EfiEnableInterrupts (\r
323 VOID\r
e00e1d46 324 );\r
3eb9473e 325\r
326/*++ \r
327Routine Description: \r
328 Enable Interrupts\r
329Arguments: \r
330 None \r
331Returns: \r
332 None \r
333--*/\r
334\r
335\r
336VOID\r
4798ea5b 337EFIAPI\r
3eb9473e 338EfiCpuVersion (\r
339 IN UINT16 *FamilyId, OPTIONAL\r
340 IN UINT8 *Model, OPTIONAL\r
341 IN UINT8 *SteppingId, OPTIONAL\r
342 IN UINT8 *Processor OPTIONAL\r
343 )\r
344/*++\r
345\r
346Routine Description:\r
347 Extract CPU detail version infomation\r
348\r
349Arguments:\r
350 FamilyId - FamilyId, including ExtendedFamilyId\r
351 Model - Model, including ExtendedModel\r
352 SteppingId - SteppingId\r
353 Processor - Processor\r
354\r
355--*/\r
356;\r
357\r
358#endif\r
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