[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Efi / Protocol / DebugSupport / DebugSupport.h

/*++\r
\r
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
\r
  DebugSupport.h\r
\r
Abstract:\r
\r
  DebugSupport protocol and supporting definitions as defined in the EFI 1.1\r
  specification.\r
  \r
  The DebugSupport protocol is used by source level debuggers to abstract the\r
  processor and handle context save and restore operations.\r
 \r
--*/\r
\r
#ifndef _DEBUG_SUPPORT_H_\r
#define _DEBUG_SUPPORT_H_\r
\r
#include "EfiApi.h"\r
#include "EfiImage.h"\r
//\r
// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
//\r
#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
  { \\r
    0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25} \\r
  }\r
\r
//\r
// Debug Support definitions\r
//\r
typedef INTN  EFI_EXCEPTION_TYPE;\r
\r
//\r
//  IA-32 processor exception types\r
//\r
#define EXCEPT_IA32_DIVIDE_ERROR    0\r
#define EXCEPT_IA32_DEBUG           1\r
#define EXCEPT_IA32_NMI             2\r
#define EXCEPT_IA32_BREAKPOINT      3\r
#define EXCEPT_IA32_OVERFLOW        4\r
#define EXCEPT_IA32_BOUND           5\r
#define EXCEPT_IA32_INVALID_OPCODE  6\r
#define EXCEPT_IA32_DOUBLE_FAULT    8\r
#define EXCEPT_IA32_INVALID_TSS     10\r
#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
#define EXCEPT_IA32_STACK_FAULT     12\r
#define EXCEPT_IA32_GP_FAULT        13\r
#define EXCEPT_IA32_PAGE_FAULT      14\r
#define EXCEPT_IA32_FP_ERROR        16\r
#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
#define EXCEPT_IA32_MACHINE_CHECK   18\r
#define EXCEPT_IA32_SIMD            19\r
\r
//\r
//  IA-32 processor context definition\r
//\r
//\r
// FXSAVE_STATE\r
// FP / MMX / XMM registers (see fxrstor instruction definition)\r
//\r
typedef struct {\r
  UINT16  Fcw;\r
  UINT16  Fsw;\r
  UINT16  Ftw;\r
  UINT16  Opcode;\r
  UINT32  Eip;\r
  UINT16  Cs;\r
  UINT16  Reserved1;\r
  UINT32  DataOffset;\r
  UINT16  Ds;\r
  UINT8   Reserved2[10];\r
#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
  UINT8   St0Mm0[10], Reserved3[6];\r
  UINT8   St1Mm1[10], Reserved4[6];\r
  UINT8   St2Mm2[10], Reserved5[6];\r
  UINT8   St3Mm3[10], Reserved6[6];\r
  UINT8   St4Mm4[10], Reserved7[6];\r
  UINT8   St5Mm5[10], Reserved8[6];\r
  UINT8   St6Mm6[10], Reserved9[6];\r
  UINT8   St7Mm7[10], Reserved10[6];\r
  UINT8   Xmm0[16];\r
  UINT8   Xmm1[16];\r
  UINT8   Xmm2[16];\r
  UINT8   Xmm3[16];\r
  UINT8   Xmm4[16];\r
  UINT8   Xmm5[16];\r
  UINT8   Xmm6[16];\r
  UINT8   Xmm7[16];\r
  UINT8   Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_IA32;\r
#else\r
  UINT8   St0Mm0[10], Reserved3[6];\r
  UINT8   St0Mm1[10], Reserved4[6];\r
  UINT8   St0Mm2[10], Reserved5[6];\r
  UINT8   St0Mm3[10], Reserved6[6];\r
  UINT8   St0Mm4[10], Reserved7[6];\r
  UINT8   St0Mm5[10], Reserved8[6];\r
  UINT8   St0Mm6[10], Reserved9[6];\r
  UINT8   St0Mm7[10], Reserved10[6];\r
  UINT8   Reserved11[22 * 16];\r
} EFI_FX_SAVE_STATE;\r
#endif\r
\r
typedef struct {\r
  UINT32                 ExceptionData;\r
#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
  EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
#else\r
  EFI_FX_SAVE_STATE      FxSaveState;\r
#endif\r
  UINT32                 Dr0;\r
  UINT32                 Dr1;\r
  UINT32                 Dr2;\r
  UINT32                 Dr3;\r
  UINT32                 Dr6;\r
  UINT32                 Dr7;\r
  UINT32                 Cr0;\r
  UINT32                 Cr1;  /* Reserved */\r
  UINT32                 Cr2;\r
  UINT32                 Cr3;\r
  UINT32                 Cr4;\r
  UINT32                 Eflags;\r
  UINT32                 Ldtr;\r
  UINT32                 Tr;\r
  UINT32                 Gdtr[2];\r
  UINT32                 Idtr[2];\r
  UINT32                 Eip;\r
  UINT32                 Gs;\r
  UINT32                 Fs;\r
  UINT32                 Es;\r
  UINT32                 Ds;\r
  UINT32                 Cs;\r
  UINT32                 Ss;\r
  UINT32                 Edi;\r
  UINT32                 Esi;\r
  UINT32                 Ebp;\r
  UINT32                 Esp;\r
  UINT32                 Ebx;\r
  UINT32                 Edx;\r
  UINT32                 Ecx;\r
  UINT32                 Eax;\r
} EFI_SYSTEM_CONTEXT_IA32;\r
\r
//\r
//  X64 processor exception types\r
//\r
#define EXCEPT_X64_DIVIDE_ERROR    0\r
#define EXCEPT_X64_DEBUG           1\r
#define EXCEPT_X64_NMI             2\r
#define EXCEPT_X64_BREAKPOINT      3\r
#define EXCEPT_X64_OVERFLOW        4\r
#define EXCEPT_X64_BOUND           5\r
#define EXCEPT_X64_INVALID_OPCODE  6\r
#define EXCEPT_X64_DOUBLE_FAULT    8\r
#define EXCEPT_X64_INVALID_TSS     10\r
#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
#define EXCEPT_X64_STACK_FAULT     12\r
#define EXCEPT_X64_GP_FAULT        13\r
#define EXCEPT_X64_PAGE_FAULT      14\r
#define EXCEPT_X64_FP_ERROR        16\r
#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
#define EXCEPT_X64_MACHINE_CHECK   18\r
#define EXCEPT_X64_SIMD            19\r
\r
//\r
//  X64 processor context definition\r
//\r
// FXSAVE_STATE\r
// FP / MMX / XMM registers (see fxrstor instruction definition)\r
//\r
typedef struct {\r
  UINT16  Fcw;\r
  UINT16  Fsw;\r
  UINT16  Ftw;\r
  UINT16  Opcode;\r
  UINT64  Rip;\r
  UINT64  DataOffset;\r
  UINT8   Reserved1[8];\r
  UINT8   St0Mm0[10], Reserved2[6];\r
  UINT8   St1Mm1[10], Reserved3[6];\r
  UINT8   St2Mm2[10], Reserved4[6];\r
  UINT8   St3Mm3[10], Reserved5[6];\r
  UINT8   St4Mm4[10], Reserved6[6];\r
  UINT8   St5Mm5[10], Reserved7[6];\r
  UINT8   St6Mm6[10], Reserved8[6];\r
  UINT8   St7Mm7[10], Reserved9[6];\r
  UINT8   Xmm0[16];\r
  UINT8   Xmm1[16];\r
  UINT8   Xmm2[16];\r
  UINT8   Xmm3[16];\r
  UINT8   Xmm4[16];\r
  UINT8   Xmm5[16];\r
  UINT8   Xmm6[16];\r
  UINT8   Xmm7[16];\r
#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
  //\r
  // NOTE: UEFI 2.0 spec definition as follows. It should be updated \r
  // after spec update.\r
  //\r
  UINT8   Reserved11[14 * 16];\r
#else\r
  UINT8   Xmm8[16];\r
  UINT8   Xmm9[16];\r
  UINT8   Xmm10[16];\r
  UINT8   Xmm11[16];\r
  UINT8   Xmm12[16];\r
  UINT8   Xmm13[16];\r
  UINT8   Xmm14[16];\r
  UINT8   Xmm15[16];\r
  UINT8   Reserved10[6 * 16];\r
#endif\r
} EFI_FX_SAVE_STATE_X64;\r
\r
typedef struct {\r
  UINT64                ExceptionData;\r
  EFI_FX_SAVE_STATE_X64 FxSaveState;\r
  UINT64                Dr0;\r
  UINT64                Dr1;\r
  UINT64                Dr2;\r
  UINT64                Dr3;\r
  UINT64                Dr6;\r
  UINT64                Dr7;\r
  UINT64                Cr0;\r
  UINT64                Cr1;  /* Reserved */\r
  UINT64                Cr2;\r
  UINT64                Cr3;\r
  UINT64                Cr4;\r
  UINT64                Cr8;\r
  UINT64                Rflags;\r
  UINT64                Ldtr;\r
  UINT64                Tr;\r
  UINT64                Gdtr[2];\r
  UINT64                Idtr[2];\r
  UINT64                Rip;\r
  UINT64                Gs;\r
  UINT64                Fs;\r
  UINT64                Es;\r
  UINT64                Ds;\r
  UINT64                Cs;\r
  UINT64                Ss;\r
  UINT64                Rdi;\r
  UINT64                Rsi;\r
  UINT64                Rbp;\r
  UINT64                Rsp;\r
  UINT64                Rbx;\r
  UINT64                Rdx;\r
  UINT64                Rcx;\r
  UINT64                Rax;\r
  UINT64                R8;\r
  UINT64                R9;\r
  UINT64                R10;\r
  UINT64                R11;\r
  UINT64                R12;\r
  UINT64                R13;\r
  UINT64                R14;\r
  UINT64                R15;\r
} EFI_SYSTEM_CONTEXT_X64;\r
\r
//\r
//  IPF processor exception types\r
//\r
#define EXCEPT_IPF_VHTP_TRANSLATION       0\r
#define EXCEPT_IPF_INSTRUCTION_TLB        1\r
#define EXCEPT_IPF_DATA_TLB               2\r
#define EXCEPT_IPF_ALT_INSTRUCTION_TLB    3\r
#define EXCEPT_IPF_ALT_DATA_TLB           4\r
#define EXCEPT_IPF_DATA_NESTED_TLB        5\r
#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
#define EXCEPT_IPF_DATA_KEY_MISSED        7\r
#define EXCEPT_IPF_DIRTY_BIT              8\r
#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
#define EXCEPT_IPF_DATA_ACCESS_BIT        10\r
#define EXCEPT_IPF_BREAKPOINT             11\r
#define EXCEPT_IPF_EXTERNAL_INTERRUPT     12\r
//\r
// 13 - 19 reserved\r
//\r
#define EXCEPT_IPF_PAGE_NOT_PRESENT           20\r
#define EXCEPT_IPF_KEY_PERMISSION             21\r
#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS  22\r
#define EXCEPT_IPF_DATA_ACCESS_RIGHTS         23\r
#define EXCEPT_IPF_GENERAL_EXCEPTION          24\r
#define EXCEPT_IPF_DISABLED_FP_REGISTER       25\r
#define EXCEPT_IPF_NAT_CONSUMPTION            26\r
#define EXCEPT_IPF_SPECULATION                27\r
//\r
// 28 reserved\r
//\r
#define EXCEPT_IPF_DEBUG                          29\r
#define EXCEPT_IPF_UNALIGNED_REFERENCE            30\r
#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE     31\r
#define EXCEPT_IPF_FP_FAULT                       32\r
#define EXCEPT_IPF_FP_TRAP                        33\r
#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP  34\r
#define EXCEPT_IPF_TAKEN_BRANCH                   35\r
#define EXCEPT_IPF_SINGLE_STEP                    36\r
//\r
// 37 - 44 reserved\r
//\r
#define EXCEPT_IPF_IA32_EXCEPTION 45\r
#define EXCEPT_IPF_IA32_INTERCEPT 46\r
#define EXCEPT_IPF_IA32_INTERRUPT 47\r
\r
//\r
//  IPF processor context definition\r
//\r
typedef struct {\r
  //\r
  // The first reserved field is necessary to preserve alignment for the correct\r
  // bits in UNAT and to insure F2 is 16 byte aligned..\r
  //\r
  UINT64  Reserved;\r
  UINT64  R1;\r
  UINT64  R2;\r
  UINT64  R3;\r
  UINT64  R4;\r
  UINT64  R5;\r
  UINT64  R6;\r
  UINT64  R7;\r
  UINT64  R8;\r
  UINT64  R9;\r
  UINT64  R10;\r
  UINT64  R11;\r
  UINT64  R12;\r
  UINT64  R13;\r
  UINT64  R14;\r
  UINT64  R15;\r
  UINT64  R16;\r
  UINT64  R17;\r
  UINT64  R18;\r
  UINT64  R19;\r
  UINT64  R20;\r
  UINT64  R21;\r
  UINT64  R22;\r
  UINT64  R23;\r
  UINT64  R24;\r
  UINT64  R25;\r
  UINT64  R26;\r
  UINT64  R27;\r
  UINT64  R28;\r
  UINT64  R29;\r
  UINT64  R30;\r
  UINT64  R31;\r
\r
  UINT64  F2[2];\r
  UINT64  F3[2];\r
  UINT64  F4[2];\r
  UINT64  F5[2];\r
  UINT64  F6[2];\r
  UINT64  F7[2];\r
  UINT64  F8[2];\r
  UINT64  F9[2];\r
  UINT64  F10[2];\r
  UINT64  F11[2];\r
  UINT64  F12[2];\r
  UINT64  F13[2];\r
  UINT64  F14[2];\r
  UINT64  F15[2];\r
  UINT64  F16[2];\r
  UINT64  F17[2];\r
  UINT64  F18[2];\r
  UINT64  F19[2];\r
  UINT64  F20[2];\r
  UINT64  F21[2];\r
  UINT64  F22[2];\r
  UINT64  F23[2];\r
  UINT64  F24[2];\r
  UINT64  F25[2];\r
  UINT64  F26[2];\r
  UINT64  F27[2];\r
  UINT64  F28[2];\r
  UINT64  F29[2];\r
  UINT64  F30[2];\r
  UINT64  F31[2];\r
\r
  UINT64  Pr;\r
\r
  UINT64  B0;\r
  UINT64  B1;\r
  UINT64  B2;\r
  UINT64  B3;\r
  UINT64  B4;\r
  UINT64  B5;\r
  UINT64  B6;\r
  UINT64  B7;\r
\r
  //\r
  // application registers\r
  //\r
  UINT64  ArRsc;\r
  UINT64  ArBsp;\r
  UINT64  ArBspstore;\r
  UINT64  ArRnat;\r
\r
  UINT64  ArFcr;\r
\r
  UINT64  ArEflag;\r
  UINT64  ArCsd;\r
  UINT64  ArSsd;\r
  UINT64  ArCflg;\r
  UINT64  ArFsr;\r
  UINT64  ArFir;\r
  UINT64  ArFdr;\r
\r
  UINT64  ArCcv;\r
\r
  UINT64  ArUnat;\r
\r
  UINT64  ArFpsr;\r
\r
  UINT64  ArPfs;\r
  UINT64  ArLc;\r
  UINT64  ArEc;\r
\r
  //\r
  // control registers\r
  //\r
  UINT64  CrDcr;\r
  UINT64  CrItm;\r
  UINT64  CrIva;\r
  UINT64  CrPta;\r
  UINT64  CrIpsr;\r
  UINT64  CrIsr;\r
  UINT64  CrIip;\r
  UINT64  CrIfa;\r
  UINT64  CrItir;\r
  UINT64  CrIipa;\r
  UINT64  CrIfs;\r
  UINT64  CrIim;\r
  UINT64  CrIha;\r
\r
  //\r
  // debug registers\r
  //\r
  UINT64  Dbr0;\r
  UINT64  Dbr1;\r
  UINT64  Dbr2;\r
  UINT64  Dbr3;\r
  UINT64  Dbr4;\r
  UINT64  Dbr5;\r
  UINT64  Dbr6;\r
  UINT64  Dbr7;\r
\r
  UINT64  Ibr0;\r
  UINT64  Ibr1;\r
  UINT64  Ibr2;\r
  UINT64  Ibr3;\r
  UINT64  Ibr4;\r
  UINT64  Ibr5;\r
  UINT64  Ibr6;\r
  UINT64  Ibr7;\r
\r
  //\r
  // virtual registers - nat bits for R1-R31\r
  //\r
  UINT64  IntNat;\r
\r
} EFI_SYSTEM_CONTEXT_IPF;\r
\r
//\r
//  EBC processor exception types\r
//\r
#define EXCEPT_EBC_UNDEFINED            0\r
#define EXCEPT_EBC_DIVIDE_ERROR         1\r
#define EXCEPT_EBC_DEBUG                2\r
#define EXCEPT_EBC_BREAKPOINT           3\r
#define EXCEPT_EBC_OVERFLOW             4\r
#define EXCEPT_EBC_INVALID_OPCODE       5   // opcode out of range\r
#define EXCEPT_EBC_STACK_FAULT          6\r
#define EXCEPT_EBC_ALIGNMENT_CHECK      7\r
#define EXCEPT_EBC_INSTRUCTION_ENCODING 8   // malformed instruction\r
#define EXCEPT_EBC_BAD_BREAK            9   // BREAK 0 or undefined BREAK\r
#define EXCEPT_EBC_STEP                 10  // to support debug stepping\r
//\r
// For coding convenience, define the maximum valid EBC exception.\r
//\r
#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
\r
//\r
//  EBC processor context definition\r
//\r
typedef struct {\r
  UINT64  R0;\r
  UINT64  R1;\r
  UINT64  R2;\r
  UINT64  R3;\r
  UINT64  R4;\r
  UINT64  R5;\r
  UINT64  R6;\r
  UINT64  R7;\r
  UINT64  Flags;\r
  UINT64  ControlFlags;\r
  UINT64  Ip;\r
} EFI_SYSTEM_CONTEXT_EBC;\r
\r
//\r
// Universal EFI_SYSTEM_CONTEXT definition\r
//\r
typedef union {\r
  EFI_SYSTEM_CONTEXT_EBC  *SystemContextEbc;\r
  EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
  EFI_SYSTEM_CONTEXT_X64  *SystemContextX64;\r
  EFI_SYSTEM_CONTEXT_IPF  *SystemContextIpf;\r
} EFI_SYSTEM_CONTEXT;\r
\r
//\r
// DebugSupport callback function prototypes\r
//\r
typedef\r
VOID\r
(*EFI_EXCEPTION_CALLBACK) (\r
  IN     EFI_EXCEPTION_TYPE               ExceptionType,\r
  IN OUT EFI_SYSTEM_CONTEXT               SystemContext\r
  );\r
\r
typedef\r
VOID\r
(*EFI_PERIODIC_CALLBACK) (\r
  IN OUT EFI_SYSTEM_CONTEXT               SystemContext\r
  );\r
\r
//\r
// Machine type definition\r
//\r
typedef enum {\r
  IsaIa32 = EFI_IMAGE_MACHINE_IA32,\r
  IsaX64  = EFI_IMAGE_MACHINE_X64,\r
  IsaIpf  = EFI_IMAGE_MACHINE_IA64,\r
  IsaEbc  = EFI_IMAGE_MACHINE_EBC\r
} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
\r
EFI_FORWARD_DECLARATION (EFI_DEBUG_SUPPORT_PROTOCOL);\r
\r
//\r
// DebugSupport member function definitions\r
//\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX) (\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          * This,\r
  OUT UINTN                              *MaxProcessorIndex\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK) (\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          * This,\r
  IN UINTN                               ProcessorIndex,\r
  IN EFI_PERIODIC_CALLBACK               PeriodicCallback\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK) (\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          * This,\r
  IN UINTN                               ProcessorIndex,\r
  IN EFI_EXCEPTION_CALLBACK              ExceptionCallback,\r
  IN EFI_EXCEPTION_TYPE                  ExceptionType\r
  );\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE) (\r
  IN EFI_DEBUG_SUPPORT_PROTOCOL          * This,\r
  IN UINTN                               ProcessorIndex,\r
  IN VOID                                *Start,\r
  IN UINT64                              Length\r
  );\r
\r
//\r
// DebugSupport protocol definition\r
//\r
struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
  EFI_INSTRUCTION_SET_ARCHITECTURE  Isa;\r
  EFI_GET_MAXIMUM_PROCESSOR_INDEX   GetMaximumProcessorIndex;\r
  EFI_REGISTER_PERIODIC_CALLBACK    RegisterPeriodicCallback;\r
  EFI_REGISTER_EXCEPTION_CALLBACK   RegisterExceptionCallback;\r
  EFI_INVALIDATE_INSTRUCTION_CACHE  InvalidateInstructionCache;\r
};\r
\r
extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
\r
#endif /* _DEBUG_SUPPORT_H_ */\r
Commit	Line	Data
3eb9473e	1	/*++\r
3eb9473e	2	\r
f57387d5 HT	3	Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r
f57387d5 HT	4	This program and the accompanying materials \r
3eb9473e	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	\r
	14	DebugSupport.h\r
	15	\r
	16	Abstract:\r
	17	\r
	18	DebugSupport protocol and supporting definitions as defined in the EFI 1.1\r
	19	specification.\r
	20	\r
	21	The DebugSupport protocol is used by source level debuggers to abstract the\r
	22	processor and handle context save and restore operations.\r
	23	\r
	24	--*/\r
	25	\r
	26	#ifndef _DEBUG_SUPPORT_H_\r
	27	#define _DEBUG_SUPPORT_H_\r
	28	\r
	29	#include "EfiApi.h"\r
	30	#include "EfiImage.h"\r
	31	//\r
	32	// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}\r
	33	//\r
	34	#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
	35	{ \\r
7ccf38a3	36	0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25} \\r
3eb9473e	37	}\r
	38	\r
	39	//\r
	40	// Debug Support definitions\r
	41	//\r
	42	typedef INTN EFI_EXCEPTION_TYPE;\r
	43	\r
	44	//\r
	45	// IA-32 processor exception types\r
	46	//\r
	47	#define EXCEPT_IA32_DIVIDE_ERROR 0\r
	48	#define EXCEPT_IA32_DEBUG 1\r
	49	#define EXCEPT_IA32_NMI 2\r
	50	#define EXCEPT_IA32_BREAKPOINT 3\r
	51	#define EXCEPT_IA32_OVERFLOW 4\r
	52	#define EXCEPT_IA32_BOUND 5\r
	53	#define EXCEPT_IA32_INVALID_OPCODE 6\r
	54	#define EXCEPT_IA32_DOUBLE_FAULT 8\r
	55	#define EXCEPT_IA32_INVALID_TSS 10\r
	56	#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
	57	#define EXCEPT_IA32_STACK_FAULT 12\r
	58	#define EXCEPT_IA32_GP_FAULT 13\r
	59	#define EXCEPT_IA32_PAGE_FAULT 14\r
	60	#define EXCEPT_IA32_FP_ERROR 16\r
	61	#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
	62	#define EXCEPT_IA32_MACHINE_CHECK 18\r
	63	#define EXCEPT_IA32_SIMD 19\r
	64	\r
	65	//\r
	66	// IA-32 processor context definition\r
	67	//\r
	68	//\r
	69	// FXSAVE_STATE\r
	70	// FP / MMX / XMM registers (see fxrstor instruction definition)\r
	71	//\r
	72	typedef struct {\r
	73	UINT16 Fcw;\r
	74	UINT16 Fsw;\r
	75	UINT16 Ftw;\r
	76	UINT16 Opcode;\r
	77	UINT32 Eip;\r
	78	UINT16 Cs;\r
	79	UINT16 Reserved1;\r
	80	UINT32 DataOffset;\r
	81	UINT16 Ds;\r
	82	UINT8 Reserved2[10];\r
	83	#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
	84	UINT8 St0Mm0[10], Reserved3[6];\r
	85	UINT8 St1Mm1[10], Reserved4[6];\r
	86	UINT8 St2Mm2[10], Reserved5[6];\r
	87	UINT8 St3Mm3[10], Reserved6[6];\r
	88	UINT8 St4Mm4[10], Reserved7[6];\r
	89	UINT8 St5Mm5[10], Reserved8[6];\r
	90	UINT8 St6Mm6[10], Reserved9[6];\r
	91	UINT8 St7Mm7[10], Reserved10[6];\r
	92	UINT8 Xmm0[16];\r
	93	UINT8 Xmm1[16];\r
	94	UINT8 Xmm2[16];\r
	95	UINT8 Xmm3[16];\r
	96	UINT8 Xmm4[16];\r
	97	UINT8 Xmm5[16];\r
	98	UINT8 Xmm6[16];\r
	99	UINT8 Xmm7[16];\r
	100	UINT8 Reserved11[14 * 16];\r
101	} EFI_FX_SAVE_STATE_IA32;\r
102	#else\r
103	UINT8 St0Mm0[10], Reserved3[6];\r
104	UINT8 St0Mm1[10], Reserved4[6];\r
105	UINT8 St0Mm2[10], Reserved5[6];\r
106	UINT8 St0Mm3[10], Reserved6[6];\r
107	UINT8 St0Mm4[10], Reserved7[6];\r
108	UINT8 St0Mm5[10], Reserved8[6];\r
109	UINT8 St0Mm6[10], Reserved9[6];\r
110	UINT8 St0Mm7[10], Reserved10[6];\r
111	UINT8 Reserved11[22 * 16];\r
112	} EFI_FX_SAVE_STATE;\r
113	#endif\r
114	\r
115	typedef struct {\r
116	UINT32 ExceptionData;\r
117	#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
118	EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
119	#else\r
120	EFI_FX_SAVE_STATE FxSaveState;\r
121	#endif\r
122	UINT32 Dr0;\r
123	UINT32 Dr1;\r
124	UINT32 Dr2;\r
125	UINT32 Dr3;\r
126	UINT32 Dr6;\r
127	UINT32 Dr7;\r
128	UINT32 Cr0;\r
129	UINT32 Cr1; /* Reserved */\r
130	UINT32 Cr2;\r
131	UINT32 Cr3;\r
132	UINT32 Cr4;\r
133	UINT32 Eflags;\r
134	UINT32 Ldtr;\r
135	UINT32 Tr;\r
136	UINT32 Gdtr[2];\r
137	UINT32 Idtr[2];\r
138	UINT32 Eip;\r
139	UINT32 Gs;\r
140	UINT32 Fs;\r
141	UINT32 Es;\r
142	UINT32 Ds;\r
143	UINT32 Cs;\r
144	UINT32 Ss;\r
145	UINT32 Edi;\r
146	UINT32 Esi;\r
147	UINT32 Ebp;\r
148	UINT32 Esp;\r
149	UINT32 Ebx;\r
150	UINT32 Edx;\r
151	UINT32 Ecx;\r
152	UINT32 Eax;\r
153	} EFI_SYSTEM_CONTEXT_IA32;\r
154	\r
155	//\r
156	// X64 processor exception types\r
157	//\r
158	#define EXCEPT_X64_DIVIDE_ERROR 0\r
159	#define EXCEPT_X64_DEBUG 1\r
160	#define EXCEPT_X64_NMI 2\r
161	#define EXCEPT_X64_BREAKPOINT 3\r
162	#define EXCEPT_X64_OVERFLOW 4\r
163	#define EXCEPT_X64_BOUND 5\r
164	#define EXCEPT_X64_INVALID_OPCODE 6\r
165	#define EXCEPT_X64_DOUBLE_FAULT 8\r
166	#define EXCEPT_X64_INVALID_TSS 10\r
167	#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
168	#define EXCEPT_X64_STACK_FAULT 12\r
169	#define EXCEPT_X64_GP_FAULT 13\r
170	#define EXCEPT_X64_PAGE_FAULT 14\r
171	#define EXCEPT_X64_FP_ERROR 16\r
172	#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
173	#define EXCEPT_X64_MACHINE_CHECK 18\r
174	#define EXCEPT_X64_SIMD 19\r
175	\r
176	//\r
177	// X64 processor context definition\r
178	//\r
179	// FXSAVE_STATE\r
180	// FP / MMX / XMM registers (see fxrstor instruction definition)\r
181	//\r
182	typedef struct {\r
183	UINT16 Fcw;\r
184	UINT16 Fsw;\r
185	UINT16 Ftw;\r
186	UINT16 Opcode;\r
187	UINT64 Rip;\r
188	UINT64 DataOffset;\r
189	UINT8 Reserved1[8];\r
190	UINT8 St0Mm0[10], Reserved2[6];\r
191	UINT8 St1Mm1[10], Reserved3[6];\r
192	UINT8 St2Mm2[10], Reserved4[6];\r
193	UINT8 St3Mm3[10], Reserved5[6];\r
194	UINT8 St4Mm4[10], Reserved6[6];\r
195	UINT8 St5Mm5[10], Reserved7[6];\r
196	UINT8 St6Mm6[10], Reserved8[6];\r
197	UINT8 St7Mm7[10], Reserved9[6];\r
198	UINT8 Xmm0[16];\r
199	UINT8 Xmm1[16];\r
200	UINT8 Xmm2[16];\r
201	UINT8 Xmm3[16];\r
202	UINT8 Xmm4[16];\r
203	UINT8 Xmm5[16];\r
204	UINT8 Xmm6[16];\r
205	UINT8 Xmm7[16];\r
206	#if (EFI_SPECIFICATION_VERSION >= 0x00020000)\r
207	//\r
208	// NOTE: UEFI 2.0 spec definition as follows. It should be updated \r
209	// after spec update.\r
210	//\r
211	UINT8 Reserved11[14 * 16];\r
212	#else\r
213	UINT8 Xmm8[16];\r
214	UINT8 Xmm9[16];\r
215	UINT8 Xmm10[16];\r
216	UINT8 Xmm11[16];\r
217	UINT8 Xmm12[16];\r
218	UINT8 Xmm13[16];\r
219	UINT8 Xmm14[16];\r
220	UINT8 Xmm15[16];\r
221	UINT8 Reserved10[6 * 16];\r
222	#endif\r
223	} EFI_FX_SAVE_STATE_X64;\r
224	\r
225	typedef struct {\r
226	UINT64 ExceptionData;\r
227	EFI_FX_SAVE_STATE_X64 FxSaveState;\r
228	UINT64 Dr0;\r
229	UINT64 Dr1;\r
230	UINT64 Dr2;\r
231	UINT64 Dr3;\r
232	UINT64 Dr6;\r
233	UINT64 Dr7;\r
234	UINT64 Cr0;\r
235	UINT64 Cr1; /* Reserved */\r
236	UINT64 Cr2;\r
237	UINT64 Cr3;\r
238	UINT64 Cr4;\r
239	UINT64 Cr8;\r
240	UINT64 Rflags;\r
241	UINT64 Ldtr;\r
242	UINT64 Tr;\r
243	UINT64 Gdtr[2];\r
244	UINT64 Idtr[2];\r
245	UINT64 Rip;\r
246	UINT64 Gs;\r
247	UINT64 Fs;\r
248	UINT64 Es;\r
249	UINT64 Ds;\r
250	UINT64 Cs;\r
251	UINT64 Ss;\r
252	UINT64 Rdi;\r
253	UINT64 Rsi;\r
254	UINT64 Rbp;\r
255	UINT64 Rsp;\r
256	UINT64 Rbx;\r
257	UINT64 Rdx;\r
258	UINT64 Rcx;\r
259	UINT64 Rax;\r
260	UINT64 R8;\r
261	UINT64 R9;\r
262	UINT64 R10;\r
263	UINT64 R11;\r
264	UINT64 R12;\r
265	UINT64 R13;\r
266	UINT64 R14;\r
267	UINT64 R15;\r
268	} EFI_SYSTEM_CONTEXT_X64;\r
269	\r
270	//\r
271	// IPF processor exception types\r
272	//\r
273	#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
274	#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
275	#define EXCEPT_IPF_DATA_TLB 2\r
276	#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
277	#define EXCEPT_IPF_ALT_DATA_TLB 4\r
278	#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
279	#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
280	#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
281	#define EXCEPT_IPF_DIRTY_BIT 8\r
282	#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
283	#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
284	#define EXCEPT_IPF_BREAKPOINT 11\r
285	#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
286	//\r
287	// 13 - 19 reserved\r
288	//\r
289	#define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r
290	#define EXCEPT_IPF_KEY_PERMISSION 21\r
291	#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r
292	#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r
293	#define EXCEPT_IPF_GENERAL_EXCEPTION 24\r
294	#define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r
295	#define EXCEPT_IPF_NAT_CONSUMPTION 26\r
296	#define EXCEPT_IPF_SPECULATION 27\r
297	//\r
298	// 28 reserved\r
299	//\r
300	#define EXCEPT_IPF_DEBUG 29\r
301	#define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r
302	#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r
303	#define EXCEPT_IPF_FP_FAULT 32\r
304	#define EXCEPT_IPF_FP_TRAP 33\r
305	#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r
306	#define EXCEPT_IPF_TAKEN_BRANCH 35\r
307	#define EXCEPT_IPF_SINGLE_STEP 36\r
308	//\r
309	// 37 - 44 reserved\r
310	//\r
311	#define EXCEPT_IPF_IA32_EXCEPTION 45\r
312	#define EXCEPT_IPF_IA32_INTERCEPT 46\r
313	#define EXCEPT_IPF_IA32_INTERRUPT 47\r
314	\r
315	//\r
316	// IPF processor context definition\r
317	//\r
318	typedef struct {\r
319	//\r
320	// The first reserved field is necessary to preserve alignment for the correct\r
321	// bits in UNAT and to insure F2 is 16 byte aligned..\r
322	//\r
323	UINT64 Reserved;\r
324	UINT64 R1;\r
325	UINT64 R2;\r
326	UINT64 R3;\r
327	UINT64 R4;\r
328	UINT64 R5;\r
329	UINT64 R6;\r
330	UINT64 R7;\r
331	UINT64 R8;\r
332	UINT64 R9;\r
333	UINT64 R10;\r
334	UINT64 R11;\r
335	UINT64 R12;\r
336	UINT64 R13;\r
337	UINT64 R14;\r
338	UINT64 R15;\r
339	UINT64 R16;\r
340	UINT64 R17;\r
341	UINT64 R18;\r
342	UINT64 R19;\r
343	UINT64 R20;\r
344	UINT64 R21;\r
345	UINT64 R22;\r
346	UINT64 R23;\r
347	UINT64 R24;\r
348	UINT64 R25;\r
349	UINT64 R26;\r
350	UINT64 R27;\r
351	UINT64 R28;\r
352	UINT64 R29;\r
353	UINT64 R30;\r
354	UINT64 R31;\r
355	\r
356	UINT64 F2[2];\r
357	UINT64 F3[2];\r
358	UINT64 F4[2];\r
359	UINT64 F5[2];\r
360	UINT64 F6[2];\r
361	UINT64 F7[2];\r
362	UINT64 F8[2];\r
363	UINT64 F9[2];\r
364	UINT64 F10[2];\r
365	UINT64 F11[2];\r
366	UINT64 F12[2];\r
367	UINT64 F13[2];\r
368	UINT64 F14[2];\r
369	UINT64 F15[2];\r
370	UINT64 F16[2];\r
371	UINT64 F17[2];\r
372	UINT64 F18[2];\r
373	UINT64 F19[2];\r
374	UINT64 F20[2];\r
375	UINT64 F21[2];\r
376	UINT64 F22[2];\r
377	UINT64 F23[2];\r
378	UINT64 F24[2];\r
379	UINT64 F25[2];\r
380	UINT64 F26[2];\r
381	UINT64 F27[2];\r
382	UINT64 F28[2];\r
383	UINT64 F29[2];\r
384	UINT64 F30[2];\r
385	UINT64 F31[2];\r
386	\r
387	UINT64 Pr;\r
388	\r
389	UINT64 B0;\r
390	UINT64 B1;\r
391	UINT64 B2;\r
392	UINT64 B3;\r
393	UINT64 B4;\r
394	UINT64 B5;\r
395	UINT64 B6;\r
396	UINT64 B7;\r
397	\r
398	//\r
399	// application registers\r
400	//\r
401	UINT64 ArRsc;\r
402	UINT64 ArBsp;\r
403	UINT64 ArBspstore;\r
404	UINT64 ArRnat;\r
405	\r
406	UINT64 ArFcr;\r
407	\r
408	UINT64 ArEflag;\r
409	UINT64 ArCsd;\r
410	UINT64 ArSsd;\r
411	UINT64 ArCflg;\r
412	UINT64 ArFsr;\r
413	UINT64 ArFir;\r
414	UINT64 ArFdr;\r
415	\r
416	UINT64 ArCcv;\r
417	\r
418	UINT64 ArUnat;\r
419	\r
420	UINT64 ArFpsr;\r
421	\r
422	UINT64 ArPfs;\r
423	UINT64 ArLc;\r
424	UINT64 ArEc;\r
425	\r
426	//\r
427	// control registers\r
428	//\r
429	UINT64 CrDcr;\r
430	UINT64 CrItm;\r
431	UINT64 CrIva;\r
432	UINT64 CrPta;\r
433	UINT64 CrIpsr;\r
434	UINT64 CrIsr;\r
435	UINT64 CrIip;\r
436	UINT64 CrIfa;\r
437	UINT64 CrItir;\r
438	UINT64 CrIipa;\r
439	UINT64 CrIfs;\r
440	UINT64 CrIim;\r
441	UINT64 CrIha;\r
442	\r
443	//\r
444	// debug registers\r
445	//\r
446	UINT64 Dbr0;\r
447	UINT64 Dbr1;\r
448	UINT64 Dbr2;\r
449	UINT64 Dbr3;\r
450	UINT64 Dbr4;\r
451	UINT64 Dbr5;\r
452	UINT64 Dbr6;\r
453	UINT64 Dbr7;\r
454	\r
455	UINT64 Ibr0;\r
456	UINT64 Ibr1;\r
457	UINT64 Ibr2;\r
458	UINT64 Ibr3;\r
459	UINT64 Ibr4;\r
460	UINT64 Ibr5;\r
461	UINT64 Ibr6;\r
462	UINT64 Ibr7;\r
463	\r
464	//\r
465	// virtual registers - nat bits for R1-R31\r
466	//\r
467	UINT64 IntNat;\r
468	\r
469	} EFI_SYSTEM_CONTEXT_IPF;\r
470	\r
471	//\r
472	// EBC processor exception types\r
473	//\r
474	#define EXCEPT_EBC_UNDEFINED 0\r
475	#define EXCEPT_EBC_DIVIDE_ERROR 1\r
476	#define EXCEPT_EBC_DEBUG 2\r
477	#define EXCEPT_EBC_BREAKPOINT 3\r
478	#define EXCEPT_EBC_OVERFLOW 4\r
479	#define EXCEPT_EBC_INVALID_OPCODE 5 // opcode out of range\r
480	#define EXCEPT_EBC_STACK_FAULT 6\r
481	#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
482	#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 // malformed instruction\r
483	#define EXCEPT_EBC_BAD_BREAK 9 // BREAK 0 or undefined BREAK\r
484	#define EXCEPT_EBC_STEP 10 // to support debug stepping\r
485	//\r
486	// For coding convenience, define the maximum valid EBC exception.\r
487	//\r
488	#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
489	\r
490	//\r
491	// EBC processor context definition\r
492	//\r
493	typedef struct {\r
494	UINT64 R0;\r
495	UINT64 R1;\r
496	UINT64 R2;\r
497	UINT64 R3;\r
498	UINT64 R4;\r
499	UINT64 R5;\r
500	UINT64 R6;\r
501	UINT64 R7;\r
502	UINT64 Flags;\r
503	UINT64 ControlFlags;\r
504	UINT64 Ip;\r
505	} EFI_SYSTEM_CONTEXT_EBC;\r
506	\r
507	//\r
508	// Universal EFI_SYSTEM_CONTEXT definition\r
509	//\r
510	typedef union {\r
511	EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
512	EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
513	EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
514	EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
515	} EFI_SYSTEM_CONTEXT;\r
516	\r
517	//\r
518	// DebugSupport callback function prototypes\r
519	//\r
520	typedef\r
521	VOID\r
522	(*EFI_EXCEPTION_CALLBACK) (\r
523	IN EFI_EXCEPTION_TYPE ExceptionType,\r
524	IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
525	);\r
526	\r
527	typedef\r
528	VOID\r
529	(*EFI_PERIODIC_CALLBACK) (\r
530	IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
531	);\r
532	\r
533	//\r
534	// Machine type definition\r
535	//\r
536	typedef enum {\r
537	IsaIa32 = EFI_IMAGE_MACHINE_IA32,\r
538	IsaX64 = EFI_IMAGE_MACHINE_X64,\r
539	IsaIpf = EFI_IMAGE_MACHINE_IA64,\r
540	IsaEbc = EFI_IMAGE_MACHINE_EBC\r
541	} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
542	\r
543	EFI_FORWARD_DECLARATION (EFI_DEBUG_SUPPORT_PROTOCOL);\r
544	\r
545	//\r
546	// DebugSupport member function definitions\r
547	//\r
548	typedef\r
549	EFI_STATUS\r
550	(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX) (\r
551	IN EFI_DEBUG_SUPPORT_PROTOCOL * This,\r
552	OUT UINTN *MaxProcessorIndex\r
553	);\r
554	\r
555	typedef\r
556	EFI_STATUS\r
557	(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK) (\r
558	IN EFI_DEBUG_SUPPORT_PROTOCOL * This,\r
559	IN UINTN ProcessorIndex,\r
560	IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
561	);\r
562	\r
563	typedef\r
564	EFI_STATUS\r
565	(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK) (\r
566	IN EFI_DEBUG_SUPPORT_PROTOCOL * This,\r
567	IN UINTN ProcessorIndex,\r
568	IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
569	IN EFI_EXCEPTION_TYPE ExceptionType\r
570	);\r
571	\r
572	typedef\r
573	EFI_STATUS\r
574	(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE) (\r
575	IN EFI_DEBUG_SUPPORT_PROTOCOL * This,\r
576	IN UINTN ProcessorIndex,\r
577	IN VOID *Start,\r
578	IN UINT64 Length\r
579	);\r
580	\r
581	//\r
582	// DebugSupport protocol definition\r
583	//\r
e5bce275	584	struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
3eb9473e	585	EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
	586	EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
	587	EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
	588	EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
	589	EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
e5bce275	590	};\r
3eb9473e	591	\r
	592	extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
	593	\r
	594	#endif /* _DEBUG_SUPPORT_H_ */\r