projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3eb9473e | 1 | // ++\r |
| 2 | \r | |
| 3 | // TODO: fix comment to start with /*++\r | |
| 4 | //\r | |
| f57387d5 HT |
5 | // Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>\r |
| 6 | // This program and the accompanying materials\r | |
| 3eb9473e | 7 | // are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | // which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | // http://opensource.org/licenses/bsd-license.php\r | |
| 10 | //\r | |
| 11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | //\r | |
| 14 | // Module Name:\r | |
| 15 | //\r | |
| 16 | // IpfDefines.h\r | |
| 17 | //\r | |
| 18 | // Abstract:\r | |
| 19 | //\r | |
| 20 | // IPF Processor Defines.\r | |
| 21 | // NOTE: This file is included by assembly files as well.\r | |
| 22 | //\r | |
| 23 | // --\r | |
| 24 | //\r | |
| 25 | #ifndef _IPFDEFINES_H\r | |
| 26 | #define _IPFDEFINES_H\r | |
| 27 | \r | |
| 28 | //\r | |
| 29 | // IPI DElivery Methods\r | |
| 30 | //\r | |
| 31 | #define IPI_INT_DELIVERY 0x0\r | |
| 32 | #define IPI_PMI_DELIVERY 0x2\r | |
| 33 | #define IPI_NMI_DELIVERY 0x4\r | |
| 34 | #define IPI_INIT_DELIVERY 0x5\r | |
| 35 | #define IPI_ExtINT_DELIVERY 0x7\r | |
| 36 | \r | |
| 37 | //\r | |
| 38 | // Define Itanium-based system registers.\r | |
| 39 | //\r | |
| 40 | // Define Itanium-based system register bit field offsets.\r | |
| 41 | //\r | |
| 42 | // Processor Status Register (PSR) Bit positions\r | |
| 43 | //\r | |
| 44 | // User / System mask\r | |
| 45 | //\r | |
| 46 | #define PSR_RV0 0\r | |
| 47 | #define PSR_BE 1\r | |
| 48 | #define PSR_UP 2\r | |
| 49 | #define PSR_AC 3\r | |
| 50 | #define PSR_MFL 4\r | |
| 51 | #define PSR_MFH 5\r | |
| 52 | \r | |
| 53 | //\r | |
| 54 | // PSR bits 6-12 reserved (must be zero)\r | |
| 55 | //\r | |
| 56 | #define PSR_MBZ0 6\r | |
| 57 | #define PSR_MBZ0_V 0x1ffUL L\r | |
| 58 | \r | |
| 59 | //\r | |
| 60 | // System only mask\r | |
| 61 | //\r | |
| 62 | #define PSR_IC 13\r | |
| 63 | #define PSR_IC_MASK (1 << 13)\r | |
| 64 | #define PSR_I 14\r | |
| 65 | #define PSR_PK 15\r | |
| 66 | #define PSR_MBZ1 16\r | |
| 67 | #define PSR_MBZ1_V 0x1UL L\r | |
| 68 | #define PSR_DT 17\r | |
| 69 | #define PSR_DFL 18\r | |
| 70 | #define PSR_DFH 19\r | |
| 71 | #define PSR_SP 20\r | |
| 72 | #define PSR_PP 21\r | |
| 73 | #define PSR_DI 22\r | |
| 74 | #define PSR_SI 23\r | |
| 75 | #define PSR_DB 24\r | |
| 76 | #define PSR_LP 25\r | |
| 77 | #define PSR_TB 26\r | |
| 78 | #define PSR_RT 27\r | |
| 79 | \r | |
| 80 | //\r | |
| 81 | // PSR bits 28-31 reserved (must be zero)\r | |
| 82 | //\r | |
| 83 | #define PSR_MBZ2 28\r | |
| 84 | #define PSR_MBZ2_V 0xfUL L\r | |
| 85 | \r | |
| 86 | //\r | |
| 87 | // Neither mask\r | |
| 88 | //\r | |
| 89 | #define PSR_CPL 32\r | |
| 90 | #define PSR_CPL_LEN 2\r | |
| 91 | #define PSR_IS 34\r | |
| 92 | #define PSR_MC 35\r | |
| 93 | #define PSR_IT 36\r | |
| 94 | #define PSR_IT_MASK 0x1000000000\r | |
| 95 | #define PSR_ID 37\r | |
| 96 | #define PSR_DA 38\r | |
| 97 | #define PSR_DD 39\r | |
| 98 | #define PSR_SS 40\r | |
| 99 | #define PSR_RI 41\r | |
| 100 | #define PSR_RI_LEN 2\r | |
| 101 | #define PSR_ED 43\r | |
| 102 | #define PSR_BN 44\r | |
| 103 | \r | |
| 104 | //\r | |
| 105 | // PSR bits 45-63 reserved (must be zero)\r | |
| 106 | //\r | |
| 107 | #define PSR_MBZ3 45\r | |
| 108 | #define PSR_MBZ3_V 0xfffffUL L\r | |
| 109 | \r | |
| 110 | //\r | |
| 111 | // Floating Point Status Register (FPSR) Bit positions\r | |
| 112 | //\r | |
| 113 | //\r | |
| 114 | // Traps\r | |
| 115 | //\r | |
| 116 | #define FPSR_VD 0\r | |
| 117 | #define FPSR_DD 1\r | |
| 118 | #define FPSR_ZD 2\r | |
| 119 | #define FPSR_OD 3\r | |
| 120 | #define FPSR_UD 4\r | |
| 121 | #define FPSR_ID 5\r | |
| 122 | \r | |
| 123 | //\r | |
| 124 | // Status Field 0 - Controls\r | |
| 125 | //\r | |
| 126 | #define FPSR0_FTZ0 6\r | |
| 127 | #define FPSR0_WRE0 7\r | |
| 128 | #define FPSR0_PC0 8\r | |
| 129 | #define FPSR0_RC0 10\r | |
| 130 | #define FPSR0_TD0 12\r | |
| 131 | \r | |
| 132 | //\r | |
| 133 | // Status Field 0 - Flags\r | |
| 134 | //\r | |
| 135 | #define FPSR0_V0 13\r | |
| 136 | #define FPSR0_D0 14\r | |
| 137 | #define FPSR0_Z0 15\r | |
| 138 | #define FPSR0_O0 16\r | |
| 139 | #define FPSR0_U0 17\r | |
| 140 | #define FPSR0_I0 18\r | |
| 141 | \r | |
| 142 | //\r | |
| 143 | // Status Field 1 - Controls\r | |
| 144 | //\r | |
| 145 | #define FPSR1_FTZ0 19\r | |
| 146 | #define FPSR1_WRE0 20\r | |
| 147 | #define FPSR1_PC0 21\r | |
| 148 | #define FPSR1_RC0 23\r | |
| 149 | #define FPSR1_TD0 25\r | |
| 150 | \r | |
| 151 | //\r | |
| 152 | // Status Field 1 - Flags\r | |
| 153 | //\r | |
| 154 | #define FPSR1_V0 26\r | |
| 155 | #define FPSR1_D0 27\r | |
| 156 | #define FPSR1_Z0 28\r | |
| 157 | #define FPSR1_O0 29\r | |
| 158 | #define FPSR1_U0 30\r | |
| 159 | #define FPSR1_I0 31\r | |
| 160 | \r | |
| 161 | //\r | |
| 162 | // Status Field 2 - Controls\r | |
| 163 | //\r | |
| 164 | #define FPSR2_FTZ0 32\r | |
| 165 | #define FPSR2_WRE0 33\r | |
| 166 | #define FPSR2_PC0 34\r | |
| 167 | #define FPSR2_RC0 36\r | |
| 168 | #define FPSR2_TD0 38\r | |
| 169 | \r | |
| 170 | //\r | |
| 171 | // Status Field 2 - Flags\r | |
| 172 | //\r | |
| 173 | #define FPSR2_V0 39\r | |
| 174 | #define FPSR2_D0 40\r | |
| 175 | #define FPSR2_Z0 41\r | |
| 176 | #define FPSR2_O0 42\r | |
| 177 | #define FPSR2_U0 43\r | |
| 178 | #define FPSR2_I0 44\r | |
| 179 | \r | |
| 180 | //\r | |
| 181 | // Status Field 3 - Controls\r | |
| 182 | //\r | |
| 183 | #define FPSR3_FTZ0 45\r | |
| 184 | #define FPSR3_WRE0 46\r | |
| 185 | #define FPSR3_PC0 47\r | |
| 186 | #define FPSR3_RC0 49\r | |
| 187 | #define FPSR3_TD0 51\r | |
| 188 | \r | |
| 189 | //\r | |
| 190 | // Status Field 0 - Flags\r | |
| 191 | //\r | |
| 192 | #define FPSR3_V0 52\r | |
| 193 | #define FPSR3_D0 53\r | |
| 194 | #define FPSR3_Z0 54\r | |
| 195 | #define FPSR3_O0 55\r | |
| 196 | #define FPSR3_U0 56\r | |
| 197 | #define FPSR3_I0 57\r | |
| 198 | \r | |
| 199 | //\r | |
| 200 | // FPSR bits 58-63 Reserved -- Must be zero\r | |
| 201 | //\r | |
| 202 | #define FPSR_MBZ0 58\r | |
| 203 | #define FPSR_MBZ0_V 0x3fUL L\r | |
| 204 | \r | |
| 205 | //\r | |
| 206 | // For setting up FPSR on kernel entry\r | |
| 207 | // All traps are disabled.\r | |
| 208 | //\r | |
| 209 | #define FPSR_FOR_KERNEL 0x3f\r | |
| 210 | \r | |
| 211 | #define FP_REG_SIZE 16 // 16 byte spill size\r | |
| 212 | #define HIGHFP_REGS_LENGTH (96 * 16)\r | |
| 213 | \r | |
| 214 | //\r | |
| 215 | // Define hardware Task Priority Register (TPR)\r | |
| 216 | //\r | |
| 217 | //\r | |
| 218 | // TPR bit positions\r | |
| 219 | //\r | |
| 220 | #define TPR_MIC 4 // Bits 0 - 3 ignored\r | |
| 221 | #define TPR_MIC_LEN 4\r | |
| 222 | #define TPR_MMI 16 // Mask Maskable Interrupt\r | |
| 223 | //\r | |
| 224 | // Define hardware Interrupt Status Register (ISR)\r | |
| 225 | //\r | |
| 226 | //\r | |
| 227 | // ISR bit positions\r | |
| 228 | //\r | |
| 229 | #define ISR_CODE 0\r | |
| 230 | #define ISR_CODE_LEN 16\r | |
| 231 | #define ISR_CODE_MASK 0xFFFF\r | |
| 232 | #define ISR_IA_VECTOR 16\r | |
| 233 | #define ISR_IA_VECTOR_LEN 8\r | |
| 234 | #define ISR_MBZ0 24\r | |
| 235 | #define ISR_MBZ0_V 0xff\r | |
| 236 | #define ISR_X 32\r | |
| 237 | #define ISR_W 33\r | |
| 238 | #define ISR_R 34\r | |
| 239 | #define ISR_NA 35\r | |
| 240 | #define ISR_SP 36\r | |
| 241 | #define ISR_RS 37\r | |
| 242 | #define ISR_IR 38\r | |
| 243 | #define ISR_NI 39\r | |
| 244 | #define ISR_MBZ1 40\r | |
| 245 | #define ISR_EI 41\r | |
| 246 | #define ISR_ED 43\r | |
| 247 | #define ISR_MBZ2 44\r | |
| 248 | #define ISR_MBZ2_V 0xfffff\r | |
| 249 | \r | |
| 250 | //\r | |
| 251 | // ISR codes\r | |
| 252 | //\r | |
| 253 | // For General exceptions: ISR{3:0}\r | |
| 254 | //\r | |
| 255 | #define ISR_ILLEGAL_OP 0 // Illegal operation fault\r | |
| 256 | #define ISR_PRIV_OP 1 // Privileged operation fault\r | |
| 257 | #define ISR_PRIV_REG 2 // Privileged register fauls\r | |
| 258 | #define ISR_RESVD_REG 3 // Reserved register/field flt\r | |
| 259 | #define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault\r | |
| 260 | //\r | |
| 261 | // Define hardware Default Control Register (DCR)\r | |
| 262 | //\r | |
| 263 | //\r | |
| 264 | // DCR bit positions\r | |
| 265 | //\r | |
| 266 | #define DCR_PP 0\r | |
| 267 | #define DCR_BE 1\r | |
| 268 | #define DCR_LC 2\r | |
| 269 | #define DCR_MBZ0 4\r | |
| 270 | #define DCR_MBZ0_V 0xf\r | |
| 271 | #define DCR_DM 8\r | |
| 272 | #define DCR_DP 9\r | |
| 273 | #define DCR_DK 10\r | |
| 274 | #define DCR_DX 11\r | |
| 275 | #define DCR_DR 12\r | |
| 276 | #define DCR_DA 13\r | |
| 277 | #define DCR_DD 14\r | |
| 278 | #define DCR_DEFER_ALL 0x7f00\r | |
| 279 | #define DCR_MBZ1 2\r | |
| 280 | #define DCR_MBZ1_V 0xffffffffffffUL L\r | |
| 281 | \r | |
| 282 | //\r | |
| 283 | // Define hardware RSE Configuration Register\r | |
| 284 | //\r | |
| 285 | // RS Configuration (RSC) bit field positions\r | |
| 286 | //\r | |
| 287 | #define RSC_MODE 0\r | |
| 288 | #define RSC_PL 2\r | |
| 289 | #define RSC_BE 4\r | |
| 290 | #define RSC_MBZ0 5\r | |
| 291 | #define RSC_MBZ0_V 0x3ff\r | |
| 292 | #define RSC_LOADRS 16\r | |
| 293 | #define RSC_LOADRS_LEN 14\r | |
| 294 | #define RSC_MBZ1 30\r | |
| 295 | #define RSC_MBZ1_V 0x3ffffffffUL L\r | |
| 296 | \r | |
| 297 | //\r | |
| 298 | // RSC modes\r | |
| 299 | //\r | |
| 300 | #define RSC_MODE_LY (0x0) // Lazy\r | |
| 301 | #define RSC_MODE_SI (0x1) // Store intensive\r | |
| 302 | #define RSC_MODE_LI (0x2) // Load intensive\r | |
| 303 | #define RSC_MODE_EA (0x3) // Eager\r | |
| 304 | //\r | |
| 305 | // RSC Endian bit values\r | |
| 306 | //\r | |
| 307 | #define RSC_BE_LITTLE 0\r | |
| 308 | #define RSC_BE_BIG 1\r | |
| 309 | \r | |
| 310 | //\r | |
| 311 | // Define Interruption Function State (IFS) Register\r | |
| 312 | //\r | |
| 313 | // IFS bit field positions\r | |
| 314 | //\r | |
| 315 | #define IFS_IFM 0\r | |
| 316 | #define IFS_IFM_LEN 38\r | |
| 317 | #define IFS_MBZ0 38\r | |
| 318 | #define IFS_MBZ0_V 0x1ffffff\r | |
| 319 | #define IFS_V 63\r | |
| 320 | #define IFS_V_LEN 1\r | |
| 321 | \r | |
| 322 | //\r | |
| 323 | // IFS is valid when IFS_V = IFS_VALID\r | |
| 324 | //\r | |
| 325 | #define IFS_VALID 1\r | |
| 326 | \r | |
| 327 | //\r | |
| 328 | // Define Page Table Address (PTA)\r | |
| 329 | //\r | |
| 330 | #define PTA_VE 0\r | |
| 331 | #define PTA_VF 8\r | |
| 332 | #define PTA_SIZE 2\r | |
| 333 | #define PTA_SIZE_LEN 6\r | |
| 334 | #define PTA_BASE 15\r | |
| 335 | \r | |
| 336 | //\r | |
| 337 | // Define Region Register (RR)\r | |
| 338 | //\r | |
| 339 | //\r | |
| 340 | // RR bit field positions\r | |
| 341 | //\r | |
| 342 | #define RR_VE 0\r | |
| 343 | #define RR_MBZ0 1\r | |
| 344 | #define RR_PS 2\r | |
| 345 | #define RR_PS_LEN 6\r | |
| 346 | #define RR_RID 8\r | |
| 347 | #define RR_RID_LEN 24\r | |
| 348 | #define RR_MBZ1 32\r | |
| 349 | \r | |
| 350 | //\r | |
| 351 | // SAL uses region register 0 and RID of 1000\r | |
| 352 | //\r | |
| 353 | #define SAL_RID 0x1000\r | |
| 354 | #define SAL_RR_REG 0x0\r | |
| 355 | #define SAL_TR 0x0\r | |
| 356 | \r | |
| 357 | //\r | |
| 358 | // Total number of region registers\r | |
| 359 | //\r | |
| 360 | #define RR_SIZE 8\r | |
| 361 | \r | |
| 362 | //\r | |
| 363 | // Define Protection Key Register (PKR)\r | |
| 364 | //\r | |
| 365 | // PKR bit field positions\r | |
| 366 | //\r | |
| 367 | #define PKR_V 0\r | |
| 368 | #define PKR_WD 1\r | |
| 369 | #define PKR_RD 2\r | |
| 370 | #define PKR_XD 3\r | |
| 371 | #define PKR_MBZ0 4\r | |
| 372 | #define PKR_KEY 8\r | |
| 373 | #define PKR_KEY_LEN 24\r | |
| 374 | #define PKR_MBZ1 32\r | |
| 375 | \r | |
| 376 | #define PKR_VALID (1 << PKR_V)\r | |
| 377 | \r | |
| 378 | //\r | |
| 379 | // Number of protection key registers\r | |
| 380 | //\r | |
| 381 | #define PKRNUM 8\r | |
| 382 | \r | |
| 383 | //\r | |
| 384 | // Define Interruption TLB Insertion register (ITIR)\r | |
| 385 | //\r | |
| 386 | //\r | |
| 387 | // Define Translation Insertion Format (TR)\r | |
| 388 | //\r | |
| 389 | // PTE0 bit field positions\r | |
| 390 | //\r | |
| 391 | #define PTE0_P 0\r | |
| 392 | #define PTE0_MBZ0 1\r | |
| 393 | #define PTE0_MA 2\r | |
| 394 | #define PTE0_A 5\r | |
| 395 | #define PTE0_D 6\r | |
| 396 | #define PTE0_PL 7\r | |
| 397 | #define PTE0_AR 9\r | |
| 398 | #define PTE0_PPN 12\r | |
| 399 | #define PTE0_MBZ1 48\r | |
| 400 | #define PTE0_ED 52\r | |
| 401 | #define PTE0_IGN0 53\r | |
| 402 | \r | |
| 403 | //\r | |
| 404 | // ITIR bit field positions\r | |
| 405 | //\r | |
| 406 | #define ITIR_MBZ0 0\r | |
| 407 | #define ITIR_PS 2\r | |
| 408 | #define ITIR_PS_LEN 6\r | |
| 409 | #define ITIR_KEY 8\r | |
| 410 | #define ITIR_KEY_LEN 24\r | |
| 411 | #define ITIR_MBZ1 32\r | |
| 412 | #define ITIR_MBZ1_LEN 16\r | |
| 413 | #define ITIR_PPN 48\r | |
| 414 | #define ITIR_PPN_LEN 15\r | |
| 415 | #define ITIR_MBZ2 63\r | |
| 416 | \r | |
| 417 | #define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)\r | |
| 418 | #define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)\r | |
| 419 | // Dirty (bit 6=1), Accessed (bit 5=1),\r | |
| 420 | // MA WB (bits 4-2=000), Present (bit 0=1)\r | |
| 421 | //\r | |
| 422 | // Memory access rights\r | |
| 423 | //\r | |
| 424 | #define AR_UR_KR 0x0 // user/kernel read\r | |
| 425 | #define AR_URX_KRX 0x1 // user/kernel read and execute\r | |
| 426 | #define AR_URW_KRW 0x2 // user/kernel read & write\r | |
| 427 | #define AR_URWX_KRWX 0x3 // user/kernel read,write&execute\r | |
| 428 | #define AR_UR_KRW 0x4 // user read/kernel read,write\r | |
| 429 | #define AR_URX_KRWX 0x5 // user read/execute, kernel all\r | |
| 430 | #define AR_URWX_KRW 0x6 // user all, kernel read & write\r | |
| 431 | #define AR_UX_KRX 0x7 // user execute only, kernel read and execute\r | |
| 432 | //\r | |
| 433 | // Memory attribute values\r | |
| 434 | //\r | |
| 435 | //\r | |
| 436 | // The next 4 are all cached, non-sequential & speculative, coherent\r | |
| 437 | //\r | |
| 438 | #define MA_WBU 0x0 // Write back, unordered\r | |
| 439 | //\r | |
| 440 | // The next 3 are all non-cached, sequential & non-speculative\r | |
| 441 | //\r | |
| 442 | #define MA_UC 0x4 // Non-coalescing, sequential & non-speculative\r | |
| 443 | #define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative\r | |
| 444 | // & fetchadd exported\r | |
| 445 | //\r | |
| 446 | #define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.\r | |
| 447 | #define MA_NAT 0xf // NaT page\r | |
| 448 | //\r | |
| 449 | // Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the\r | |
| 450 | // base of IVA (Interruption Vector Address)\r | |
| 451 | //\r | |
| 452 | #define IVT_SIZE 0x8000\r | |
| 453 | #define EXTRA_ALIGNMENT 0x1000\r | |
| 454 | \r | |
| 455 | #define OFF_VHPTFLT 0x0000 // VHPT Translation fault\r | |
| 456 | #define OFF_ITLBFLT 0x0400 // Instruction TLB fault\r | |
| 457 | #define OFF_DTLBFLT 0x0800 // Data TLB fault\r | |
| 458 | #define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault\r | |
| 459 | #define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault\r | |
| 460 | #define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault\r | |
| 461 | #define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault\r | |
| 462 | #define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault\r | |
| 463 | #define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault\r | |
| 464 | #define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault\r | |
| 465 | #define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault\r | |
| 466 | #define OFF_BREAKFLT 0x2C00 // Break Inst fault\r | |
| 467 | #define OFF_EXTINT 0x3000 // External Interrupt\r | |
| 468 | //\r | |
| 469 | // Offset 0x3400 to 0x0x4C00 are reserved\r | |
| 470 | //\r | |
| 471 | #define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault\r | |
| 472 | #define OFF_KEYPERMFLT 0x5100 // Key Permission fault\r | |
| 473 | #define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt\r | |
| 474 | #define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault\r | |
| 475 | #define OFF_GPFLT 0x5400 // General Exception fault\r | |
| 476 | #define OFF_FPDISFLT 0x5500 // Disable-FP fault\r | |
| 477 | #define OFF_NATFLT 0x5600 // NAT Consumption fault\r | |
| 478 | #define OFF_SPECLNFLT 0x5700 // Speculation fault\r | |
| 479 | #define OFF_DBGFLT 0x5900 // Debug fault\r | |
| 480 | #define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault\r | |
| 481 | #define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault\r | |
| 482 | #define OFF_FPFLT 0x5C00 // Floating Point fault\r | |
| 483 | #define OFF_FPTRAP 0x5D00 // Floating Point Trap\r | |
| 484 | #define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap\r | |
| 485 | #define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap\r | |
| 486 | #define OFF_SSTEPTRAP 0x6000 // Single Step Trap\r | |
| 487 | //\r | |
| 488 | // Offset 0x6100 to 0x6800 are reserved\r | |
| 489 | //\r | |
| 490 | #define OFF_IA32EXCEPTN 0x6900 // iA32 Exception\r | |
| 491 | #define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept\r | |
| 492 | #define OFF_IA32INT 0x6B00 // iA32 Interrupt\r | |
| 493 | #define NUMBER_OF_VECTORS 0x100\r | |
| 494 | //\r | |
| 495 | // Privilege levels\r | |
| 496 | //\r | |
| 497 | #define PL_KERNEL 0\r | |
| 498 | #define PL_USER 3\r | |
| 499 | \r | |
| 500 | //\r | |
| 501 | // Instruction set (IS) bits\r | |
| 502 | //\r | |
| 503 | #define IS_IA64 0\r | |
| 504 | #define IS_IA 1\r | |
| 505 | \r | |
| 506 | //\r | |
| 507 | // RSC while in kernel: enabled, little endian, PL = 0, eager mode\r | |
| 508 | //\r | |
| 509 | #define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r | |
| 510 | \r | |
| 511 | //\r | |
| 512 | // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode\r | |
| 513 | //\r | |
| 514 | #define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r | |
| 515 | \r | |
| 516 | //\r | |
| 517 | // RSE disabled: disabled, PL = 0, little endian, eager mode\r | |
| 518 | //\r | |
| 519 | #define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))\r | |
| 520 | \r | |
| 521 | #define NAT_BITS_PER_RNAT_REG 63\r | |
| 522 | \r | |
| 523 | //\r | |
| 524 | // Macros for generating PTE0 and PTE1 value\r | |
| 525 | //\r | |
| 526 | #define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \\r | |
| 527 | ( ( ed << PTE0_ED ) | \\r | |
| 528 | ( ppn12_47 << PTE0_PPN ) | \\r | |
| 529 | ( ar << PTE0_AR ) | \\r | |
| 530 | ( pl << PTE0_PL ) | \\r | |
| 531 | ( d << PTE0_D ) | \\r | |
| 532 | ( a << PTE0_A ) | \\r | |
| 533 | ( ma << PTE0_MA ) | \\r | |
| 534 | ( p << PTE0_P ) \\r | |
| 535 | )\r | |
| 536 | \r | |
| 537 | #define ITIR(ppn48_63, key, ps) \\r | |
| 538 | ( ( ps << ITIR_PS ) | \\r | |
| 539 | ( key << ITIR_KEY ) | \\r | |
| 540 | ( ppn48_63 << ITIR_PPN ) \\r | |
| 541 | )\r | |
| 542 | \r | |
| 543 | //\r | |
| 544 | // Macro to generate mask value from bit position. The result is a\r | |
| 545 | // 64-bit.\r | |
| 546 | //\r | |
| 547 | #define BITMASK(bp, value) (value << bp)\r | |
| 548 | \r | |
| 549 | #define BUNDLE_SIZE 16\r | |
| 550 | #define SPURIOUS_INT 0xF\r | |
| 551 | \r | |
| 552 | #define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;\r | |
| 553 | \r | |
| 554 | #define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;\r | |
| 555 | \r | |
| 556 | #endif\r |