projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3eb9473e | 1 | /*++\r |
| 2 | \r | |
| 2c7e5c2f HT |
3 | Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r |
| 4 | This program and the accompanying materials \r | |
| 3eb9473e | 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r | |
| 7 | http://opensource.org/licenses/bsd-license.php \r | |
| 8 | \r | |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 11 | \r | |
| 12 | \r | |
| 13 | Module Name:\r | |
| 14 | \r | |
| 15 | EdkIIGluePciExpressLib.h\r | |
| 16 | \r | |
| 17 | Abstract: \r | |
| 18 | \r | |
| 19 | Public header file for Pci Express Lib\r | |
| 20 | \r | |
| 21 | --*/\r | |
| 22 | \r | |
| 23 | #ifndef __EDKII_GLUE_PCI_EXPRESS_LIB_H__\r | |
| 24 | #define __EDKII_GLUE_PCI_EXPRESS_LIB_H__\r | |
| 25 | \r | |
| 26 | \r | |
| 27 | /**\r | |
| 28 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
| 29 | address that can be passed to the PCI Library functions.\r | |
| 30 | \r | |
| 31 | Computes an address that is compatible with the PCI Library functions. The\r | |
| 32 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
| 33 | the generation of the address.\r | |
| 34 | \r | |
| 35 | @param Bus PCI Bus number. Range 0..255.\r | |
| 36 | @param Device PCI Device number. Range 0..31.\r | |
| 37 | @param Function PCI Function number. Range 0..7.\r | |
| 38 | @param Register PCI Register number. Range 0..4095.\r | |
| 39 | \r | |
| 40 | @return The encode PCI address.\r | |
| 41 | \r | |
| 42 | **/\r | |
| 43 | #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
| 44 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
| 45 | \r | |
| 46 | /**\r | |
| 47 | Reads an 8-bit PCI configuration register.\r | |
| 48 | \r | |
| 49 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
| 50 | This function must guarantee that all PCI read and write operations are\r | |
| 51 | serialized.\r | |
| 52 | \r | |
| 53 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 54 | \r | |
| 55 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 56 | Register.\r | |
| 57 | \r | |
| 58 | @return The read value from the PCI configuration register.\r | |
| 59 | \r | |
| 60 | **/\r | |
| 61 | UINT8\r | |
| 62 | EFIAPI\r | |
| 63 | PciExpressRead8 (\r | |
| 64 | IN UINTN Address\r | |
| 65 | );\r | |
| 66 | \r | |
| 67 | /**\r | |
| 68 | Writes an 8-bit PCI configuration register.\r | |
| 69 | \r | |
| 70 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
| 71 | value specified by Value. Value is returned. This function must guarantee\r | |
| 72 | that all PCI read and write operations are serialized.\r | |
| 73 | \r | |
| 74 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 75 | \r | |
| 76 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 77 | Register.\r | |
| 78 | @param Value The value to write.\r | |
| 79 | \r | |
| 80 | @return The value written to the PCI configuration register.\r | |
| 81 | \r | |
| 82 | **/\r | |
| 83 | UINT8\r | |
| 84 | EFIAPI\r | |
| 85 | PciExpressWrite8 (\r | |
| 86 | IN UINTN Address,\r | |
| 87 | IN UINT8 Data\r | |
| 88 | );\r | |
| 89 | \r | |
| 90 | /**\r | |
| 91 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
| 92 | an 8-bit value.\r | |
| 93 | \r | |
| 94 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 95 | bitwise inclusive OR between the read result and the value specified by\r | |
| 96 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 97 | specified by Address. The value written to the PCI configuration register is\r | |
| 98 | returned. This function must guarantee that all PCI read and write operations\r | |
| 99 | are serialized.\r | |
| 100 | \r | |
| 101 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 102 | \r | |
| 103 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 104 | Register.\r | |
| 105 | @param OrData The value to OR with the PCI configuration register.\r | |
| 106 | \r | |
| 107 | @return The value written back to the PCI configuration register.\r | |
| 108 | \r | |
| 109 | **/\r | |
| 110 | UINT8\r | |
| 111 | EFIAPI\r | |
| 112 | PciExpressOr8 (\r | |
| 113 | IN UINTN Address,\r | |
| 114 | IN UINT8 OrData\r | |
| 115 | );\r | |
| 116 | \r | |
| 117 | /**\r | |
| 118 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 119 | value.\r | |
| 120 | \r | |
| 121 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 122 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 123 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 124 | Address. The value written to the PCI configuration register is returned.\r | |
| 125 | This function must guarantee that all PCI read and write operations are\r | |
| 126 | serialized.\r | |
| 127 | \r | |
| 128 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 129 | \r | |
| 130 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 131 | Register.\r | |
| 132 | @param AndData The value to AND with the PCI configuration register.\r | |
| 133 | \r | |
| 134 | @return The value written back to the PCI configuration register.\r | |
| 135 | \r | |
| 136 | **/\r | |
| 137 | UINT8\r | |
| 138 | EFIAPI\r | |
| 139 | PciExpressAnd8 (\r | |
| 140 | IN UINTN Address,\r | |
| 141 | IN UINT8 AndData\r | |
| 142 | );\r | |
| 143 | \r | |
| 144 | /**\r | |
| 145 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 146 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
| 147 | \r | |
| 148 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 149 | bitwise AND between the read result and the value specified by AndData,\r | |
| 150 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
| 151 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
| 152 | configuration register specified by Address. The value written to the PCI\r | |
| 153 | configuration register is returned. This function must guarantee that all PCI\r | |
| 154 | read and write operations are serialized.\r | |
| 155 | \r | |
| 156 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 157 | \r | |
| 158 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 159 | Register.\r | |
| 160 | @param AndData The value to AND with the PCI configuration register.\r | |
| 161 | @param OrData The value to OR with the result of the AND operation.\r | |
| 162 | \r | |
| 163 | @return The value written back to the PCI configuration register.\r | |
| 164 | \r | |
| 165 | **/\r | |
| 166 | UINT8\r | |
| 167 | EFIAPI\r | |
| 168 | PciExpressAndThenOr8 (\r | |
| 169 | IN UINTN Address,\r | |
| 170 | IN UINT8 AndData,\r | |
| 171 | IN UINT8 OrData\r | |
| 172 | );\r | |
| 173 | \r | |
| 174 | /**\r | |
| 175 | Reads a bit field of a PCI configuration register.\r | |
| 176 | \r | |
| 177 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
| 178 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 179 | returned.\r | |
| 180 | \r | |
| 181 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 182 | If StartBit is greater than 7, then ASSERT().\r | |
| 183 | If EndBit is greater than 7, then ASSERT().\r | |
| 184 | If EndBit is less than StartBit, then ASSERT().\r | |
| 185 | \r | |
| 186 | @param Address PCI configuration register to read.\r | |
| 187 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 188 | Range 0..7.\r | |
| 189 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 190 | Range 0..7.\r | |
| 191 | \r | |
| 192 | @return The value of the bit field read from the PCI configuration register.\r | |
| 193 | \r | |
| 194 | **/\r | |
| 195 | UINT8\r | |
| 196 | EFIAPI\r | |
| 197 | PciExpressBitFieldRead8 (\r | |
| 198 | IN UINTN Address,\r | |
| 199 | IN UINTN StartBit,\r | |
| 200 | IN UINTN EndBit\r | |
| 201 | );\r | |
| 202 | \r | |
| 203 | /**\r | |
| 204 | Writes a bit field to a PCI configuration register.\r | |
| 205 | \r | |
| 206 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 207 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 208 | destination PCI configuration register are preserved. The new value of the\r | |
| 209 | 8-bit register is returned.\r | |
| 210 | \r | |
| 211 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 212 | If StartBit is greater than 7, then ASSERT().\r | |
| 213 | If EndBit is greater than 7, then ASSERT().\r | |
| 214 | If EndBit is less than StartBit, then ASSERT().\r | |
| 215 | \r | |
| 216 | @param Address PCI configuration register to write.\r | |
| 217 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 218 | Range 0..7.\r | |
| 219 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 220 | Range 0..7.\r | |
| 221 | @param Value New value of the bit field.\r | |
| 222 | \r | |
| 223 | @return The value written back to the PCI configuration register.\r | |
| 224 | \r | |
| 225 | **/\r | |
| 226 | UINT8\r | |
| 227 | EFIAPI\r | |
| 228 | PciExpressBitFieldWrite8 (\r | |
| 229 | IN UINTN Address,\r | |
| 230 | IN UINTN StartBit,\r | |
| 231 | IN UINTN EndBit,\r | |
| 232 | IN UINT8 Value\r | |
| 233 | );\r | |
| 234 | \r | |
| 235 | /**\r | |
| 236 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
| 237 | writes the result back to the bit field in the 8-bit port.\r | |
| 238 | \r | |
| 239 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 240 | bitwise inclusive OR between the read result and the value specified by\r | |
| 241 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 242 | specified by Address. The value written to the PCI configuration register is\r | |
| 243 | returned. This function must guarantee that all PCI read and write operations\r | |
| 244 | are serialized. Extra left bits in OrData are stripped.\r | |
| 245 | \r | |
| 246 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 247 | If StartBit is greater than 7, then ASSERT().\r | |
| 248 | If EndBit is greater than 7, then ASSERT().\r | |
| 249 | If EndBit is less than StartBit, then ASSERT().\r | |
| 250 | \r | |
| 251 | @param Address PCI configuration register to write.\r | |
| 252 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 253 | Range 0..7.\r | |
| 254 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 255 | Range 0..7.\r | |
| 256 | @param OrData The value to OR with the PCI configuration register.\r | |
| 257 | \r | |
| 258 | @return The value written back to the PCI configuration register.\r | |
| 259 | \r | |
| 260 | **/\r | |
| 261 | UINT8\r | |
| 262 | EFIAPI\r | |
| 263 | PciExpressBitFieldOr8 (\r | |
| 264 | IN UINTN Address,\r | |
| 265 | IN UINTN StartBit,\r | |
| 266 | IN UINTN EndBit,\r | |
| 267 | IN UINT8 OrData\r | |
| 268 | );\r | |
| 269 | \r | |
| 270 | /**\r | |
| 271 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
| 272 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
| 273 | \r | |
| 274 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 275 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 276 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 277 | Address. The value written to the PCI configuration register is returned.\r | |
| 278 | This function must guarantee that all PCI read and write operations are\r | |
| 279 | serialized. Extra left bits in AndData are stripped.\r | |
| 280 | \r | |
| 281 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 282 | If StartBit is greater than 7, then ASSERT().\r | |
| 283 | If EndBit is greater than 7, then ASSERT().\r | |
| 284 | If EndBit is less than StartBit, then ASSERT().\r | |
| 285 | \r | |
| 286 | @param Address PCI configuration register to write.\r | |
| 287 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 288 | Range 0..7.\r | |
| 289 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 290 | Range 0..7.\r | |
| 291 | @param AndData The value to AND with the PCI configuration register.\r | |
| 292 | \r | |
| 293 | @return The value written back to the PCI configuration register.\r | |
| 294 | \r | |
| 295 | **/\r | |
| 296 | UINT8\r | |
| 297 | EFIAPI\r | |
| 298 | PciExpressBitFieldAnd8 (\r | |
| 299 | IN UINTN Address,\r | |
| 300 | IN UINTN StartBit,\r | |
| 301 | IN UINTN EndBit,\r | |
| 302 | IN UINT8 AndData\r | |
| 303 | );\r | |
| 304 | \r | |
| 305 | /**\r | |
| 306 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
| 307 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
| 308 | 8-bit port.\r | |
| 309 | \r | |
| 310 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 311 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
| 312 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
| 313 | configuration register specified by Address. The value written to the PCI\r | |
| 314 | configuration register is returned. This function must guarantee that all PCI\r | |
| 315 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 316 | OrData are stripped.\r | |
| 317 | \r | |
| 318 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 319 | If StartBit is greater than 7, then ASSERT().\r | |
| 320 | If EndBit is greater than 7, then ASSERT().\r | |
| 321 | If EndBit is less than StartBit, then ASSERT().\r | |
| 322 | \r | |
| 323 | @param Address PCI configuration register to write.\r | |
| 324 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 325 | Range 0..7.\r | |
| 326 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 327 | Range 0..7.\r | |
| 328 | @param AndData The value to AND with the PCI configuration register.\r | |
| 329 | @param OrData The value to OR with the result of the AND operation.\r | |
| 330 | \r | |
| 331 | @return The value written back to the PCI configuration register.\r | |
| 332 | \r | |
| 333 | **/\r | |
| 334 | UINT8\r | |
| 335 | EFIAPI\r | |
| 336 | PciExpressBitFieldAndThenOr8 (\r | |
| 337 | IN UINTN Address,\r | |
| 338 | IN UINTN StartBit,\r | |
| 339 | IN UINTN EndBit,\r | |
| 340 | IN UINT8 AndData,\r | |
| 341 | IN UINT8 OrData\r | |
| 342 | );\r | |
| 343 | \r | |
| 344 | /**\r | |
| 345 | Reads a 16-bit PCI configuration register.\r | |
| 346 | \r | |
| 347 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
| 348 | This function must guarantee that all PCI read and write operations are\r | |
| 349 | serialized.\r | |
| 350 | \r | |
| 351 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 352 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 353 | \r | |
| 354 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 355 | Register.\r | |
| 356 | \r | |
| 357 | @return The read value from the PCI configuration register.\r | |
| 358 | \r | |
| 359 | **/\r | |
| 360 | UINT16\r | |
| 361 | EFIAPI\r | |
| 362 | PciExpressRead16 (\r | |
| 363 | IN UINTN Address\r | |
| 364 | );\r | |
| 365 | \r | |
| 366 | /**\r | |
| 367 | Writes a 16-bit PCI configuration register.\r | |
| 368 | \r | |
| 369 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
| 370 | value specified by Value. Value is returned. This function must guarantee\r | |
| 371 | that all PCI read and write operations are serialized.\r | |
| 372 | \r | |
| 373 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 374 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 375 | \r | |
| 376 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 377 | Register.\r | |
| 378 | @param Value The value to write.\r | |
| 379 | \r | |
| 380 | @return The value written to the PCI configuration register.\r | |
| 381 | \r | |
| 382 | **/\r | |
| 383 | UINT16\r | |
| 384 | EFIAPI\r | |
| 385 | PciExpressWrite16 (\r | |
| 386 | IN UINTN Address,\r | |
| 387 | IN UINT16 Data\r | |
| 388 | );\r | |
| 389 | \r | |
| 390 | /**\r | |
| 391 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
| 392 | a 16-bit value.\r | |
| 393 | \r | |
| 394 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 395 | bitwise inclusive OR between the read result and the value specified by\r | |
| 396 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 397 | specified by Address. The value written to the PCI configuration register is\r | |
| 398 | returned. This function must guarantee that all PCI read and write operations\r | |
| 399 | are serialized.\r | |
| 400 | \r | |
| 401 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 402 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 403 | \r | |
| 404 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 405 | Register.\r | |
| 406 | @param OrData The value to OR with the PCI configuration register.\r | |
| 407 | \r | |
| 408 | @return The value written back to the PCI configuration register.\r | |
| 409 | \r | |
| 410 | **/\r | |
| 411 | UINT16\r | |
| 412 | EFIAPI\r | |
| 413 | PciExpressOr16 (\r | |
| 414 | IN UINTN Address,\r | |
| 415 | IN UINT16 OrData\r | |
| 416 | );\r | |
| 417 | \r | |
| 418 | /**\r | |
| 419 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 420 | value.\r | |
| 421 | \r | |
| 422 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 423 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 424 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 425 | Address. The value written to the PCI configuration register is returned.\r | |
| 426 | This function must guarantee that all PCI read and write operations are\r | |
| 427 | serialized.\r | |
| 428 | \r | |
| 429 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 430 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 431 | \r | |
| 432 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 433 | Register.\r | |
| 434 | @param AndData The value to AND with the PCI configuration register.\r | |
| 435 | \r | |
| 436 | @return The value written back to the PCI configuration register.\r | |
| 437 | \r | |
| 438 | **/\r | |
| 439 | UINT16\r | |
| 440 | EFIAPI\r | |
| 441 | PciExpressAnd16 (\r | |
| 442 | IN UINTN Address,\r | |
| 443 | IN UINT16 AndData\r | |
| 444 | );\r | |
| 445 | \r | |
| 446 | /**\r | |
| 447 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 448 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
| 449 | \r | |
| 450 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 451 | bitwise AND between the read result and the value specified by AndData,\r | |
| 452 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
| 453 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
| 454 | configuration register specified by Address. The value written to the PCI\r | |
| 455 | configuration register is returned. This function must guarantee that all PCI\r | |
| 456 | read and write operations are serialized.\r | |
| 457 | \r | |
| 458 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 459 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 460 | \r | |
| 461 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 462 | Register.\r | |
| 463 | @param AndData The value to AND with the PCI configuration register.\r | |
| 464 | @param OrData The value to OR with the result of the AND operation.\r | |
| 465 | \r | |
| 466 | @return The value written back to the PCI configuration register.\r | |
| 467 | \r | |
| 468 | **/\r | |
| 469 | UINT16\r | |
| 470 | EFIAPI\r | |
| 471 | PciExpressAndThenOr16 (\r | |
| 472 | IN UINTN Address,\r | |
| 473 | IN UINT16 AndData,\r | |
| 474 | IN UINT16 OrData\r | |
| 475 | );\r | |
| 476 | \r | |
| 477 | /**\r | |
| 478 | Reads a bit field of a PCI configuration register.\r | |
| 479 | \r | |
| 480 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
| 481 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 482 | returned.\r | |
| 483 | \r | |
| 484 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 485 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 486 | If StartBit is greater than 15, then ASSERT().\r | |
| 487 | If EndBit is greater than 15, then ASSERT().\r | |
| 488 | If EndBit is less than StartBit, then ASSERT().\r | |
| 489 | \r | |
| 490 | @param Address PCI configuration register to read.\r | |
| 491 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 492 | Range 0..15.\r | |
| 493 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 494 | Range 0..15.\r | |
| 495 | \r | |
| 496 | @return The value of the bit field read from the PCI configuration register.\r | |
| 497 | \r | |
| 498 | **/\r | |
| 499 | UINT16\r | |
| 500 | EFIAPI\r | |
| 501 | PciExpressBitFieldRead16 (\r | |
| 502 | IN UINTN Address,\r | |
| 503 | IN UINTN StartBit,\r | |
| 504 | IN UINTN EndBit\r | |
| 505 | );\r | |
| 506 | \r | |
| 507 | /**\r | |
| 508 | Writes a bit field to a PCI configuration register.\r | |
| 509 | \r | |
| 510 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 511 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 512 | destination PCI configuration register are preserved. The new value of the\r | |
| 513 | 16-bit register is returned.\r | |
| 514 | \r | |
| 515 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 516 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 517 | If StartBit is greater than 15, then ASSERT().\r | |
| 518 | If EndBit is greater than 15, then ASSERT().\r | |
| 519 | If EndBit is less than StartBit, then ASSERT().\r | |
| 520 | \r | |
| 521 | @param Address PCI configuration register to write.\r | |
| 522 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 523 | Range 0..15.\r | |
| 524 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 525 | Range 0..15.\r | |
| 526 | @param Value New value of the bit field.\r | |
| 527 | \r | |
| 528 | @return The value written back to the PCI configuration register.\r | |
| 529 | \r | |
| 530 | **/\r | |
| 531 | UINT16\r | |
| 532 | EFIAPI\r | |
| 533 | PciExpressBitFieldWrite16 (\r | |
| 534 | IN UINTN Address,\r | |
| 535 | IN UINTN StartBit,\r | |
| 536 | IN UINTN EndBit,\r | |
| 537 | IN UINT16 Value\r | |
| 538 | );\r | |
| 539 | \r | |
| 540 | /**\r | |
| 541 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
| 542 | writes the result back to the bit field in the 16-bit port.\r | |
| 543 | \r | |
| 544 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 545 | bitwise inclusive OR between the read result and the value specified by\r | |
| 546 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 547 | specified by Address. The value written to the PCI configuration register is\r | |
| 548 | returned. This function must guarantee that all PCI read and write operations\r | |
| 549 | are serialized. Extra left bits in OrData are stripped.\r | |
| 550 | \r | |
| 551 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 552 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 553 | If StartBit is greater than 15, then ASSERT().\r | |
| 554 | If EndBit is greater than 15, then ASSERT().\r | |
| 555 | If EndBit is less than StartBit, then ASSERT().\r | |
| 556 | \r | |
| 557 | @param Address PCI configuration register to write.\r | |
| 558 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 559 | Range 0..15.\r | |
| 560 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 561 | Range 0..15.\r | |
| 562 | @param OrData The value to OR with the PCI configuration register.\r | |
| 563 | \r | |
| 564 | @return The value written back to the PCI configuration register.\r | |
| 565 | \r | |
| 566 | **/\r | |
| 567 | UINT16\r | |
| 568 | EFIAPI\r | |
| 569 | PciExpressBitFieldOr16 (\r | |
| 570 | IN UINTN Address,\r | |
| 571 | IN UINTN StartBit,\r | |
| 572 | IN UINTN EndBit,\r | |
| 573 | IN UINT16 OrData\r | |
| 574 | );\r | |
| 575 | \r | |
| 576 | /**\r | |
| 577 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
| 578 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
| 579 | \r | |
| 580 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 581 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 582 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 583 | Address. The value written to the PCI configuration register is returned.\r | |
| 584 | This function must guarantee that all PCI read and write operations are\r | |
| 585 | serialized. Extra left bits in AndData are stripped.\r | |
| 586 | \r | |
| 587 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 588 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 589 | If StartBit is greater than 15, then ASSERT().\r | |
| 590 | If EndBit is greater than 15, then ASSERT().\r | |
| 591 | If EndBit is less than StartBit, then ASSERT().\r | |
| 592 | \r | |
| 593 | @param Address PCI configuration register to write.\r | |
| 594 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 595 | Range 0..15.\r | |
| 596 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 597 | Range 0..15.\r | |
| 598 | @param AndData The value to AND with the PCI configuration register.\r | |
| 599 | \r | |
| 600 | @return The value written back to the PCI configuration register.\r | |
| 601 | \r | |
| 602 | **/\r | |
| 603 | UINT16\r | |
| 604 | EFIAPI\r | |
| 605 | PciExpressBitFieldAnd16 (\r | |
| 606 | IN UINTN Address,\r | |
| 607 | IN UINTN StartBit,\r | |
| 608 | IN UINTN EndBit,\r | |
| 609 | IN UINT16 AndData\r | |
| 610 | );\r | |
| 611 | \r | |
| 612 | /**\r | |
| 613 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
| 614 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
| 615 | 16-bit port.\r | |
| 616 | \r | |
| 617 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 618 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
| 619 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
| 620 | configuration register specified by Address. The value written to the PCI\r | |
| 621 | configuration register is returned. This function must guarantee that all PCI\r | |
| 622 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 623 | OrData are stripped.\r | |
| 624 | \r | |
| 625 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 626 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 627 | If StartBit is greater than 15, then ASSERT().\r | |
| 628 | If EndBit is greater than 15, then ASSERT().\r | |
| 629 | If EndBit is less than StartBit, then ASSERT().\r | |
| 630 | \r | |
| 631 | @param Address PCI configuration register to write.\r | |
| 632 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 633 | Range 0..15.\r | |
| 634 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 635 | Range 0..15.\r | |
| 636 | @param AndData The value to AND with the PCI configuration register.\r | |
| 637 | @param OrData The value to OR with the result of the AND operation.\r | |
| 638 | \r | |
| 639 | @return The value written back to the PCI configuration register.\r | |
| 640 | \r | |
| 641 | **/\r | |
| 642 | UINT16\r | |
| 643 | EFIAPI\r | |
| 644 | PciExpressBitFieldAndThenOr16 (\r | |
| 645 | IN UINTN Address,\r | |
| 646 | IN UINTN StartBit,\r | |
| 647 | IN UINTN EndBit,\r | |
| 648 | IN UINT16 AndData,\r | |
| 649 | IN UINT16 OrData\r | |
| 650 | );\r | |
| 651 | \r | |
| 652 | /**\r | |
| 653 | Reads a 32-bit PCI configuration register.\r | |
| 654 | \r | |
| 655 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
| 656 | This function must guarantee that all PCI read and write operations are\r | |
| 657 | serialized.\r | |
| 658 | \r | |
| 659 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 660 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 661 | \r | |
| 662 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 663 | Register.\r | |
| 664 | \r | |
| 665 | @return The read value from the PCI configuration register.\r | |
| 666 | \r | |
| 667 | **/\r | |
| 668 | UINT32\r | |
| 669 | EFIAPI\r | |
| 670 | PciExpressRead32 (\r | |
| 671 | IN UINTN Address\r | |
| 672 | );\r | |
| 673 | \r | |
| 674 | /**\r | |
| 675 | Writes a 32-bit PCI configuration register.\r | |
| 676 | \r | |
| 677 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
| 678 | value specified by Value. Value is returned. This function must guarantee\r | |
| 679 | that all PCI read and write operations are serialized.\r | |
| 680 | \r | |
| 681 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 682 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 683 | \r | |
| 684 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 685 | Register.\r | |
| 686 | @param Value The value to write.\r | |
| 687 | \r | |
| 688 | @return The value written to the PCI configuration register.\r | |
| 689 | \r | |
| 690 | **/\r | |
| 691 | UINT32\r | |
| 692 | EFIAPI\r | |
| 693 | PciExpressWrite32 (\r | |
| 694 | IN UINTN Address,\r | |
| 695 | IN UINT32 Data\r | |
| 696 | );\r | |
| 697 | \r | |
| 698 | /**\r | |
| 699 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
| 700 | a 32-bit value.\r | |
| 701 | \r | |
| 702 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 703 | bitwise inclusive OR between the read result and the value specified by\r | |
| 704 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 705 | specified by Address. The value written to the PCI configuration register is\r | |
| 706 | returned. This function must guarantee that all PCI read and write operations\r | |
| 707 | are serialized.\r | |
| 708 | \r | |
| 709 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 710 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 711 | \r | |
| 712 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 713 | Register.\r | |
| 714 | @param OrData The value to OR with the PCI configuration register.\r | |
| 715 | \r | |
| 716 | @return The value written back to the PCI configuration register.\r | |
| 717 | \r | |
| 718 | **/\r | |
| 719 | UINT32\r | |
| 720 | EFIAPI\r | |
| 721 | PciExpressOr32 (\r | |
| 722 | IN UINTN Address,\r | |
| 723 | IN UINT32 OrData\r | |
| 724 | );\r | |
| 725 | \r | |
| 726 | /**\r | |
| 727 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 728 | value.\r | |
| 729 | \r | |
| 730 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 731 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 732 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 733 | Address. The value written to the PCI configuration register is returned.\r | |
| 734 | This function must guarantee that all PCI read and write operations are\r | |
| 735 | serialized.\r | |
| 736 | \r | |
| 737 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 738 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 739 | \r | |
| 740 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 741 | Register.\r | |
| 742 | @param AndData The value to AND with the PCI configuration register.\r | |
| 743 | \r | |
| 744 | @return The value written back to the PCI configuration register.\r | |
| 745 | \r | |
| 746 | **/\r | |
| 747 | UINT32\r | |
| 748 | EFIAPI\r | |
| 749 | PciExpressAnd32 (\r | |
| 750 | IN UINTN Address,\r | |
| 751 | IN UINT32 AndData\r | |
| 752 | );\r | |
| 753 | \r | |
| 754 | /**\r | |
| 755 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 756 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
| 757 | \r | |
| 758 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 759 | bitwise AND between the read result and the value specified by AndData,\r | |
| 760 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
| 761 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
| 762 | configuration register specified by Address. The value written to the PCI\r | |
| 763 | configuration register is returned. This function must guarantee that all PCI\r | |
| 764 | read and write operations are serialized.\r | |
| 765 | \r | |
| 766 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 767 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 768 | \r | |
| 769 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 770 | Register.\r | |
| 771 | @param AndData The value to AND with the PCI configuration register.\r | |
| 772 | @param OrData The value to OR with the result of the AND operation.\r | |
| 773 | \r | |
| 774 | @return The value written back to the PCI configuration register.\r | |
| 775 | \r | |
| 776 | **/\r | |
| 777 | UINT32\r | |
| 778 | EFIAPI\r | |
| 779 | PciExpressAndThenOr32 (\r | |
| 780 | IN UINTN Address,\r | |
| 781 | IN UINT32 AndData,\r | |
| 782 | IN UINT32 OrData\r | |
| 783 | );\r | |
| 784 | \r | |
| 785 | /**\r | |
| 786 | Reads a bit field of a PCI configuration register.\r | |
| 787 | \r | |
| 788 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
| 789 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 790 | returned.\r | |
| 791 | \r | |
| 792 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 793 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 794 | If StartBit is greater than 31, then ASSERT().\r | |
| 795 | If EndBit is greater than 31, then ASSERT().\r | |
| 796 | If EndBit is less than StartBit, then ASSERT().\r | |
| 797 | \r | |
| 798 | @param Address PCI configuration register to read.\r | |
| 799 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 800 | Range 0..31.\r | |
| 801 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 802 | Range 0..31.\r | |
| 803 | \r | |
| 804 | @return The value of the bit field read from the PCI configuration register.\r | |
| 805 | \r | |
| 806 | **/\r | |
| 807 | UINT32\r | |
| 808 | EFIAPI\r | |
| 809 | PciExpressBitFieldRead32 (\r | |
| 810 | IN UINTN Address,\r | |
| 811 | IN UINTN StartBit,\r | |
| 812 | IN UINTN EndBit\r | |
| 813 | );\r | |
| 814 | \r | |
| 815 | /**\r | |
| 816 | Writes a bit field to a PCI configuration register.\r | |
| 817 | \r | |
| 818 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 819 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 820 | destination PCI configuration register are preserved. The new value of the\r | |
| 821 | 32-bit register is returned.\r | |
| 822 | \r | |
| 823 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 824 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 825 | If StartBit is greater than 31, then ASSERT().\r | |
| 826 | If EndBit is greater than 31, then ASSERT().\r | |
| 827 | If EndBit is less than StartBit, then ASSERT().\r | |
| 828 | \r | |
| 829 | @param Address PCI configuration register to write.\r | |
| 830 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 831 | Range 0..31.\r | |
| 832 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 833 | Range 0..31.\r | |
| 834 | @param Value New value of the bit field.\r | |
| 835 | \r | |
| 836 | @return The value written back to the PCI configuration register.\r | |
| 837 | \r | |
| 838 | **/\r | |
| 839 | UINT32\r | |
| 840 | EFIAPI\r | |
| 841 | PciExpressBitFieldWrite32 (\r | |
| 842 | IN UINTN Address,\r | |
| 843 | IN UINTN StartBit,\r | |
| 844 | IN UINTN EndBit,\r | |
| 845 | IN UINT32 Value\r | |
| 846 | );\r | |
| 847 | \r | |
| 848 | /**\r | |
| 849 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
| 850 | writes the result back to the bit field in the 32-bit port.\r | |
| 851 | \r | |
| 852 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 853 | bitwise inclusive OR between the read result and the value specified by\r | |
| 854 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 855 | specified by Address. The value written to the PCI configuration register is\r | |
| 856 | returned. This function must guarantee that all PCI read and write operations\r | |
| 857 | are serialized. Extra left bits in OrData are stripped.\r | |
| 858 | \r | |
| 859 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 860 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 861 | If StartBit is greater than 31, then ASSERT().\r | |
| 862 | If EndBit is greater than 31, then ASSERT().\r | |
| 863 | If EndBit is less than StartBit, then ASSERT().\r | |
| 864 | \r | |
| 865 | @param Address PCI configuration register to write.\r | |
| 866 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 867 | Range 0..31.\r | |
| 868 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 869 | Range 0..31.\r | |
| 870 | @param OrData The value to OR with the PCI configuration register.\r | |
| 871 | \r | |
| 872 | @return The value written back to the PCI configuration register.\r | |
| 873 | \r | |
| 874 | **/\r | |
| 875 | UINT32\r | |
| 876 | EFIAPI\r | |
| 877 | PciExpressBitFieldOr32 (\r | |
| 878 | IN UINTN Address,\r | |
| 879 | IN UINTN StartBit,\r | |
| 880 | IN UINTN EndBit,\r | |
| 881 | IN UINT32 OrData\r | |
| 882 | );\r | |
| 883 | \r | |
| 884 | /**\r | |
| 885 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
| 886 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
| 887 | \r | |
| 888 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 889 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 890 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 891 | Address. The value written to the PCI configuration register is returned.\r | |
| 892 | This function must guarantee that all PCI read and write operations are\r | |
| 893 | serialized. Extra left bits in AndData are stripped.\r | |
| 894 | \r | |
| 895 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 896 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 897 | If StartBit is greater than 31, then ASSERT().\r | |
| 898 | If EndBit is greater than 31, then ASSERT().\r | |
| 899 | If EndBit is less than StartBit, then ASSERT().\r | |
| 900 | \r | |
| 901 | @param Address PCI configuration register to write.\r | |
| 902 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 903 | Range 0..31.\r | |
| 904 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 905 | Range 0..31.\r | |
| 906 | @param AndData The value to AND with the PCI configuration register.\r | |
| 907 | \r | |
| 908 | @return The value written back to the PCI configuration register.\r | |
| 909 | \r | |
| 910 | **/\r | |
| 911 | UINT32\r | |
| 912 | EFIAPI\r | |
| 913 | PciExpressBitFieldAnd32 (\r | |
| 914 | IN UINTN Address,\r | |
| 915 | IN UINTN StartBit,\r | |
| 916 | IN UINTN EndBit,\r | |
| 917 | IN UINT32 AndData\r | |
| 918 | );\r | |
| 919 | \r | |
| 920 | /**\r | |
| 921 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
| 922 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
| 923 | 32-bit port.\r | |
| 924 | \r | |
| 925 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 926 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
| 927 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
| 928 | configuration register specified by Address. The value written to the PCI\r | |
| 929 | configuration register is returned. This function must guarantee that all PCI\r | |
| 930 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 931 | OrData are stripped.\r | |
| 932 | \r | |
| 933 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 934 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 935 | If StartBit is greater than 31, then ASSERT().\r | |
| 936 | If EndBit is greater than 31, then ASSERT().\r | |
| 937 | If EndBit is less than StartBit, then ASSERT().\r | |
| 938 | \r | |
| 939 | @param Address PCI configuration register to write.\r | |
| 940 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 941 | Range 0..31.\r | |
| 942 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 943 | Range 0..31.\r | |
| 944 | @param AndData The value to AND with the PCI configuration register.\r | |
| 945 | @param OrData The value to OR with the result of the AND operation.\r | |
| 946 | \r | |
| 947 | @return The value written back to the PCI configuration register.\r | |
| 948 | \r | |
| 949 | **/\r | |
| 950 | UINT32\r | |
| 951 | EFIAPI\r | |
| 952 | PciExpressBitFieldAndThenOr32 (\r | |
| 953 | IN UINTN Address,\r | |
| 954 | IN UINTN StartBit,\r | |
| 955 | IN UINTN EndBit,\r | |
| 956 | IN UINT32 AndData,\r | |
| 957 | IN UINT32 OrData\r | |
| 958 | );\r | |
| 959 | \r | |
| 960 | /**\r | |
| 961 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
| 962 | \r | |
| 963 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
| 964 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
| 965 | configuration registers from a single PCI function to be read. Size is\r | |
| 966 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
| 967 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
| 968 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
| 969 | end of the range.\r | |
| 970 | \r | |
| 971 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 972 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 973 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 974 | \r | |
| 975 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
| 976 | Function and Register.\r | |
| 977 | @param Size Size in bytes of the transfer.\r | |
| 978 | @param Buffer Pointer to a buffer receiving the data read.\r | |
| 979 | \r | |
| 980 | @return Size\r | |
| 981 | \r | |
| 982 | **/\r | |
| 983 | UINTN\r | |
| 984 | EFIAPI\r | |
| 985 | PciExpressReadBuffer (\r | |
| 986 | IN UINTN StartAddress,\r | |
| 987 | IN UINTN Size,\r | |
| 988 | OUT VOID *Buffer\r | |
| 989 | );\r | |
| 990 | \r | |
| 991 | /**\r | |
| 992 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
| 993 | configuration space.\r | |
| 994 | \r | |
| 995 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
| 996 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
| 997 | configuration registers from a single PCI function to be written. Size is\r | |
| 998 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
| 999 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
| 1000 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
| 1001 | and the end of the range.\r | |
| 1002 | \r | |
| 1003 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1004 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 1005 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1006 | \r | |
| 1007 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
| 1008 | Function and Register.\r | |
| 1009 | @param Size Size in bytes of the transfer.\r | |
| 1010 | @param Buffer Pointer to a buffer containing the data to write.\r | |
| 1011 | \r | |
| 1012 | @return Size\r | |
| 1013 | \r | |
| 1014 | **/\r | |
| 1015 | UINTN\r | |
| 1016 | EFIAPI\r | |
| 1017 | PciExpressWriteBuffer (\r | |
| 1018 | IN UINTN StartAddress,\r | |
| 1019 | IN UINTN Size,\r | |
| 1020 | IN VOID *Buffer\r | |
| 1021 | );\r | |
| 1022 | \r | |
| 1023 | #endif\r |