[mirror_edk2.git] / EdkCompatibilityPkg / Sample / Tools / Source / GenPage / VirtualMemory.h

/*++ \r
\r
Copyright 2006 - 2007, Intel Corporation                                                         \r
All rights reserved. This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
  VirtualMemory.h\r
  \r
Abstract:\r
\r
  x64 Long Mode Virtual Memory Management Definitions  \r
\r
  References:\r
    1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
    4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
--*/\r
\r
#ifndef _VIRTUAL_MEMORY_H_\r
#define _VIRTUAL_MEMORY_H_\r
\r
#include "Tiano.h"\r
\r
#pragma pack(1)\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
\r
//\r
// Page-Directory Offset 4K\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:1;             // Must Be Zero\r
    UINT64  Reserved2:1;              // Reserved\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} X64_PAGE_DIRECTORY_ENTRY_4K;\r
\r
//\r
// Page Table Entry 4K\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  PAT:1;                    // 0 = Ignore Page Attribute Table \r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} X64_PAGE_TABLE_ENTRY_4K;\r
\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1 \r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} X64_PAGE_TABLE_ENTRY_2M;\r
\r
#pragma pack()\r
\r
#endif \r
Commit	Line	Data
3eb9473e	1	/*++ \r
	2	\r
	3	Copyright 2006 - 2007, Intel Corporation \r
	4	All rights reserved. This program and the accompanying materials \r
	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	VirtualMemory.h\r
	14	\r
	15	Abstract:\r
	16	\r
	17	x64 Long Mode Virtual Memory Management Definitions \r
	18	\r
	19	References:\r
	20	1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	21	2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	22	3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
	23	4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
	24	--*/\r
	25	\r
	26	#ifndef _VIRTUAL_MEMORY_H_\r
	27	#define _VIRTUAL_MEMORY_H_\r
	28	\r
	29	#include "Tiano.h"\r
	30	\r
	31	#pragma pack(1)\r
	32	\r
	33	//\r
	34	// Page-Map Level-4 Offset (PML4) and\r
	35	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	36	//\r
	37	\r
	38	typedef union {\r
	39	struct {\r
	40	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	41	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	42	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	43	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	44	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	45	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	46	UINT64 Reserved:1; // Reserved\r
	47	UINT64 MustBeZero:2; // Must Be Zero\r
	48	UINT64 Available:3; // Available for use by system software\r
	49	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	50	UINT64 AvabilableHigh:11; // Available for use by system software\r
	51	UINT64 Nx:1; // No Execute bit\r
	52	} Bits;\r
	53	UINT64 Uint64;\r
	54	} X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r
	55	\r
	56	//\r
	57	// Page-Directory Offset 4K\r
	58	//\r
	59	typedef union {\r
	60	struct {\r
	61	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	62	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	63	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	64	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
65	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
66	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
67	UINT64 Reserved:1; // Reserved\r
68	UINT64 MustBeZero:1; // Must Be Zero\r
69	UINT64 Reserved2:1; // Reserved\r
70	UINT64 Available:3; // Available for use by system software\r
71	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
72	UINT64 AvabilableHigh:11; // Available for use by system software\r
73	UINT64 Nx:1; // No Execute bit\r
74	} Bits;\r
75	UINT64 Uint64;\r
76	} X64_PAGE_DIRECTORY_ENTRY_4K;\r
77	\r
78	//\r
79	// Page Table Entry 4K\r
80	//\r
81	typedef union {\r
82	struct {\r
83	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
84	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
85	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
86	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
87	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
88	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
89	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
90	UINT64 PAT:1; // 0 = Ignore Page Attribute Table \r
91	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
92	UINT64 Available:3; // Available for use by system software\r
93	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
94	UINT64 AvabilableHigh:11; // Available for use by system software\r
95	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
96	} Bits;\r
97	UINT64 Uint64;\r
98	} X64_PAGE_TABLE_ENTRY_4K;\r
99	\r
100	\r
101	//\r
102	// Page Table Entry 2MB\r
103	//\r
104	typedef union {\r
105	struct {\r
106	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
107	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
108	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
109	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
110	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
111	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
112	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
113	UINT64 MustBe1:1; // Must be 1 \r
114	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
115	UINT64 Available:3; // Available for use by system software\r
116	UINT64 PAT:1; //\r
117	UINT64 MustBeZero:8; // Must be zero;\r
118	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
119	UINT64 AvabilableHigh:11; // Available for use by system software\r
120	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
121	} Bits;\r
122	UINT64 Uint64;\r
123	} X64_PAGE_TABLE_ENTRY_2M;\r
124	\r
125	#pragma pack()\r
126	\r
127	#endif \r