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Add DevicePathUtilities DevicePathToText DevciePathFromText USB2HostController protocols
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
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562d2849 1/*++\r
2\r
3Copyright (c) 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 Ehci.h\r
15 \r
16Abstract: \r
17 \r
18\r
19Revision History\r
20--*/\r
21\r
22#ifndef _EHCI_H\r
23#define _EHCI_H\r
24\r
25//\r
26// Universal Host Controller Interface data structures and defines\r
27//\r
28#include <IndustryStandard/pci22.h>\r
29\r
30#ifdef EFI_DEBUG\r
31extern UINTN gEHCDebugLevel;\r
32extern UINTN gEHCErrorLevel;\r
33#endif\r
34\r
35#define STALL_1_MACRO_SECOND 1\r
36#define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND\r
37#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r
38\r
39#define SETUP_PACKET_PID_CODE 0x02\r
40#define INPUT_PACKET_PID_CODE 0x01\r
41#define OUTPUT_PACKET_PID_CODE 0x0\r
42\r
43#define ITD_SELECT_TYPE 0x0\r
44#define QH_SELECT_TYPE 0x01\r
45#define SITD_SELECT_TYPE 0x02\r
46#define FSTN_SELECT_TYPE 0x03\r
47\r
48#define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND\r
49#define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND\r
50#define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND\r
51#define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND\r
52#define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND\r
53#define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND\r
54\r
55#define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */\r
56\r
57#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1\r
58\r
59#define EHCI_MIN_PACKET_SIZE 8\r
60#define EHCI_MAX_PACKET_SIZE 1024\r
61#define EHCI_MAX_FRAME_LIST_LENGTH 1024\r
62#define EHCI_BLOCK_SIZE_WITH_TT 64\r
63#define EHCI_BLOCK_SIZE 512\r
64#define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)\r
65\r
66#define NAK_COUNT_RELOAD 3\r
67#define QTD_ERROR_COUNTER 1\r
68#define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1\r
69\r
70#define QTD_STATUS_ACTIVE 0x80\r
71#define QTD_STATUS_HALTED 0x40\r
72#define QTD_STATUS_BUFFER_ERR 0x20\r
73#define QTD_STATUS_BABBLE_ERR 0x10\r
74#define QTD_STATUS_TRANSACTION_ERR 0x08\r
75#define QTD_STATUS_DO_STOP_SPLIT 0x02\r
76#define QTD_STATUS_DO_START_SPLIT 0\r
77#define QTD_STATUS_DO_PING 0x01\r
78#define QTD_STATUS_DO_OUT 0\r
79\r
80#define DATA0 0\r
81#define DATA1 1\r
82\r
83#define MICRO_FRAME_0_CHANNEL 0x01\r
84#define MICRO_FRAME_1_CHANNEL 0x02\r
85#define MICRO_FRAME_2_CHANNEL 0x04\r
86#define MICRO_FRAME_3_CHANNEL 0x08\r
87#define MICRO_FRAME_4_CHANNEL 0x10\r
88#define MICRO_FRAME_5_CHANNEL 0x20\r
89#define MICRO_FRAME_6_CHANNEL 0x40\r
90#define MICRO_FRAME_7_CHANNEL 0x80\r
91\r
92#define CONTROL_TRANSFER 0x01\r
93#define BULK_TRANSFER 0x02\r
94#define SYNC_INTERRUPT_TRANSFER 0x04\r
95#define ASYNC_INTERRUPT_TRANSFER 0x08\r
96#define SYNC_ISOCHRONOUS_TRANSFER 0x10\r
97#define ASYNC_ISOCHRONOUS_TRANSFER 0x20\r
98\r
99\r
100//\r
101// Enhanced Host Controller Registers definitions\r
102//\r
103extern UINT32 mUsbCapabilityLen;\r
104extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
105extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
106\r
107#define USBCMD 0x0 /* Command Register Offset 00-03h */\r
108#define USBCMD_RS 0x01 /* Run / Stop */\r
109#define USBCMD_HCRESET 0x02 /* Host controller reset */\r
110#define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */\r
111#define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */\r
112#define USBCMD_PSE 0x10 /* Periodic schedule enable */\r
113#define USBCMD_ASE 0x20 /* Asynchronous schedule enable */\r
114#define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */\r
115\r
116#define USBSTS 0x04 /* Statue Register Offset 04-07h */\r
117#define USBSTS_HSE 0x10 /* Host system error */\r
118#define USBSTS_IAA 0x20 /* Interrupt on async advance */\r
119#define USBSTS_HCH 0x1000 /* Host controller halted */\r
120#define USBSTS_PSS 0x4000 /* Periodic schedule status */\r
121#define USBSTS_ASS 0x8000 /* Asynchronous schedule status */\r
122\r
123#define USBINTR 0x08 /* Command Register Offset 08-0bh */\r
124\r
125#define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */\r
126\r
127#define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */\r
128\r
129#define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */\r
130\r
131#define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */\r
132\r
133#define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */\r
134#define CONFIGFLAG_CF 0x01 /* Configure Flag */\r
135\r
136#define PORTSC 0x44 /* Port Status/Control Offset 44-47h */\r
137#define PORTSC_CCS 0x01 /* Current Connect Status*/\r
138#define PORTSC_CSC 0x02 /* Connect Status Change */\r
139#define PORTSC_PED 0x04 /* Port Enable / Disable */\r
140#define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */\r
141#define PORTSC_OCA 0x10 /* Over current Active */\r
142#define PORTSC_OCC 0x20 /* Over current Change */\r
143#define PORTSC_FPR 0x40 /* Force Port Resume */\r
144#define PORTSC_SUSP 0x80 /* Port Suspend State */\r
145#define PORTSC_PR 0x100 /* Port Reset */\r
146#define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */\r
147#define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */\r
148#define PORTSC_PP 0x1000 /* Port Power */\r
149#define PORTSC_PO 0x2000 /* Port Owner */\r
150\r
151#define CAPLENGTH 0 /* Capability Register Length 00h */\r
152\r
153#define HCIVERSION 0x02 /* Interface Version Number 02-03h */\r
154\r
155#define HCSPARAMS 0x04 /* Structural Parameters 04-07h */\r
156#define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */\r
157\r
158#define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */\r
159#define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */\r
160#define HCCP_PFLF 0x02 /* Programmable Frame List Flag */\r
161#define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */\r
162\r
163#define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */\r
164\r
165#define CLASSC 0x09 /* Class Code 09-0bh */\r
166\r
167#define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */\r
168\r
169#define SBRN 0x60 /* Serial Bus Release Number 60h */\r
170\r
171#define FLADJ 0x61 /* Frame Length Adjustment Register 61h */\r
172\r
173#define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */\r
174\r
175//\r
176// PCI Configuration Registers\r
177//\r
178#define EHCI_PCI_CLASSC 0x09\r
179#define EHCI_PCI_MEMORY_BASE 0x10\r
180\r
181//\r
182// Memory Offset Registers\r
183//\r
184#define EHCI_MEMORY_CAPLENGTH 0x0\r
185#define EHCI_MEMORY_CONFIGFLAG 0x40\r
186\r
187//\r
188// USB Base Class Code,Sub-Class Code and Programming Interface\r
189//\r
190#define PCI_CLASSC_PI_EHCI 0x20\r
191\r
192#define SETUP_PACKET_ID 0x2D\r
193#define INPUT_PACKET_ID 0x69\r
194#define OUTPUT_PACKET_ID 0xE1\r
195#define ERROR_PACKET_ID 0x55\r
196\r
197#define bit(a) 1 << (a)\r
198\r
199#define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))\r
200#define GET_32B_TO_63B(Addr) ((((UINTN) Addr) >> 32) & (0xffffffff))\r
201\r
202\r
203//\r
204// Ehci Data and Ctrl Structures\r
205//\r
206#pragma pack(1)\r
207\r
208typedef struct {\r
209 UINT8 PI;\r
210 UINT8 SubClassCode;\r
211 UINT8 BaseCode;\r
212} USB_CLASSC;\r
213\r
214typedef struct {\r
215 UINT32 NextQtdTerminate : 1;\r
216 UINT32 Rsvd1 : 4;\r
217 UINT32 NextQtdPointer : 27;\r
218\r
219 UINT32 AltNextQtdTerminate : 1;\r
220 UINT32 Rsvd2 : 4;\r
221 UINT32 AltNextQtdPointer : 27;\r
222\r
223 UINT32 Status : 8;\r
224 UINT32 PidCode : 2;\r
225 UINT32 ErrorCount : 2;\r
226 UINT32 CurrentPage : 3;\r
227 UINT32 InterruptOnComplete : 1;\r
228 UINT32 TotalBytes : 15;\r
229 UINT32 DataToggle : 1;\r
230\r
231 UINT32 CurrentOffset : 12;\r
232 UINT32 BufferPointer0 : 20;\r
233\r
234 UINT32 Rsvd3 : 12;\r
235 UINT32 BufferPointer1 : 20;\r
236\r
237 UINT32 Rsvd4 : 12;\r
238 UINT32 BufferPointer2 : 20;\r
239\r
240 UINT32 Rsvd5 : 12;\r
241 UINT32 BufferPointer3 : 20;\r
242\r
243 UINT32 Rsvd6 : 12;\r
244 UINT32 BufferPointer4 : 20;\r
245\r
246 UINT32 ExtBufferPointer0;\r
247 UINT32 ExtBufferPointer1;\r
248 UINT32 ExtBufferPointer2;\r
249 UINT32 ExtBufferPointer3;\r
250 UINT32 ExtBufferPointer4;\r
251} EHCI_QTD_HW;\r
252\r
253typedef struct {\r
254 UINT32 QhTerminate : 1;\r
255 UINT32 SelectType : 2;\r
256 UINT32 Rsvd1 : 2;\r
257 UINT32 QhHorizontalPointer : 27;\r
258\r
259 UINT32 DeviceAddr : 7;\r
260 UINT32 Inactive : 1;\r
261 UINT32 EndpointNum : 4;\r
262 UINT32 EndpointSpeed : 2;\r
263 UINT32 DataToggleControl : 1;\r
264 UINT32 HeadReclamationFlag : 1;\r
265 UINT32 MaxPacketLen : 11;\r
266 UINT32 ControlEndpointFlag : 1;\r
267 UINT32 NakCountReload : 4;\r
268\r
269 UINT32 InerruptScheduleMask : 8;\r
270 UINT32 SplitComletionMask : 8;\r
271 UINT32 HubAddr : 7;\r
272 UINT32 PortNum : 7;\r
273 UINT32 Multiplier : 2;\r
274\r
275 UINT32 Rsvd2 : 5;\r
276 UINT32 CurrentQtdPointer : 27;\r
277\r
278 UINT32 NextQtdTerminate : 1;\r
279 UINT32 Rsvd3 : 4;\r
280 UINT32 NextQtdPointer : 27;\r
281\r
282 UINT32 AltNextQtdTerminate : 1;\r
283 UINT32 NakCount : 4;\r
284 UINT32 AltNextQtdPointer : 27;\r
285\r
286 UINT32 Status : 8;\r
287 UINT32 PidCode : 2;\r
288 UINT32 ErrorCount : 2;\r
289 UINT32 CurrentPage : 3;\r
290 UINT32 InterruptOnComplete : 1;\r
291 UINT32 TotalBytes : 15;\r
292 UINT32 DataToggle : 1;\r
293\r
294 UINT32 CurrentOffset : 12;\r
295 UINT32 BufferPointer0 : 20;\r
296\r
297 UINT32 CompleteSplitMask : 8;\r
298 UINT32 Rsvd4 : 4;\r
299 UINT32 BufferPointer1 : 20;\r
300\r
301 UINT32 FrameTag : 5;\r
302 UINT32 SplitBytes : 7;\r
303 UINT32 BufferPointer2 : 20;\r
304\r
305 UINT32 Rsvd5 : 12;\r
306 UINT32 BufferPointer3 : 20;\r
307\r
308 UINT32 Rsvd6 : 12;\r
309 UINT32 BufferPointer4 : 20;\r
310\r
311 UINT32 ExtBufferPointer0;\r
312 UINT32 ExtBufferPointer1;\r
313 UINT32 ExtBufferPointer2;\r
314 UINT32 ExtBufferPointer3;\r
315 UINT32 ExtBufferPointer4;\r
316} EHCI_QH_HW;\r
317\r
318typedef struct {\r
319 UINT32 LinkTerminate : 1;\r
320 UINT32 SelectType : 2;\r
321 UINT32 Rsvd : 2;\r
322 UINT32 LinkPointer : 27;\r
323} FRAME_LIST_ENTRY;\r
324\r
325#pragma pack()\r
326\r
327typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;\r
328typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;\r
329typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;\r
330\r
331typedef struct _EHCI_QTD_ENTITY {\r
332 EHCI_QTD_HW Qtd;\r
333 UINT32 TotalBytes;\r
334 UINT32 StaticTotalBytes;\r
335 UINT32 StaticCurrentOffset;\r
336 EHCI_QTD_ENTITY *Prev;\r
337 EHCI_QTD_ENTITY *Next;\r
338 EHCI_QTD_ENTITY *AltNext;\r
339 EHCI_QH_ENTITY *SelfQh;\r
340} EHCI_QTD_ENTITY;\r
341\r
342typedef struct _EHCI_QH_ENTITY {\r
343 EHCI_QH_HW Qh;\r
344 EHCI_QH_ENTITY *Next;\r
345 EHCI_QH_ENTITY *Prev;\r
346 EHCI_QTD_ENTITY *FirstQtdPtr;\r
347 EHCI_QTD_ENTITY *LastQtdPtr;\r
348 EHCI_QTD_ENTITY *AltQtdPtr;\r
349 UINTN Interval;\r
350 UINT8 TransferType;\r
351} EHCI_QH_ENTITY;\r
352\r
353#define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)\r
354#define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)\r
355\r
356\r
357//\r
358// Ehci Managment Structures\r
359//\r
360#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
361\r
362#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
363\r
364typedef struct _LIST_HEAD {\r
365 struct _LIST_HEAD *pre;\r
366 struct _LIST_HEAD *next;\r
367} LIST_HEAD;\r
368\r
369typedef struct _EHCI_ASYNC_REQUEST {\r
370 UINT8 TransferType;\r
371 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;\r
372 VOID *Context;\r
373 EHCI_ASYNC_REQUEST *Prev;\r
374 EHCI_ASYNC_REQUEST *Next;\r
375 EHCI_QH_ENTITY *QhPtr;\r
376} EHCI_ASYNC_REQUEST;\r
377\r
378typedef struct _MEMORY_MANAGE_HEADER {\r
379 UINT8 *BitArrayPtr;\r
380 UINTN BitArraySizeInBytes;\r
381 UINT8 *MemoryBlockPtr;\r
382 UINTN MemoryBlockSizeInBytes;\r
383 VOID *Mapping;\r
384 struct _MEMORY_MANAGE_HEADER *Next;\r
385} MEMORY_MANAGE_HEADER;\r
386\r
387typedef struct _USB2_HC_DEV {\r
388 UINTN Signature;\r
389 EFI_PCI_IO_PROTOCOL *PciIo;\r
390 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
391 UINTN PeriodicFrameListLength;\r
392 VOID *PeriodicFrameListBuffer;\r
393 VOID *PeriodicFrameListMap;\r
394 VOID *AsyncList;\r
395 EHCI_ASYNC_REQUEST *AsyncRequestList;\r
396 EFI_EVENT AsyncRequestEvent;\r
397 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
398 MEMORY_MANAGE_HEADER *MemoryHeader;\r
399 UINT8 Is64BitCapable;\r
400 UINT32 High32BitAddr;\r
401} USB2_HC_DEV;\r
402\r
403\r
404//\r
405// Internal Functions Declaration\r
406//\r
407\r
408//\r
409// EhciMem Functions\r
410//\r
411EFI_STATUS\r
412CreateMemoryBlock (\r
413 IN USB2_HC_DEV *HcDev,\r
414 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
415 IN UINTN MemoryBlockSizeInPages\r
416 )\r
417/*++\r
418\r
419Routine Description:\r
420\r
421 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,\r
422 and use PciIo->Map to map the common buffer for Bus Master Read/Write.\r
423\r
424Arguments:\r
425\r
426 HcDev - USB2_HC_DEV\r
427 MemoryHeader - MEMORY_MANAGE_HEADER to output\r
428 MemoryBlockSizeInPages - MemoryBlockSizeInPages\r
429 \r
430Returns:\r
431\r
432 EFI_SUCCESS Success\r
433 EFI_OUT_OF_RESOURCES Fail for no resources\r
434 EFI_UNSUPPORTED Unsupported currently\r
435 \r
436--*/\r
437;\r
438\r
439EFI_STATUS\r
440FreeMemoryHeader (\r
441 IN USB2_HC_DEV *HcDev,\r
442 IN MEMORY_MANAGE_HEADER *MemoryHeader\r
443 )\r
444/*++\r
445\r
446Routine Description:\r
447\r
448 Free Memory Header\r
449\r
450Arguments:\r
451\r
452 HcDev - USB2_HC_DEV\r
453 MemoryHeader - MemoryHeader to be freed\r
454\r
455Returns:\r
456\r
457 EFI_SUCCESS Success\r
458 EFI_INVALID_PARAMETER Parameter is error\r
459\r
460--*/\r
461;\r
462\r
463VOID\r
464InsertMemoryHeaderToList (\r
465 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
466 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
467 )\r
468/*++\r
469\r
470Routine Description:\r
471\r
472 Insert Memory Header To List\r
473\r
474Arguments:\r
475\r
476 MemoryHeader - MEMORY_MANAGE_HEADER\r
477 NewMemoryHeader - MEMORY_MANAGE_HEADER\r
478\r
479Returns:\r
480\r
481 VOID\r
482\r
483--*/\r
484;\r
485\r
486EFI_STATUS\r
487AllocMemInMemoryBlock (\r
488 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
489 OUT VOID **Pool,\r
490 IN UINTN NumberOfMemoryUnit\r
491 )\r
492/*++\r
493\r
494Routine Description:\r
495\r
496 Alloc Memory In MemoryBlock\r
497\r
498Arguments:\r
499\r
500 MemoryHeader - MEMORY_MANAGE_HEADER\r
501 Pool - Place to store pointer to memory\r
502 NumberOfMemoryUnit - Number Of Memory Unit\r
503\r
504Returns:\r
505\r
506 EFI_SUCCESS Success\r
507 EFI_NOT_FOUND Can't find the free memory \r
508\r
509--*/\r
510;\r
511\r
512BOOLEAN\r
513IsMemoryBlockEmptied (\r
514 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
515 )\r
516/*++\r
517\r
518Routine Description:\r
519\r
520 Is Memory Block Emptied\r
521\r
522Arguments:\r
523\r
524 MemoryHeaderPtr - MEMORY_MANAGE_HEADER\r
525\r
526Returns:\r
527\r
528 TRUE Empty\r
529 FALSE Not Empty \r
530\r
531--*/\r
532;\r
533\r
534VOID\r
535DelinkMemoryBlock (\r
536 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
537 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader\r
538 )\r
539/*++\r
540\r
541Routine Description:\r
542\r
543 Delink Memory Block\r
544\r
545Arguments:\r
546\r
547 FirstMemoryHeader - MEMORY_MANAGE_HEADER\r
548 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER\r
549\r
550Returns:\r
551\r
552 VOID\r
553\r
554--*/\r
555;\r
556\r
557EFI_STATUS\r
558InitialMemoryManagement (\r
559 IN USB2_HC_DEV *HcDev\r
560 )\r
561/*++\r
562\r
563Routine Description:\r
564\r
565 Initialize Memory Management\r
566\r
567Arguments:\r
568\r
569 HcDev - USB2_HC_DEV\r
570\r
571Returns:\r
572\r
573 EFI_SUCCESS Success\r
574 EFI_DEVICE_ERROR Fail\r
575\r
576--*/\r
577;\r
578\r
579EFI_STATUS\r
580DeinitialMemoryManagement (\r
581 IN USB2_HC_DEV *HcDev\r
582 )\r
583/*++\r
584\r
585Routine Description:\r
586\r
587 Deinitialize Memory Management\r
588\r
589Arguments:\r
590\r
591 HcDev - USB2_HC_DEV\r
592\r
593Returns:\r
594\r
595 EFI_SUCCESS Success\r
596 EFI_DEVICE_ERROR Fail\r
597 \r
598--*/\r
599;\r
600\r
601EFI_STATUS\r
602EhciAllocatePool (\r
603 IN USB2_HC_DEV *HcDev,\r
604 OUT UINT8 **Pool,\r
605 IN UINTN AllocSize\r
606 )\r
607/*++\r
608\r
609Routine Description:\r
610\r
611 Ehci Allocate Pool\r
612\r
613Arguments:\r
614\r
615 HcDev - USB2_HC_DEV\r
616 Pool - Place to store pointer to the memory buffer\r
617 AllocSize - Alloc Size\r
618\r
619Returns:\r
620\r
621 EFI_SUCCESS Success\r
622 EFI_DEVICE_ERROR Fail\r
623 \r
624--*/\r
625;\r
626\r
627VOID\r
628EhciFreePool (\r
629 IN USB2_HC_DEV *HcDev,\r
630 IN UINT8 *Pool,\r
631 IN UINTN AllocSize\r
632 )\r
633/*++\r
634\r
635Routine Description:\r
636\r
637 Uhci Free Pool\r
638\r
639Arguments:\r
640\r
641 HcDev - USB_HC_DEV\r
642 Pool - Pool to free\r
643 AllocSize - Pool size\r
644\r
645Returns:\r
646\r
647 VOID\r
648\r
649--*/\r
650;\r
651\r
652//\r
653// EhciReg Functions\r
654//\r
655EFI_STATUS\r
656ReadEhcCapabiltiyReg (\r
657 IN USB2_HC_DEV *HcDev,\r
658 IN UINT32 CapabiltiyRegAddr,\r
659 IN OUT UINT32 *Data\r
660 )\r
661/*++\r
662\r
663Routine Description:\r
664\r
665 Read Ehc Capabitlity register\r
666 \r
667Arguments:\r
668\r
669 HcDev - USB2_HC_DEV \r
670 CapabiltiyRegAddr - Ehc Capability register address\r
671 Data - A pointer to data read from register\r
672 \r
673Returns:\r
674\r
675 EFI_SUCCESS Success\r
676 EFI_DEVICE_ERROR Fail\r
677 \r
678--*/\r
679;\r
680\r
681EFI_STATUS\r
682ReadEhcOperationalReg (\r
683 IN USB2_HC_DEV *HcDev,\r
684 IN UINT32 OperationalRegAddr,\r
685 IN OUT UINT32 *Data\r
686 )\r
687/*++\r
688\r
689Routine Description:\r
690\r
691 Read Ehc Operation register\r
692 \r
693Arguments:\r
694\r
695 HcDev - USB2_HC_DEV \r
696 OperationalRegAddr - Ehc Operation register address\r
697 Data - A pointer to data read from register\r
698 \r
699Returns:\r
700\r
701 EFI_SUCCESS Success\r
702 EFI_DEVICE_ERROR Fail\r
703 \r
704--*/\r
705;\r
706\r
707EFI_STATUS\r
708WriteEhcOperationalReg (\r
709 IN USB2_HC_DEV *HcDev,\r
710 IN UINT32 OperationalRegAddr,\r
711 IN UINT32 Data\r
712 )\r
713/*++\r
714\r
715Routine Description:\r
716\r
717 Write Ehc Operation register\r
718 \r
719Arguments:\r
720\r
721 HcDev - USB2_HC_DEV \r
722 OperationalRegAddr - Ehc Operation register address\r
723 Data - 32bit write to register\r
724 \r
725Returns:\r
726\r
727 EFI_SUCCESS Success\r
728 EFI_DEVICE_ERROR Fail\r
729 \r
730--*/\r
731;\r
732\r
733EFI_STATUS\r
734SetEhcDoorbell (\r
735 IN USB2_HC_DEV *HcDev\r
736 )\r
737/*++\r
738\r
739Routine Description:\r
740\r
741 Set Ehc door bell bit\r
742 \r
743Arguments:\r
744\r
745 HcDev - USB2_HC_DEV \r
746 \r
747Returns:\r
748\r
749 EFI_SUCCESS Success\r
750 EFI_DEVICE_ERROR Fail\r
751 \r
752--*/\r
753;\r
754\r
755EFI_STATUS\r
756SetFrameListLen (\r
757 IN USB2_HC_DEV *HcDev,\r
758 IN UINTN Length\r
759 )\r
760/*++\r
761\r
762Routine Description:\r
763\r
764 Set the length of Frame List\r
765 \r
766Arguments:\r
767\r
768 HcDev - USB2_HC_DEV \r
769 Length - the required length of frame list\r
770 \r
771Returns:\r
772\r
773 EFI_SUCCESS Success\r
774 EFI_INVALID_PARAMETER Invalid parameter\r
775 EFI_DEVICE_ERROR Fail\r
776 \r
777--*/\r
778;\r
779\r
780BOOLEAN\r
781IsFrameListProgrammable (\r
782 IN USB2_HC_DEV *HcDev\r
783 )\r
784/*++\r
785\r
786Routine Description:\r
787\r
788 Whether frame list is programmable\r
789 \r
790Arguments:\r
791\r
792 HcDev - USB2_HC_DEV \r
793 \r
794Returns:\r
795\r
796 TRUE Programmable\r
797 FALSE Unprogrammable\r
798 \r
799--*/\r
800;\r
801\r
802BOOLEAN\r
803IsPeriodicScheduleEnabled (\r
804 IN USB2_HC_DEV *HcDev\r
805 )\r
806/*++\r
807\r
808Routine Description:\r
809\r
810 Whether periodic schedule is enabled\r
811 \r
812Arguments:\r
813\r
814 HcDev - USB2_HC_DEV \r
815 \r
816Returns:\r
817\r
818 TRUE Enabled\r
819 FALSE Disabled\r
820 \r
821--*/\r
822;\r
823\r
824BOOLEAN\r
825IsAsyncScheduleEnabled (\r
826 IN USB2_HC_DEV *HcDev\r
827 )\r
828/*++\r
829\r
830Routine Description:\r
831\r
832 Whether asynchronous schedule is enabled\r
833 \r
834Arguments:\r
835\r
836 HcDev - USB2_HC_DEV \r
837 \r
838Returns:\r
839\r
840 TRUE Enabled\r
841 FALSE Disabled\r
842 \r
843--*/\r
844;\r
845\r
846BOOLEAN\r
847IsEhcPortEnabled (\r
848 IN USB2_HC_DEV *HcDev,\r
849 IN UINT8 PortNum\r
850 )\r
851/*++\r
852\r
853Routine Description:\r
854\r
855 Whether port is enabled\r
856 \r
857Arguments:\r
858\r
859 HcDev - USB2_HC_DEV \r
860 \r
861Returns:\r
862\r
863 TRUE Enabled\r
864 FALSE Disabled\r
865 \r
866--*/\r
867;\r
868\r
869BOOLEAN\r
870IsEhcReseted (\r
871 IN USB2_HC_DEV *HcDev\r
872 )\r
873/*++\r
874\r
875Routine Description:\r
876\r
877 Whether Ehc is halted\r
878 \r
879Arguments:\r
880\r
881 HcDev - USB2_HC_DEV \r
882 \r
883Returns:\r
884\r
885 TRUE Reseted\r
886 FALSE Unreseted\r
887 \r
888--*/\r
889;\r
890\r
891BOOLEAN\r
892IsEhcHalted (\r
893 IN USB2_HC_DEV *HcDev\r
894 )\r
895/*++\r
896\r
897Routine Description:\r
898\r
899 Whether Ehc is halted\r
900 \r
901Arguments:\r
902\r
903 HcDev - USB2_HC_DEV \r
904 \r
905Returns:\r
906\r
907 TRUE Halted\r
908 FALSE Not halted\r
909 \r
910--*/\r
911;\r
912\r
913BOOLEAN\r
914IsEhcSysError (\r
915 IN USB2_HC_DEV *HcDev\r
916 )\r
917/*++\r
918\r
919Routine Description:\r
920\r
921 Whether Ehc is system error\r
922 \r
923Arguments:\r
924\r
925 HcDev - USB2_HC_DEV \r
926 \r
927Returns:\r
928\r
929 TRUE System error\r
930 FALSE No system error\r
931 \r
932--*/\r
933;\r
934\r
935BOOLEAN\r
936IsHighSpeedDevice (\r
937 IN EFI_USB2_HC_PROTOCOL *This,\r
938 IN UINT8 PortNum \r
939 )\r
940/*++\r
941\r
942Routine Description:\r
943\r
944 Whether high speed device attached\r
945 \r
946Arguments:\r
947\r
948 HcDev - USB2_HC_DEV \r
949 \r
950Returns:\r
951\r
952 TRUE High speed\r
953 FALSE Full speed\r
954 \r
955--*/\r
956;\r
957\r
958EFI_STATUS\r
959WaitForEhcReset (\r
960 IN USB2_HC_DEV *HcDev,\r
961 IN UINTN Timeout\r
962 )\r
963/*++\r
964\r
965Routine Description:\r
966\r
967 wait for Ehc reset or timeout\r
968 \r
969Arguments:\r
970\r
971 HcDev - USB2_HC_DEV \r
972 Timeout - timeout threshold\r
973 \r
974Returns:\r
975\r
976 EFI_SUCCESS Success\r
977 EFI_TIMEOUT Timeout\r
978 \r
979--*/\r
980;\r
981\r
982EFI_STATUS\r
983WaitForEhcHalt (\r
984 IN USB2_HC_DEV *HcDev,\r
985 IN UINTN Timeout\r
986 )\r
987/*++\r
988\r
989Routine Description:\r
990\r
991 wait for Ehc halt or timeout\r
992 \r
993Arguments:\r
994\r
995 HcDev - USB2_HC_DEV \r
996 Timeout - timeout threshold\r
997 \r
998Returns:\r
999\r
1000 EFI_SUCCESS Success\r
1001 EFI_TIMEOUT Timeout\r
1002 \r
1003--*/\r
1004;\r
1005\r
1006EFI_STATUS\r
1007WaitForEhcNotHalt (\r
1008 IN USB2_HC_DEV *HcDev,\r
1009 IN UINTN Timeout\r
1010 )\r
1011/*++\r
1012\r
1013Routine Description:\r
1014\r
1015 wait for Ehc not halt or timeout\r
1016 \r
1017Arguments:\r
1018\r
1019 HcDev - USB2_HC_DEV \r
1020 Timeout - timeout threshold\r
1021 \r
1022Returns:\r
1023\r
1024 EFI_SUCCESS Success\r
1025 EFI_TIMEOUT Timeout\r
1026 \r
1027--*/\r
1028;\r
1029\r
1030EFI_STATUS\r
1031WaitForEhcDoorbell (\r
1032 IN USB2_HC_DEV *HcDev,\r
1033 IN UINTN Timeout\r
1034 )\r
1035/*++\r
1036\r
1037Routine Description:\r
1038\r
1039 Wait for periodic schedule disable or timeout\r
1040\r
1041Arguments:\r
1042\r
1043 HcDev - USB2_HC_DEV \r
1044 Timeout - timeout threshold\r
1045\r
1046Returns:\r
1047\r
1048 EFI_SUCCESS Success\r
1049 EFI_TIMEOUT Timeout\r
1050 \r
1051--*/\r
1052;\r
1053\r
1054EFI_STATUS\r
1055WaitForAsyncScheduleEnable (\r
1056 IN USB2_HC_DEV *HcDev,\r
1057 IN UINTN Timeout\r
1058 )\r
1059/*++\r
1060\r
1061Routine Description:\r
1062\r
1063 Wait for Ehc asynchronous schedule enable or timeout\r
1064 \r
1065Arguments:\r
1066\r
1067 HcDev - USB2_HC_DEV \r
1068 Timeout - timeout threshold\r
1069 \r
1070Returns:\r
1071\r
1072 EFI_SUCCESS Success\r
1073 EFI_TIMEOUT Timeout\r
1074 \r
1075--*/\r
1076;\r
1077\r
1078EFI_STATUS\r
1079WaitForAsyncScheduleDisable (\r
1080 IN USB2_HC_DEV *HcDev,\r
1081 IN UINTN Timeout\r
1082 )\r
1083/*++\r
1084\r
1085Routine Description:\r
1086\r
1087 Wait for Ehc asynchronous schedule disable or timeout\r
1088 \r
1089Arguments:\r
1090\r
1091 HcDev - USB2_HC_DEV \r
1092 Timeout - timeout threshold\r
1093 \r
1094Returns:\r
1095\r
1096 EFI_SUCCESS Success\r
1097 EFI_TIMEOUT Timeout\r
1098 \r
1099--*/\r
1100;\r
1101\r
1102EFI_STATUS\r
1103WaitForPeriodicScheduleEnable (\r
1104 IN USB2_HC_DEV *HcDev,\r
1105 IN UINTN Timeout\r
1106 )\r
1107/*++\r
1108\r
1109Routine Description:\r
1110\r
1111 Wait for Ehc periodic schedule enable or timeout\r
1112 \r
1113Arguments:\r
1114\r
1115 HcDev - USB2_HC_DEV \r
1116 Timeout - timeout threshold\r
1117 \r
1118Returns:\r
1119\r
1120 EFI_SUCCESS Success\r
1121 EFI_TIMEOUT Timeout\r
1122 \r
1123--*/\r
1124;\r
1125\r
1126EFI_STATUS\r
1127WaitForPeriodicScheduleDisable (\r
1128 IN USB2_HC_DEV *HcDev,\r
1129 IN UINTN Timeout\r
1130 )\r
1131/*++\r
1132\r
1133Routine Description:\r
1134\r
1135 Wait for periodic schedule disable or timeout\r
1136 \r
1137Arguments:\r
1138\r
1139 HcDev - USB2_HC_DEV \r
1140 Timeout - timeout threshold\r
1141 \r
1142Returns:\r
1143\r
1144 EFI_SUCCESS Success\r
1145 EFI_TIMEOUT Timeout\r
1146 \r
1147--*/\r
1148;\r
1149\r
1150EFI_STATUS\r
1151GetCapabilityLen (\r
1152 IN USB2_HC_DEV *HcDev\r
1153 )\r
1154/*++\r
1155\r
1156Routine Description:\r
1157\r
1158 Get the length of capability register\r
1159 \r
1160Arguments:\r
1161\r
1162 HcDev - USB2_HC_DEV \r
1163 \r
1164Returns:\r
1165\r
1166 EFI_SUCCESS Success\r
1167 EFI_DEVICE_ERROR Fail\r
1168 \r
1169--*/\r
1170;\r
1171\r
1172EFI_STATUS\r
1173SetFrameListBaseAddr (\r
1174 IN USB2_HC_DEV *HcDev,\r
1175 IN UINT32 FrameBuffer\r
1176 )\r
1177/*++\r
1178\r
1179Routine Description:\r
1180\r
1181 Set base address of frame list first entry\r
1182 \r
1183Arguments:\r
1184\r
1185 HcDev - USB2_HC_DEV \r
1186 FrameBuffer - base address of first entry of frame list\r
1187 \r
1188Returns:\r
1189\r
1190 EFI_SUCCESS Success\r
1191 EFI_DEVICE_ERROR Fail\r
1192 \r
1193--*/\r
1194;\r
1195\r
1196EFI_STATUS\r
1197SetAsyncListAddr (\r
1198 IN USB2_HC_DEV *HcDev,\r
1199 IN EHCI_QH_ENTITY *QhPtr\r
1200 )\r
1201/*++\r
1202\r
1203Routine Description:\r
1204\r
1205 Set address of first Async schedule Qh\r
1206 \r
1207Arguments:\r
1208\r
1209 HcDev - USB2_HC_DEV \r
1210 QhPtr - A pointer to first Qh in the Async schedule\r
1211 \r
1212Returns:\r
1213\r
1214 EFI_SUCCESS Success\r
1215 EFI_DEVICE_ERROR Fail\r
1216 \r
1217--*/\r
1218;\r
1219\r
1220EFI_STATUS\r
1221SetCtrlDataStructSeg (\r
1222 IN USB2_HC_DEV *HcDev\r
1223 )\r
1224/*++\r
1225\r
1226Routine Description:\r
1227\r
1228 Set address of first Async schedule Qh\r
1229 \r
1230Arguments:\r
1231\r
1232 HcDev - USB2_HC_DEV \r
1233 QhPtr - A pointer to first Qh in the Async schedule\r
1234 \r
1235Returns:\r
1236\r
1237 EFI_SUCCESS Success\r
1238 EFI_DEVICE_ERROR Fail\r
1239 \r
1240--*/\r
1241;\r
1242\r
1243EFI_STATUS\r
1244SetPortRoutingEhc (\r
1245 IN USB2_HC_DEV *HcDev\r
1246 )\r
1247/*++\r
1248\r
1249Routine Description:\r
1250\r
1251 Set Ehc port routing bit\r
1252 \r
1253Arguments:\r
1254\r
1255 HcDev - USB2_HC_DEV \r
1256 \r
1257Returns:\r
1258\r
1259 EFI_SUCCESS Success\r
1260 EFI_DEVICE_ERROR Fail\r
1261 \r
1262--*/\r
1263;\r
1264\r
1265EFI_STATUS\r
1266EnablePeriodicSchedule (\r
1267 IN USB2_HC_DEV *HcDev\r
1268 )\r
1269/*++\r
1270\r
1271Routine Description:\r
1272\r
1273 Enable periodic schedule\r
1274 \r
1275Arguments:\r
1276\r
1277 HcDev - USB2_HC_DEV \r
1278 \r
1279Returns:\r
1280\r
1281 EFI_SUCCESS Success\r
1282 EFI_DEVICE_ERROR Fail\r
1283 \r
1284--*/\r
1285;\r
1286\r
1287EFI_STATUS\r
1288DisablePeriodicSchedule (\r
1289 IN USB2_HC_DEV *HcDev\r
1290 )\r
1291/*++\r
1292\r
1293Routine Description:\r
1294\r
1295 Disable periodic schedule\r
1296 \r
1297Arguments:\r
1298\r
1299 HcDev - USB2_HC_DEV \r
1300 \r
1301Returns:\r
1302\r
1303 EFI_SUCCESS Success\r
1304 EFI_DEVICE_ERROR Fail\r
1305 \r
1306--*/\r
1307;\r
1308\r
1309EFI_STATUS\r
1310EnableAsynchronousSchedule (\r
1311 IN USB2_HC_DEV *HcDev\r
1312 )\r
1313/*++\r
1314\r
1315Routine Description:\r
1316\r
1317 Enable asynchrounous schedule\r
1318 \r
1319Arguments:\r
1320\r
1321 HcDev - USB2_HC_DEV \r
1322 \r
1323Returns:\r\r
1324\r
1325 EFI_SUCCESS Success\r
1326 EFI_DEVICE_ERROR Fail\r
1327 \r
1328--*/\r
1329;\r
1330\r
1331EFI_STATUS\r
1332DisableAsynchronousSchedule (\r
1333 IN USB2_HC_DEV *HcDev\r
1334 )\r
1335/*++\r
1336\r
1337Routine Description:\r
1338\r
1339 Disable asynchrounous schedule\r
1340 \r
1341Arguments:\r
1342\r
1343 HcDev - USB2_HC_DEV \r
1344 \r
1345Returns:\r
1346\r
1347 EFI_SUCCESS Success\r
1348 EFI_DEVICE_ERROR Fail\r
1349 \r
1350--*/\r
1351;\r
1352\r
1353EFI_STATUS\r
1354StartScheduleExecution (\r
1355 IN USB2_HC_DEV *HcDev\r
1356 )\r
1357/*++\r
1358\r
1359Routine Description:\r
1360\r
1361 Start Ehc schedule execution\r
1362 \r
1363Arguments:\r
1364\r
1365 HcDev - USB2_HC_DEV \r
1366 \r
1367Returns:\r
1368\r
1369 EFI_SUCCESS Success\r
1370 EFI_DEVICE_ERROR Fail\r
1371 \r
1372--*/\r
1373;\r
1374\r
1375EFI_STATUS\r
1376ResetEhc (\r
1377 IN USB2_HC_DEV *HcDev\r
1378 )\r
1379/*++\r
1380\r
1381Routine Description:\r
1382\r
1383 Reset Ehc\r
1384 \r
1385Arguments:\r
1386\r
1387 HcDev - USB2_HC_DEV \r
1388 \r
1389Returns:\r
1390\r
1391 EFI_SUCCESS Success\r
1392 EFI_DEVICE_ERROR Fail\r
1393 \r
1394--*/\r
1395;\r
1396\r
1397EFI_STATUS\r
1398ClearEhcAllStatus (\r
1399 IN USB2_HC_DEV *HcDev\r
1400 )\r
1401/*++\r
1402\r
1403Routine Description:\r
1404\r
1405 Clear Ehc all status bits\r
1406 \r
1407Arguments:\r
1408\r
1409 HcDev - USB2_HC_DEV \r
1410 \r
1411Returns:\r
1412\r
1413 EFI_SUCCESS Success\r
1414 EFI_DEVICE_ERROR Fail\r
1415 \r
1416--*/\r
1417;\r
1418\r
1419//\r
1420// EhciSched Functions\r
1421//\r
1422EFI_STATUS\r
1423InitialPeriodicFrameList (\r
1424 IN USB2_HC_DEV *HcDev,\r
1425 IN UINTN Length\r
1426 )\r
1427/*++\r
1428\r
1429Routine Description:\r
1430\r
1431 Initialize Periodic Schedule Frame List\r
1432\r
1433Arguments:\r
1434\r
1435 HcDev - USB2_HC_DEV\r
1436 Length - Frame List Length\r
1437 \r
1438Returns:\r
1439\r
1440 EFI_SUCCESS Success\r
1441 EFI_DEVICE_ERROR Fail\r
1442 \r
1443--*/\r
1444;\r
1445\r
1446VOID\r
1447DeinitialPeriodicFrameList (\r
1448 IN USB2_HC_DEV *HcDev\r
1449 )\r
1450/*++\r
1451\r
1452Routine Description:\r
1453\r
1454 Deinitialize Periodic Schedule Frame List\r
1455\r
1456Arguments:\r
1457\r
1458 HcDev - USB2_HC_DEV\r
1459\r
1460Returns:\r
1461\r
1462 VOID\r
1463 \r
1464--*/\r
1465;\r
1466\r
1467EFI_STATUS\r
1468CreatePollingTimer (\r
1469 IN USB2_HC_DEV *HcDev,\r
1470 IN EFI_EVENT_NOTIFY NotifyFunction\r
1471 )\r
1472/*++\r
1473\r
1474Routine Description:\r
1475\r
1476 Create Async Request Polling Timer\r
1477\r
1478Arguments:\r
1479\r
1480 HcDev - USB2_HC_DEV\r
1481 NotifyFunction - Timer Notify Function\r
1482 \r
1483Returns:\r
1484\r
1485 EFI_SUCCESS Success\r
1486 EFI_DEVICE_ERROR Fail\r
1487 \r
1488--*/\r
1489;\r
1490\r
1491EFI_STATUS\r
1492DestoryPollingTimer (\r
1493 IN USB2_HC_DEV *HcDev\r
1494 )\r
1495/*++\r
1496\r
1497Routine Description:\r
1498\r
1499 Destory Async Request Polling Timer\r
1500\r
1501Arguments:\r
1502\r
1503 HcDev - USB2_HC_DEV\r
1504 \r
1505Returns:\r
1506\r
1507 EFI_SUCCESS Success\r
1508 EFI_DEVICE_ERROR Fail\r
1509 \r
1510--*/\r
1511;\r
1512\r
1513EFI_STATUS\r
1514StartPollingTimer (\r
1515 IN USB2_HC_DEV *HcDev\r
1516 )\r
1517/*++\r
1518\r
1519Routine Description:\r
1520\r
1521 Start Async Request Polling Timer\r
1522\r
1523Arguments:\r
1524\r
1525 HcDev - USB2_HC_DEV\r
1526 \r
1527Returns:\r
1528\r
1529 EFI_SUCCESS Success\r
1530 EFI_DEVICE_ERROR Fail\r
1531 \r
1532--*/\r
1533;\r
1534\r
1535EFI_STATUS\r
1536StopPollingTimer (\r
1537 IN USB2_HC_DEV *HcDev\r
1538 )\r
1539/*++\r
1540\r
1541Routine Description:\r
1542\r
1543 Stop Async Request Polling Timer\r
1544\r
1545Arguments:\r
1546\r
1547 HcDev - USB2_HC_DEV\r
1548 \r
1549Returns:\r
1550\r
1551 EFI_SUCCESS Success\r
1552 EFI_DEVICE_ERROR Fail\r
1553 \r
1554--*/\r
1555;\r
1556\r
1557EFI_STATUS\r
1558CreateQh (\r
1559 IN USB2_HC_DEV *HcDev,\r
1560 IN UINT8 DeviceAddr,\r
1561 IN UINT8 Endpoint,\r
1562 IN UINT8 DeviceSpeed,\r
1563 IN UINTN MaxPacketLen,\r
1564 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1565 )\r
1566/*++\r
1567\r
1568Routine Description:\r
1569\r
1570 Create Qh Structure and Pre-Initialize\r
1571\r
1572Arguments:\r
1573\r
1574 HcDev - USB2_HC_DEV \r
1575 DeviceAddr - Address of Device\r
1576 Endpoint - Endpoint Number\r
1577 DeviceSpeed - Device Speed\r
1578 MaxPacketLen - Max Length of one Packet\r
1579 QhPtrPtr - A pointer of pointer to Qh for return\r
1580 \r
1581Returns:\r
1582\r
1583 EFI_SUCCESS Success\r
1584 EFI_DEVICE_ERROR Fail\r
1585 \r
1586--*/\r
1587;\r
1588\r
1589EFI_STATUS\r
1590CreateControlQh (\r
1591 IN USB2_HC_DEV *HcDev,\r
1592 IN UINT8 DeviceAddr,\r
1593 IN UINT8 DeviceSpeed,\r
1594 IN UINTN MaxPacketLen,\r
1595 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1596 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1597 )\r
1598/*++\r
1599\r
1600Routine Description:\r
1601\r
1602 Create Qh for Control Transfer\r
1603\r
1604Arguments:\r
1605\r
1606 HcDev - USB2_HC_DEV \r
1607 DeviceAddr - Address of Device\r
1608 DeviceSpeed - Device Speed\r
1609 MaxPacketLen - Max Length of one Packet\r
1610 Translator - Translator Transaction for SplitX\r
1611 QhPtrPtr - A pointer of pointer to Qh for return\r
1612 \r
1613Returns:\r
1614\r
1615 EFI_SUCCESS Success\r
1616 EFI_DEVICE_ERROR Fail\r
1617 \r
1618--*/\r
1619;\r
1620\r
1621EFI_STATUS\r
1622CreateBulkQh (\r
1623 IN USB2_HC_DEV *HcDev,\r
1624 IN UINT8 DeviceAddr,\r
1625 IN UINT8 EndPointAddr,\r
1626 IN UINT8 DeviceSpeed,\r
1627 IN UINT8 DataToggle,\r
1628 IN UINTN MaxPacketLen,\r
1629 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1630 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1631 )\r
1632/*++\r
1633\r
1634Routine Description:\r
1635\r
1636 Create Qh for Bulk Transfer\r
1637\r
1638Arguments:\r
1639\r
1640 HcDev - USB2_HC_DEV \r
1641 DeviceAddr - Address of Device\r
1642 EndPointAddr - Address of Endpoint\r
1643 DeviceSpeed - Device Speed\r
1644 MaxPacketLen - Max Length of one Packet\r
1645 Translator - Translator Transaction for SplitX\r
1646 QhPtrPtr - A pointer of pointer to Qh for return\r
1647 \r
1648Returns:\r
1649\r
1650 EFI_SUCCESS Success\r
1651 EFI_DEVICE_ERROR Fail\r
1652 \r
1653--*/\r
1654;\r
1655\r
1656EFI_STATUS\r
1657CreateInterruptQh (\r
1658 IN USB2_HC_DEV *HcDev,\r
1659 IN UINT8 DeviceAddr,\r
1660 IN UINT8 EndPointAddr,\r
1661 IN UINT8 DeviceSpeed,\r
1662 IN UINT8 DataToggle,\r
1663 IN UINTN MaxPacketLen,\r
1664 IN UINTN Interval,\r
1665 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1666 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1667 )\r
1668/*++\r
1669\r
1670Routine Description:\r
1671\r
1672 Create Qh for Control Transfer\r
1673\r
1674Arguments:\r
1675\r
1676 HcDev - USB2_HC_DEV \r
1677 DeviceAddr - Address of Device\r
1678 EndPointAddr - Address of Endpoint\r
1679 DeviceSpeed - Device Speed\r
1680 MaxPacketLen - Max Length of one Packet\r
1681 Interval - value of interval\r
1682 Translator - Translator Transaction for SplitX\r
1683 QhPtrPtr - A pointer of pointer to Qh for return\r
1684 \r
1685Returns:\r
1686\r
1687 EFI_SUCCESS Success\r
1688 EFI_DEVICE_ERROR Fail\r
1689 \r
1690--*/\r
1691;\r
1692\r
1693VOID\r
1694DestoryQh (\r
1695 IN USB2_HC_DEV *HcDev,\r
1696 IN EHCI_QH_ENTITY *QhPtr\r
1697 )\r
1698/*++\r
1699\r
1700Routine Description:\r
1701\r
1702 Destory Qh Structure \r
1703 \r
1704Arguments:\r
1705\r
1706 HcDev - USB2_HC_DEV \r
1707 QhPtr - A pointer to Qh\r
1708 \r
1709Returns:\r
1710\r
1711 VOID\r
1712 \r
1713--*/\r
1714;\r
1715\r
1716EFI_STATUS\r
1717CreateQtd (\r
1718 IN USB2_HC_DEV *HcDev,\r
1719 IN UINT8 *DataPtr,\r
1720 IN UINTN DataLen,\r
1721 IN UINT8 PktId,\r
1722 IN UINT8 Toggle,\r
1723 IN UINT8 QtdStatus,\r
1724 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1725 )\r
1726/*++\r
1727\r
1728Routine Description:\r
1729\r
1730 Create Qtd Structure and Pre-Initialize it\r
1731\r
1732Arguments:\r
1733\r
1734 HcDev - USB2_HC_DEV \r
1735 DataPtr - A pointer to user data buffer to transfer\r
1736 DataLen - Length of user data to transfer\r
1737 PktId - Packet Identification of this Qtd\r
1738 Toggle - Data Toggle of this Qtd\r
1739 QtdStatus - Default value of status of this Qtd\r
1740 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1741 \r
1742Returns:\r
1743\r
1744 EFI_SUCCESS Success\r
1745 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1746 \r
1747--*/\r
1748;\r
1749\r
1750EFI_STATUS\r
1751CreateSetupQtd (\r
1752 IN USB2_HC_DEV *HcDev,\r
1753 IN UINT8 *DevReqPtr,\r
1754 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1755 )\r
1756/*++\r
1757\r
1758Routine Description:\r
1759\r
1760 Create Qtd Structure for Setup \r
1761\r
1762Arguments:\r
1763\r
1764 HcDev - USB2_HC_DEV \r
1765 DevReqPtr - A pointer to Device Request Data\r
1766 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1767 \r
1768Returns:\r
1769\r
1770 EFI_SUCCESS Success\r
1771 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1772 \r
1773--*/\r
1774;\r
1775\r
1776EFI_STATUS\r
1777CreateDataQtd (\r
1778 IN USB2_HC_DEV *HcDev,\r
1779 IN UINT8 *DataPtr,\r
1780 IN UINTN DataLen,\r
1781 IN UINT8 PktId,\r
1782 IN UINT8 Toggle,\r
1783 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1784 )\r
1785/*++\r
1786\r
1787Routine Description:\r
1788\r
1789 Create Qtd Structure for data \r
1790\r
1791Arguments:\r
1792\r
1793 HcDev - USB2_HC_DEV \r
1794 DataPtr - A pointer to user data buffer to transfer\r
1795 DataLen - Length of user data to transfer\r
1796 PktId - Packet Identification of this Qtd\r
1797 Toggle - Data Toggle of this Qtd\r
1798 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1799 \r
1800Returns:\r
1801\r
1802 EFI_SUCCESS Success\r
1803 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1804 \r
1805--*/\r
1806;\r
1807\r
1808EFI_STATUS\r
1809CreateStatusQtd (\r
1810 IN USB2_HC_DEV *HcDev,\r
1811 IN UINT8 PktId,\r
1812 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1813 )\r
1814/*++\r
1815\r
1816Routine Description:\r
1817\r
1818 Create Qtd Structure for status \r
1819\r
1820Arguments:\r
1821\r
1822 HcDev - USB2_HC_DEV \r
1823 PktId - Packet Identification of this Qtd\r
1824 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1825 \r
1826Returns:\r
1827\r
1828 EFI_SUCCESS Success\r
1829 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1830 \r
1831--*/\r
1832;\r
1833\r
1834EFI_STATUS\r
1835CreateAltQtd (\r
1836 IN USB2_HC_DEV *HcDev,\r
1837 IN UINT8 PktId,\r
1838 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1839 )\r
1840/*++\r
1841\r
1842Routine Description:\r
1843\r
1844 Create Qtd Structure for Alternative \r
1845\r
1846Arguments:\r
1847\r
1848 HcDev - USB2_HC_DEV \r
1849 PktId - Packet Identification of this Qtd\r
1850 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1851 \r
1852Returns:\r
1853\r
1854 EFI_SUCCESS Success\r
1855 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1856 \r
1857--*/\r
1858;\r
1859\r
1860EFI_STATUS\r
1861CreateControlQtds (\r
1862 IN USB2_HC_DEV *HcDev,\r
1863 IN UINT8 DataPktId,\r
1864 IN UINT8 *RequestCursor,\r
1865 IN UINT8 *DataCursor,\r
1866 IN UINTN DataLen,\r
1867 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1868 OUT EHCI_QTD_ENTITY **ControlQtdsHead\r
1869 )\r
1870/*++\r
1871\r
1872Routine Description:\r
1873\r
1874 Create Qtds list for Control Transfer \r
1875\r
1876Arguments:\r
1877\r
1878 HcDev - USB2_HC_DEV \r
1879 DataPktId - Packet Identification of Data Qtds\r
1880 RequestCursor - A pointer to request structure buffer to transfer\r
1881 DataCursor - A pointer to user data buffer to transfer\r
1882 DataLen - Length of user data to transfer\r
1883 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1884 \r
1885Returns:\r
1886\r
1887 EFI_SUCCESS Success\r
1888 EFI_DEVICE_ERROR Fail\r
1889 \r
1890--*/\r
1891;\r
1892\r
1893EFI_STATUS\r
1894CreateBulkOrInterruptQtds (\r
1895 IN USB2_HC_DEV *HcDev,\r
1896 IN UINT8 PktId,\r
1897 IN UINT8 *DataCursor,\r
1898 IN UINTN DataLen,\r
1899 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1900 OUT EHCI_QTD_ENTITY **QtdsHead\r
1901 )\r
1902/*++\r
1903\r
1904Routine Description:\r
1905\r
1906 Create Qtds list for Bulk or Interrupt Transfer \r
1907\r
1908Arguments:\r
1909\r
1910 HcDev - USB2_HC_DEV \r
1911 PktId - Packet Identification of Qtds\r
1912 DataCursor - A pointer to user data buffer to transfer\r
1913 DataLen - Length of user data to transfer\r
1914 DataToggle - Data Toggle to start\r
1915 Translator - Translator Transaction for SplitX\r
1916 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1917 \r
1918Returns:\r
1919\r
1920 EFI_SUCCESS Success\r
1921 EFI_DEVICE_ERROR Fail\r
1922 \r
1923--*/\r
1924;\r
1925\r
1926VOID\r
1927DestoryQtds (\r
1928 IN USB2_HC_DEV *HcDev,\r
1929 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
1930 )\r
1931/*++\r
1932\r
1933Routine Description:\r
1934\r
1935 Destory all Qtds in the list\r
1936\r
1937Arguments:\r
1938\r
1939 HcDev - USB2_HC_DEV \r
1940 FirstQtdPtr - A pointer to first Qtd in the list \r
1941 \r
1942Returns:\r
1943\r
1944 VOID\r
1945\r
1946--*/\r
1947;\r
1948\r
1949VOID\r
1950LinkQtdToQtd (\r
1951 IN EHCI_QTD_ENTITY *PreQtdPtr,\r
1952 IN EHCI_QTD_ENTITY *QtdPtr\r
1953 )\r
1954/*++\r
1955\r
1956Routine Description:\r
1957\r
1958 Link Qtds together\r
1959 \r
1960Arguments:\r
1961\r
1962 PreQtdPtr - A pointer to pre Qtd\r
1963 QtdPtr - A pointer to next Qtd\r
1964 \r
1965Returns:\r
1966\r
1967 VOID\r
1968\r
1969--*/\r
1970;\r
1971\r
1972VOID\r
1973LinkQtdsToAltQtd (\r
1974 IN EHCI_QTD_ENTITY *FirstQtdPtr,\r
1975 IN EHCI_QTD_ENTITY *AltQtdPtr\r
1976 )\r
1977/*++\r
1978\r
1979Routine Description:\r
1980\r
1981 Link AlterQtds together\r
1982 \r
1983Arguments:\r
1984\r
1985 FirstQtdPtr - A pointer to first Qtd in the list\r
1986 AltQtdPtr - A pointer to alternative Qtd\r
1987 \r
1988Returns:\r
1989 VOID\r
1990\r
1991--*/\r
1992;\r
1993\r
1994VOID\r
1995LinkQtdToQh (\r
1996 IN EHCI_QH_ENTITY *QhPtr,\r
1997 IN EHCI_QTD_ENTITY *QtdEntryPtr\r
1998 )\r
1999/*++\r
2000\r
2001Routine Description:\r
2002\r
2003 Link Qtds list to Qh\r
2004 \r
2005Arguments:\r
2006\r
2007 QhPtr - A pointer to Qh\r
2008 QtdPtr - A pointer to first Qtd in the list\r
2009 \r
2010Returns:\r
2011\r
2012 VOID\r
2013\r
2014--*/\r
2015;\r
2016\r
2017EFI_STATUS\r
2018LinkQhToAsyncList (\r
2019 IN USB2_HC_DEV *HcDev,\r
2020 IN EHCI_QH_ENTITY *QhPtr\r
2021 )\r
2022/*++\r
2023\r
2024Routine Description:\r
2025\r
2026 Link Qh to Async Schedule List\r
2027 \r
2028Arguments:\r
2029\r
2030 HcDev - USB2_HC_DEV \r
2031 QhPtr - A pointer to Qh\r
2032 \r
2033Returns:\r
2034\r
2035 EFI_SUCCESS Success\r
2036 EFI_DEVICE_ERROR Fail\r
2037 \r
2038--*/\r
2039;\r
2040\r
2041EFI_STATUS\r
2042UnlinkQhFromAsyncList (\r
2043 IN USB2_HC_DEV *HcDev,\r
2044 IN EHCI_QH_ENTITY *QhPtr\r
2045 )\r
2046/*++\r
2047\r
2048Routine Description:\r
2049\r
2050 Unlink Qh from Async Schedule List\r
2051 \r
2052Arguments:\r
2053\r
2054 HcDev - USB2_HC_DEV \r
2055 QhPtr - A pointer to Qh\r
2056 \r
2057Returns:\r
2058\r
2059 EFI_SUCCESS Success\r
2060 EFI_DEVICE_ERROR Fail\r
2061 \r
2062--*/\r
2063;\r
2064\r
2065VOID\r
2066LinkQhToPeriodicList (\r
2067 IN USB2_HC_DEV *HcDev,\r
2068 IN EHCI_QH_ENTITY *QhPtr\r
2069 )\r
2070/*++\r
2071\r
2072Routine Description:\r
2073\r
2074 Link Qh to Periodic Schedule List\r
2075 \r
2076Arguments:\r
2077\r
2078 HcDev - USB2_HC_DEV \r
2079 QhPtr - A pointer to Qh\r
2080 \r
2081Returns:\r
2082\r
2083 VOID\r
2084\r
2085--*/\r
2086;\r
2087\r
2088VOID\r
2089UnlinkQhFromPeriodicList (\r
2090 IN USB2_HC_DEV *HcDev,\r
2091 IN EHCI_QH_ENTITY *QhPtr,\r
2092 IN UINTN Interval\r
2093 )\r
2094/*++\r
2095\r
2096Routine Description:\r
2097\r
2098 Unlink Qh from Periodic Schedule List\r
2099 \r
2100Arguments:\r
2101\r
2102 HcDev - USB2_HC_DEV \r
2103 QhPtr - A pointer to Qh\r
2104 Interval - Interval of this periodic transfer\r
2105 \r
2106Returns:\r
2107\r
2108 VOID\r
2109 \r
2110--*/\r
2111;\r
2112\r
2113VOID\r
2114LinkToAsyncReqeust (\r
2115 IN USB2_HC_DEV *HcDev,\r
2116 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2117 )\r
2118/*++\r
2119\r
2120Routine Description:\r
2121\r
2122 Llink AsyncRequest Entry to Async Request List\r
2123 \r
2124Arguments:\r
2125\r
2126 HcDev - USB2_HC_DEV \r
2127 AsyncRequestPtr - A pointer to Async Request Entry\r
2128 \r
2129Returns:\r
2130\r
2131 VOID\r
2132 \r
2133--*/\r
2134;\r
2135\r
2136VOID\r
2137UnlinkFromAsyncReqeust (\r
2138 IN USB2_HC_DEV *HcDev,\r
2139 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2140 )\r
2141/*++\r
2142\r
2143Routine Description:\r
2144\r
2145 Unlink AsyncRequest Entry from Async Request List\r
2146 \r
2147Arguments:\r
2148\r
2149 HcDev - USB2_HC_DEV \r
2150 AsyncRequestPtr - A pointer to Async Request Entry\r
2151 \r
2152Returns:\r
2153\r
2154 VOID\r
2155 \r
2156--*/\r
2157;\r
2158\r
2159UINTN\r
2160GetNumberOfQtd (\r
2161 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2162 )\r
2163/*++\r
2164\r
2165Routine Description:\r
2166\r
2167 Number of Qtds in the list\r
2168 \r
2169Arguments:\r
2170\r
2171 FirstQtdPtr - A pointer to first Qtd in the list\r
2172 \r
2173Returns:\r
2174\r
2175 Number of Qtds in the list\r
2176\r
2177--*/\r
2178;\r
2179\r
2180UINTN\r
2181GetNumberOfTransaction (\r
2182 IN UINTN SizeOfData,\r
2183 IN UINTN SizeOfTransaction\r
2184 )\r
2185/*++\r
2186\r
2187Routine Description:\r
2188\r
2189 Number of Transactions in one Qtd\r
2190 \r
2191Arguments:\r
2192\r
2193 SizeOfData - Size of one Qtd\r
2194 SizeOfTransaction - Size of one Transaction\r
2195 \r
2196Returns:\r
2197\r
2198 Number of Transactions in this Qtd\r
2199\r
2200--*/\r
2201;\r
2202\r
2203UINTN\r
2204GetCapacityOfQtd (\r
2205 IN UINT8 *BufferCursor\r
2206 )\r
2207/*++\r
2208\r
2209Routine Description:\r
2210\r
2211 Get Capacity of Qtd\r
2212 \r
2213Arguments:\r
2214\r
2215 BufferCursor - BufferCursor of the Qtd\r
2216 \r
2217Returns:\r
2218\r
2219 Capacity of Qtd\r
2220\r
2221--*/\r
2222;\r
2223\r
2224UINTN\r
2225GetApproxiOfInterval (\r
2226 IN UINTN Interval\r
2227 )\r
2228/*++\r
2229\r
2230Routine Description:\r
2231\r
2232 Get the approximate value in the 2 index sequence\r
2233 \r
2234Arguments:\r
2235\r
2236 Interval - the value of interval\r
2237 \r
2238Returns:\r
2239\r
2240 approximate value of interval in the 2 index sequence\r
2241 \r
2242--*/\r
2243;\r
2244\r
2245EHCI_QTD_HW *\r
2246GetQtdNextPointer (\r
2247 IN EHCI_QTD_HW *HwQtdPtr\r
2248 )\r
2249/*++\r
2250\r
2251Routine Description:\r
2252\r
2253 Get Qtd next pointer field\r
2254 \r
2255Arguments:\r
2256\r
2257 HwQtdPtr - A pointer to hardware Qtd structure\r
2258 \r
2259Returns:\r
2260\r
2261 A pointer to next hardware Qtd structure\r
2262 \r
2263--*/\r
2264;\r
2265\r
2266BOOLEAN\r
2267IsQtdStatusActive (\r
2268 IN EHCI_QTD_HW *HwQtdPtr\r
2269 )\r
2270/*++\r
2271\r
2272Routine Description:\r
2273\r
2274 Whether Qtd status is active or not\r
2275 \r
2276Arguments:\r
2277\r
2278 HwQtdPtr - A pointer to hardware Qtd structure\r
2279 \r
2280Returns:\r
2281\r
2282 TRUE Active\r
2283 FALSE Inactive\r
2284 \r
2285--*/\r
2286;\r
2287\r
2288BOOLEAN\r
2289IsQtdStatusHalted (\r
2290 IN EHCI_QTD_HW *HwQtdPtr\r
2291 )\r
2292/*++\r
2293\r
2294Routine Description:\r
2295\r
2296 Whether Qtd status is halted or not\r
2297 \r
2298Arguments:\r
2299\r
2300 HwQtdPtr - A pointer to hardware Qtd structure\r
2301 \r
2302Returns:\r\r
2303\r
2304 TRUE Halted\r
2305 FALSE Not halted\r
2306 \r
2307--*/\r
2308;\r
2309\r
2310BOOLEAN\r
2311IsQtdStatusBufferError (\r
2312 IN EHCI_QTD_HW *HwQtdPtr\r
2313 )\r
2314/*++\r
2315\r
2316Routine Description:\r
2317\r
2318 Whether Qtd status is buffer error or not\r
2319 \r
2320Arguments:\r
2321\r
2322 HwQtdPtr - A pointer to hardware Qtd structure\r
2323 \r
2324Returns:\r
2325\r
2326 TRUE Buffer error\r
2327 FALSE No buffer error\r
2328 \r
2329--*/\r
2330;\r
2331\r
2332BOOLEAN\r
2333IsQtdStatusBabbleError (\r
2334 IN EHCI_QTD_HW *HwQtdPtr\r
2335 )\r
2336/*++\r
2337\r
2338Routine Description:\r
2339\r
2340 Whether Qtd status is babble error or not\r
2341 \r
2342Arguments:\r
2343\r
2344 HwQtdPtr - A pointer to hardware Qtd structure\r
2345 \r
2346Returns:\r
2347\r
2348 TRUE Babble error\r
2349 FALSE No babble error\r
2350 \r
2351--*/\r
2352;\r
2353\r
2354BOOLEAN\r
2355IsQtdStatusTransactionError (\r
2356 IN EHCI_QTD_HW *HwQtdPtr\r
2357 )\r
2358/*++\r
2359\r
2360Routine Description:\r
2361\r
2362 Whether Qtd status is transaction error or not\r
2363 \r
2364Arguments:\r
2365\r
2366 HwQtdPtr - A pointer to hardware Qtd structure\r
2367 \r
2368Returns:\r
2369\r
2370 TRUE Transaction error\r
2371 FALSE No transaction error\r
2372 \r
2373--*/\r
2374;\r
2375\r
2376BOOLEAN\r
2377IsDataInTransfer (\r
2378 IN UINT8 EndPointAddress\r
2379 )\r
2380/*++\r
2381\r
2382Routine Description:\r
2383\r
2384 Whether is a DataIn direction transfer\r
2385 \r
2386Arguments:\r
2387\r
2388 EndPointAddress - address of the endpoint \r
2389 \r
2390Returns:\r
2391\r
2392 TRUE DataIn\r
2393 FALSE DataOut\r
2394 \r
2395--*/\r
2396;\r
2397\r
2398EFI_STATUS\r
2399MapDataBuffer (\r
2400 IN USB2_HC_DEV *HcDev,\r
2401 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
2402 IN OUT VOID *Data,\r
2403 IN OUT UINTN *DataLength,\r
2404 OUT UINT8 *PktId,\r
2405 OUT UINT8 **DataCursor,\r
2406 OUT VOID **DataMap\r
2407 )\r
2408/*++\r
2409\r
2410Routine Description:\r
2411\r
2412 Map address of user data buffer\r
2413 \r
2414Arguments:\r
2415\r
2416 HcDev - USB2_HC_DEV \r
2417 TransferDirection - direction of transfer\r
2418 Data - A pointer to user data buffer \r
2419 DataLength - length of user data\r
2420 PktId - Packte Identificaion\r
2421 DataCursor - mapped address to return\r
2422 DataMap - identificaion of this mapping to return\r
2423 \r
2424Returns:\r
2425\r
2426 EFI_SUCCESS Success\r
2427 EFI_DEVICE_ERROR Fail\r
2428 \r
2429--*/\r
2430;\r
2431\r
2432EFI_STATUS\r
2433MapRequestBuffer (\r
2434 IN USB2_HC_DEV *HcDev,\r
2435 IN OUT VOID *Request,\r
2436 OUT UINT8 **RequestCursor,\r
2437 OUT VOID **RequestMap\r
2438 )\r
2439/*++\r
2440\r
2441Routine Description:\r
2442\r
2443 Map address of request structure buffer\r
2444 \r
2445Arguments:\r
2446\r
2447 HcDev - USB2_HC_DEV \r
2448 Request - A pointer to request structure\r
2449 RequestCursor - Mapped address of request structure to return\r
2450 RequestMap - Identificaion of this mapping to return\r
2451 \r
2452Returns:\r
2453\r
2454 EFI_SUCCESS Success\r
2455 EFI_DEVICE_ERROR Fail\r
2456 \r
2457--*/\r
2458;\r
2459\r
2460VOID\r
2461SetQtdBufferPointer (\r
2462 IN EHCI_QTD_HW *QtdHwPtr,\r
2463 IN VOID *DataPtr,\r
2464 IN UINTN DataLen\r
2465 )\r
2466/*++\r
2467\r
2468Routine Description:\r
2469\r
2470 Set data buffer pointers in Qtd\r
2471\r
2472Arguments:\r
2473\r
2474 QtdHwPtr - A pointer to Qtd hardware structure \r
2475 DataPtr - A pointer to user data buffer\r
2476 DataLen - Length of the user data buffer\r
2477 \r
2478Returns:\r
2479\r
2480 VOID\r
2481\r
2482--*/\r
2483;\r
2484\r
2485EHCI_QTD_HW *\r
2486GetQtdAlternateNextPointer (\r
2487 IN EHCI_QTD_HW *HwQtdPtr\r
2488 )\r
2489/*++\r
2490\r
2491Routine Description:\r
2492\r
2493 Get Qtd alternate next pointer field\r
2494 \r
2495Arguments:\r
2496\r
2497 HwQtdPtr - A pointer to hardware Qtd structure\r
2498 \r
2499Returns:\r
2500\r
2501 A pointer to hardware alternate Qtd\r
2502 \r
2503--*/\r
2504;\r
2505\r
2506VOID\r
2507ZeroOutQhOverlay (\r
2508 IN EHCI_QH_ENTITY *QhPtr\r
2509 )\r
2510/*++\r
2511\r
2512Routine Description:\r
2513\r
2514 Zero out the fields in Qh structure\r
2515 \r
2516Arguments:\r
2517\r
2518 QhPtr - A pointer to Qh structure\r
2519 \r
2520Returns:\r
2521\r
2522 VOID\r
2523 \r
2524--*/\r
2525;\r
2526\r
2527VOID\r
2528UpdateAsyncRequestTransfer (\r
2529 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,\r
2530 IN UINT32 TransferResult,\r
2531 IN UINTN ErrTDPos\r
2532 )\r
2533/*++\r
2534\r
2535Routine Description:\r
2536\r
2537 Update asynchronous request transfer\r
2538 \r
2539Arguments:\r
2540\r
2541 AsyncRequestPtr - A pointer to async request \r
2542 TransferResult - transfer result \r
2543 ErrQtdPos - postion of error Qtd\r
2544 \r
2545Returns:\r
2546\r
2547 VOID\r
2548 \r
2549--*/\r
2550;\r
2551\r
2552\r
2553EFI_STATUS\r
2554DeleteAsyncRequestTransfer (\r
2555 IN USB2_HC_DEV *HcDev,\r
2556 IN UINT8 DeviceAddress,\r
2557 IN UINT8 EndPointAddress,\r
2558 OUT UINT8 *DataToggle\r
2559 )\r
2560/*++\r
2561\r
2562Routine Description:\r
2563\r
2564 Delete all asynchronous request transfer\r
2565 \r
2566Arguments:\r
2567\r
2568 HcDev - USB2_HC_DEV \r
2569 DeviceAddress - address of usb device\r
2570 EndPointAddress - address of endpoint\r
2571 DataToggle - stored data toggle\r
2572 \r
2573Returns:\r
2574\r
2575 EFI_SUCCESS Success\r
2576 EFI_DEVICE_ERROR Fail\r
2577\r
2578--*/\r
2579;\r
2580\r
2581VOID\r
2582CleanUpAllAsyncRequestTransfer (\r
2583 IN USB2_HC_DEV *HcDev\r
2584 )\r
2585/*++\r
2586\r
2587Routine Description:\r
2588\r
2589 Clean up all asynchronous request transfer\r
2590 \r
2591Arguments:\r
2592\r
2593 HcDev - USB2_HC_DEV \r
2594 \r
2595Returns:\r
2596 VOID\r
2597 \r
2598--*/\r
2599;\r
2600\r
2601EFI_STATUS\r
2602ExecuteTransfer (\r
2603 IN USB2_HC_DEV *HcDev,\r
2604 IN BOOLEAN IsControl,\r
2605 IN EHCI_QH_ENTITY *QhPtr,\r
2606 IN OUT UINTN *ActualLen,\r
2607 OUT UINT8 *DataToggle,\r
2608 IN UINTN TimeOut,\r
2609 OUT UINT32 *TransferResult\r
2610 )\r
2611/*++\r
2612\r
2613Routine Description:\r
2614\r
2615 Execute Bulk or SyncInterrupt Transfer\r
2616\r
2617Arguments:\r
2618\r
2619 HcDev - USB2_HC_DEV\r
2620 IsControl - Is control transfer or not\r
2621 QhPtr - A pointer to Qh\r
2622 ActualLen - Actual transfered Len \r
2623 DataToggle - Data Toggle\r
2624 TimeOut - TimeOut threshold\r
2625 TransferResult - Transfer result\r
2626 \r
2627Returns:\r
2628\r
2629 EFI_SUCCESS Sucess\r
2630 EFI_DEVICE_ERROR Error\r
2631 \r
2632--*/\r
2633;\r
2634\r
2635BOOLEAN\r
2636CheckQtdsTransferResult (\r
2637 IN BOOLEAN IsControl,\r
2638 IN EHCI_QH_ENTITY *QhPtr,\r
2639 OUT UINT32 *Result,\r
2640 OUT UINTN *ErrQtdPos,\r
2641 OUT UINTN *ActualLen\r
2642 )\r
2643/*++\r
2644\r
2645Routine Description:\r
2646\r
2647 Check transfer result of Qtds\r
2648\r
2649Arguments:\r
2650\r
2651 IsControl - Is control transfer or not\r
2652 QhPtr - A pointer to Qh\r
2653 Result - Transfer result\r
2654 ErrQtdPos - Error TD Position\r
2655 ActualLen - Actual Transfer Size\r
2656\r
2657Returns:\r
2658\r
2659 TRUE Qtds finished\r
2660 FALSE Not finish\r
2661 \r
2662--*/\r
2663;\r
2664\r
2665EFI_STATUS\r
2666AsyncRequestMoniter (\r
2667 IN EFI_EVENT Event,\r
2668 IN VOID *Context\r
2669 )\r
2670/*++\r
2671\r
2672Routine Description:\r
2673 \r
2674 Interrupt transfer periodic check handler\r
2675 \r
2676Arguments:\r
2677\r
2678 Event - Interrupt event\r
2679 Context - Pointer to USB2_HC_DEV\r
2680 \r
2681Returns:\r
2682 \r
2683 EFI_SUCCESS Success\r
2684 EFI_DEVICE_ERROR Fail\r
2685 \r
2686--*/\r
2687;\r
2688\r
2689#endif\r
EFI Development Kit II mirror for PVE