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[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
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562d2849 1/*++\r
2\r
3Copyright (c) 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 Ehci.h\r
15 \r
16Abstract: \r
17 \r
18\r
19Revision History\r
20--*/\r
21\r
22#ifndef _EHCI_H\r
23#define _EHCI_H\r
24\r
25//\r
26// Universal Host Controller Interface data structures and defines\r
27//\r
28#include <IndustryStandard/pci22.h>\r
29\r
562d2849 30extern UINTN gEHCDebugLevel;\r
31extern UINTN gEHCErrorLevel;\r
562d2849 32\r
33#define STALL_1_MACRO_SECOND 1\r
34#define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND\r
35#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r
36\r
37#define SETUP_PACKET_PID_CODE 0x02\r
38#define INPUT_PACKET_PID_CODE 0x01\r
39#define OUTPUT_PACKET_PID_CODE 0x0\r
40\r
41#define ITD_SELECT_TYPE 0x0\r
42#define QH_SELECT_TYPE 0x01\r
43#define SITD_SELECT_TYPE 0x02\r
44#define FSTN_SELECT_TYPE 0x03\r
45\r
46#define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND\r
47#define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND\r
48#define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND\r
49#define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND\r
50#define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND\r
51#define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND\r
52\r
53#define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */\r
54\r
55#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1\r
56\r
57#define EHCI_MIN_PACKET_SIZE 8\r
58#define EHCI_MAX_PACKET_SIZE 1024\r
59#define EHCI_MAX_FRAME_LIST_LENGTH 1024\r
60#define EHCI_BLOCK_SIZE_WITH_TT 64\r
61#define EHCI_BLOCK_SIZE 512\r
62#define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)\r
63\r
64#define NAK_COUNT_RELOAD 3\r
65#define QTD_ERROR_COUNTER 1\r
66#define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1\r
67\r
68#define QTD_STATUS_ACTIVE 0x80\r
69#define QTD_STATUS_HALTED 0x40\r
70#define QTD_STATUS_BUFFER_ERR 0x20\r
71#define QTD_STATUS_BABBLE_ERR 0x10\r
72#define QTD_STATUS_TRANSACTION_ERR 0x08\r
73#define QTD_STATUS_DO_STOP_SPLIT 0x02\r
74#define QTD_STATUS_DO_START_SPLIT 0\r
75#define QTD_STATUS_DO_PING 0x01\r
76#define QTD_STATUS_DO_OUT 0\r
77\r
78#define DATA0 0\r
79#define DATA1 1\r
80\r
81#define MICRO_FRAME_0_CHANNEL 0x01\r
82#define MICRO_FRAME_1_CHANNEL 0x02\r
83#define MICRO_FRAME_2_CHANNEL 0x04\r
84#define MICRO_FRAME_3_CHANNEL 0x08\r
85#define MICRO_FRAME_4_CHANNEL 0x10\r
86#define MICRO_FRAME_5_CHANNEL 0x20\r
87#define MICRO_FRAME_6_CHANNEL 0x40\r
88#define MICRO_FRAME_7_CHANNEL 0x80\r
89\r
90#define CONTROL_TRANSFER 0x01\r
91#define BULK_TRANSFER 0x02\r
92#define SYNC_INTERRUPT_TRANSFER 0x04\r
93#define ASYNC_INTERRUPT_TRANSFER 0x08\r
94#define SYNC_ISOCHRONOUS_TRANSFER 0x10\r
95#define ASYNC_ISOCHRONOUS_TRANSFER 0x20\r
96\r
97\r
98//\r
99// Enhanced Host Controller Registers definitions\r
100//\r
101extern UINT32 mUsbCapabilityLen;\r
102extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
103extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
104\r
105#define USBCMD 0x0 /* Command Register Offset 00-03h */\r
106#define USBCMD_RS 0x01 /* Run / Stop */\r
107#define USBCMD_HCRESET 0x02 /* Host controller reset */\r
108#define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */\r
109#define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */\r
110#define USBCMD_PSE 0x10 /* Periodic schedule enable */\r
111#define USBCMD_ASE 0x20 /* Asynchronous schedule enable */\r
112#define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */\r
113\r
114#define USBSTS 0x04 /* Statue Register Offset 04-07h */\r
115#define USBSTS_HSE 0x10 /* Host system error */\r
116#define USBSTS_IAA 0x20 /* Interrupt on async advance */\r
117#define USBSTS_HCH 0x1000 /* Host controller halted */\r
118#define USBSTS_PSS 0x4000 /* Periodic schedule status */\r
119#define USBSTS_ASS 0x8000 /* Asynchronous schedule status */\r
120\r
121#define USBINTR 0x08 /* Command Register Offset 08-0bh */\r
122\r
123#define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */\r
124\r
125#define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */\r
126\r
127#define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */\r
128\r
129#define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */\r
130\r
131#define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */\r
132#define CONFIGFLAG_CF 0x01 /* Configure Flag */\r
133\r
134#define PORTSC 0x44 /* Port Status/Control Offset 44-47h */\r
135#define PORTSC_CCS 0x01 /* Current Connect Status*/\r
136#define PORTSC_CSC 0x02 /* Connect Status Change */\r
137#define PORTSC_PED 0x04 /* Port Enable / Disable */\r
138#define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */\r
139#define PORTSC_OCA 0x10 /* Over current Active */\r
140#define PORTSC_OCC 0x20 /* Over current Change */\r
141#define PORTSC_FPR 0x40 /* Force Port Resume */\r
142#define PORTSC_SUSP 0x80 /* Port Suspend State */\r
143#define PORTSC_PR 0x100 /* Port Reset */\r
144#define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */\r
145#define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */\r
146#define PORTSC_PP 0x1000 /* Port Power */\r
147#define PORTSC_PO 0x2000 /* Port Owner */\r
148\r
149#define CAPLENGTH 0 /* Capability Register Length 00h */\r
150\r
151#define HCIVERSION 0x02 /* Interface Version Number 02-03h */\r
152\r
153#define HCSPARAMS 0x04 /* Structural Parameters 04-07h */\r
154#define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */\r
155\r
156#define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */\r
157#define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */\r
158#define HCCP_PFLF 0x02 /* Programmable Frame List Flag */\r
159#define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */\r
160\r
161#define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */\r
162\r
163#define CLASSC 0x09 /* Class Code 09-0bh */\r
164\r
165#define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */\r
166\r
167#define SBRN 0x60 /* Serial Bus Release Number 60h */\r
168\r
169#define FLADJ 0x61 /* Frame Length Adjustment Register 61h */\r
170\r
171#define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */\r
172\r
173//\r
174// PCI Configuration Registers\r
175//\r
176#define EHCI_PCI_CLASSC 0x09\r
177#define EHCI_PCI_MEMORY_BASE 0x10\r
178\r
179//\r
180// Memory Offset Registers\r
181//\r
182#define EHCI_MEMORY_CAPLENGTH 0x0\r
183#define EHCI_MEMORY_CONFIGFLAG 0x40\r
184\r
185//\r
186// USB Base Class Code,Sub-Class Code and Programming Interface\r
187//\r
188#define PCI_CLASSC_PI_EHCI 0x20\r
189\r
190#define SETUP_PACKET_ID 0x2D\r
191#define INPUT_PACKET_ID 0x69\r
192#define OUTPUT_PACKET_ID 0xE1\r
193#define ERROR_PACKET_ID 0x55\r
194\r
ffac4bcb 195#define bit(a) 1 << (a)\r
562d2849 196\r
ffac4bcb 197#define GET_0B_TO_31B(Addr) (UINT32) (UINTN) (Addr)\r
198#define GET_32B_TO_63B(Addr) (UINT32) (RShiftU64(((UINT64) (UINTN) (Addr)), 32) & 0xffffffff)\r
562d2849 199\r
200//\r
201// Ehci Data and Ctrl Structures\r
202//\r
203#pragma pack(1)\r
204\r
205typedef struct {\r
206 UINT8 PI;\r
207 UINT8 SubClassCode;\r
208 UINT8 BaseCode;\r
209} USB_CLASSC;\r
210\r
211typedef struct {\r
212 UINT32 NextQtdTerminate : 1;\r
213 UINT32 Rsvd1 : 4;\r
214 UINT32 NextQtdPointer : 27;\r
215\r
216 UINT32 AltNextQtdTerminate : 1;\r
217 UINT32 Rsvd2 : 4;\r
218 UINT32 AltNextQtdPointer : 27;\r
219\r
220 UINT32 Status : 8;\r
221 UINT32 PidCode : 2;\r
222 UINT32 ErrorCount : 2;\r
223 UINT32 CurrentPage : 3;\r
224 UINT32 InterruptOnComplete : 1;\r
225 UINT32 TotalBytes : 15;\r
226 UINT32 DataToggle : 1;\r
227\r
228 UINT32 CurrentOffset : 12;\r
229 UINT32 BufferPointer0 : 20;\r
230\r
231 UINT32 Rsvd3 : 12;\r
232 UINT32 BufferPointer1 : 20;\r
233\r
234 UINT32 Rsvd4 : 12;\r
235 UINT32 BufferPointer2 : 20;\r
236\r
237 UINT32 Rsvd5 : 12;\r
238 UINT32 BufferPointer3 : 20;\r
239\r
240 UINT32 Rsvd6 : 12;\r
241 UINT32 BufferPointer4 : 20;\r
242\r
243 UINT32 ExtBufferPointer0;\r
244 UINT32 ExtBufferPointer1;\r
245 UINT32 ExtBufferPointer2;\r
246 UINT32 ExtBufferPointer3;\r
247 UINT32 ExtBufferPointer4;\r
248} EHCI_QTD_HW;\r
249\r
250typedef struct {\r
251 UINT32 QhTerminate : 1;\r
252 UINT32 SelectType : 2;\r
253 UINT32 Rsvd1 : 2;\r
254 UINT32 QhHorizontalPointer : 27;\r
255\r
256 UINT32 DeviceAddr : 7;\r
257 UINT32 Inactive : 1;\r
258 UINT32 EndpointNum : 4;\r
259 UINT32 EndpointSpeed : 2;\r
260 UINT32 DataToggleControl : 1;\r
261 UINT32 HeadReclamationFlag : 1;\r
262 UINT32 MaxPacketLen : 11;\r
263 UINT32 ControlEndpointFlag : 1;\r
264 UINT32 NakCountReload : 4;\r
265\r
266 UINT32 InerruptScheduleMask : 8;\r
267 UINT32 SplitComletionMask : 8;\r
268 UINT32 HubAddr : 7;\r
269 UINT32 PortNum : 7;\r
270 UINT32 Multiplier : 2;\r
271\r
272 UINT32 Rsvd2 : 5;\r
273 UINT32 CurrentQtdPointer : 27;\r
274\r
275 UINT32 NextQtdTerminate : 1;\r
276 UINT32 Rsvd3 : 4;\r
277 UINT32 NextQtdPointer : 27;\r
278\r
279 UINT32 AltNextQtdTerminate : 1;\r
280 UINT32 NakCount : 4;\r
281 UINT32 AltNextQtdPointer : 27;\r
282\r
283 UINT32 Status : 8;\r
284 UINT32 PidCode : 2;\r
285 UINT32 ErrorCount : 2;\r
286 UINT32 CurrentPage : 3;\r
287 UINT32 InterruptOnComplete : 1;\r
288 UINT32 TotalBytes : 15;\r
289 UINT32 DataToggle : 1;\r
290\r
291 UINT32 CurrentOffset : 12;\r
292 UINT32 BufferPointer0 : 20;\r
293\r
294 UINT32 CompleteSplitMask : 8;\r
295 UINT32 Rsvd4 : 4;\r
296 UINT32 BufferPointer1 : 20;\r
297\r
298 UINT32 FrameTag : 5;\r
299 UINT32 SplitBytes : 7;\r
300 UINT32 BufferPointer2 : 20;\r
301\r
302 UINT32 Rsvd5 : 12;\r
303 UINT32 BufferPointer3 : 20;\r
304\r
305 UINT32 Rsvd6 : 12;\r
306 UINT32 BufferPointer4 : 20;\r
307\r
308 UINT32 ExtBufferPointer0;\r
309 UINT32 ExtBufferPointer1;\r
310 UINT32 ExtBufferPointer2;\r
311 UINT32 ExtBufferPointer3;\r
312 UINT32 ExtBufferPointer4;\r
313} EHCI_QH_HW;\r
314\r
315typedef struct {\r
316 UINT32 LinkTerminate : 1;\r
317 UINT32 SelectType : 2;\r
318 UINT32 Rsvd : 2;\r
319 UINT32 LinkPointer : 27;\r
320} FRAME_LIST_ENTRY;\r
321\r
322#pragma pack()\r
323\r
324typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;\r
325typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;\r
326typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;\r
327\r
ffac4bcb 328struct _EHCI_QTD_ENTITY {\r
562d2849 329 EHCI_QTD_HW Qtd;\r
330 UINT32 TotalBytes;\r
331 UINT32 StaticTotalBytes;\r
332 UINT32 StaticCurrentOffset;\r
333 EHCI_QTD_ENTITY *Prev;\r
334 EHCI_QTD_ENTITY *Next;\r
335 EHCI_QTD_ENTITY *AltNext;\r
336 EHCI_QH_ENTITY *SelfQh;\r
ffac4bcb 337};\r
562d2849 338\r
ffac4bcb 339struct _EHCI_QH_ENTITY {\r
562d2849 340 EHCI_QH_HW Qh;\r
341 EHCI_QH_ENTITY *Next;\r
342 EHCI_QH_ENTITY *Prev;\r
343 EHCI_QTD_ENTITY *FirstQtdPtr;\r
344 EHCI_QTD_ENTITY *LastQtdPtr;\r
345 EHCI_QTD_ENTITY *AltQtdPtr;\r
346 UINTN Interval;\r
347 UINT8 TransferType;\r
ffac4bcb 348};\r
562d2849 349\r
350#define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)\r
351#define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)\r
352\r
353\r
354//\r
355// Ehci Managment Structures\r
356//\r
357#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
358\r
359#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
360\r
ffac4bcb 361struct _EHCI_ASYNC_REQUEST {\r
562d2849 362 UINT8 TransferType;\r
363 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;\r
364 VOID *Context;\r
365 EHCI_ASYNC_REQUEST *Prev;\r
366 EHCI_ASYNC_REQUEST *Next;\r
367 EHCI_QH_ENTITY *QhPtr;\r
ffac4bcb 368};\r
562d2849 369\r
370typedef struct _MEMORY_MANAGE_HEADER {\r
371 UINT8 *BitArrayPtr;\r
372 UINTN BitArraySizeInBytes;\r
373 UINT8 *MemoryBlockPtr;\r
374 UINTN MemoryBlockSizeInBytes;\r
375 VOID *Mapping;\r
376 struct _MEMORY_MANAGE_HEADER *Next;\r
377} MEMORY_MANAGE_HEADER;\r
378\r
379typedef struct _USB2_HC_DEV {\r
380 UINTN Signature;\r
381 EFI_PCI_IO_PROTOCOL *PciIo;\r
382 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
383 UINTN PeriodicFrameListLength;\r
384 VOID *PeriodicFrameListBuffer;\r
385 VOID *PeriodicFrameListMap;\r
386 VOID *AsyncList;\r
387 EHCI_ASYNC_REQUEST *AsyncRequestList;\r
388 EFI_EVENT AsyncRequestEvent;\r
389 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
390 MEMORY_MANAGE_HEADER *MemoryHeader;\r
391 UINT8 Is64BitCapable;\r
392 UINT32 High32BitAddr;\r
393} USB2_HC_DEV;\r
394\r
395\r
396//\r
397// Internal Functions Declaration\r
398//\r
399\r
400//\r
401// EhciMem Functions\r
402//\r
403EFI_STATUS\r
404CreateMemoryBlock (\r
405 IN USB2_HC_DEV *HcDev,\r
406 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
407 IN UINTN MemoryBlockSizeInPages\r
408 )\r
409/*++\r
410\r
411Routine Description:\r
412\r
413 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,\r
414 and use PciIo->Map to map the common buffer for Bus Master Read/Write.\r
415\r
416Arguments:\r
417\r
418 HcDev - USB2_HC_DEV\r
419 MemoryHeader - MEMORY_MANAGE_HEADER to output\r
420 MemoryBlockSizeInPages - MemoryBlockSizeInPages\r
421 \r
422Returns:\r
423\r
424 EFI_SUCCESS Success\r
425 EFI_OUT_OF_RESOURCES Fail for no resources\r
426 EFI_UNSUPPORTED Unsupported currently\r
427 \r
428--*/\r
429;\r
430\r
431EFI_STATUS\r
432FreeMemoryHeader (\r
433 IN USB2_HC_DEV *HcDev,\r
434 IN MEMORY_MANAGE_HEADER *MemoryHeader\r
435 )\r
436/*++\r
437\r
438Routine Description:\r
439\r
440 Free Memory Header\r
441\r
442Arguments:\r
443\r
444 HcDev - USB2_HC_DEV\r
445 MemoryHeader - MemoryHeader to be freed\r
446\r
447Returns:\r
448\r
449 EFI_SUCCESS Success\r
450 EFI_INVALID_PARAMETER Parameter is error\r
451\r
452--*/\r
453;\r
454\r
455VOID\r
456InsertMemoryHeaderToList (\r
457 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
458 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
459 )\r
460/*++\r
461\r
462Routine Description:\r
463\r
464 Insert Memory Header To List\r
465\r
466Arguments:\r
467\r
468 MemoryHeader - MEMORY_MANAGE_HEADER\r
469 NewMemoryHeader - MEMORY_MANAGE_HEADER\r
470\r
471Returns:\r
472\r
473 VOID\r
474\r
475--*/\r
476;\r
477\r
478EFI_STATUS\r
479AllocMemInMemoryBlock (\r
480 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
481 OUT VOID **Pool,\r
482 IN UINTN NumberOfMemoryUnit\r
483 )\r
484/*++\r
485\r
486Routine Description:\r
487\r
488 Alloc Memory In MemoryBlock\r
489\r
490Arguments:\r
491\r
492 MemoryHeader - MEMORY_MANAGE_HEADER\r
493 Pool - Place to store pointer to memory\r
494 NumberOfMemoryUnit - Number Of Memory Unit\r
495\r
496Returns:\r
497\r
498 EFI_SUCCESS Success\r
499 EFI_NOT_FOUND Can't find the free memory \r
500\r
501--*/\r
502;\r
503\r
504BOOLEAN\r
505IsMemoryBlockEmptied (\r
506 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
507 )\r
508/*++\r
509\r
510Routine Description:\r
511\r
512 Is Memory Block Emptied\r
513\r
514Arguments:\r
515\r
516 MemoryHeaderPtr - MEMORY_MANAGE_HEADER\r
517\r
518Returns:\r
519\r
520 TRUE Empty\r
521 FALSE Not Empty \r
522\r
523--*/\r
524;\r
525\r
526VOID\r
527DelinkMemoryBlock (\r
528 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
529 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader\r
530 )\r
531/*++\r
532\r
533Routine Description:\r
534\r
535 Delink Memory Block\r
536\r
537Arguments:\r
538\r
539 FirstMemoryHeader - MEMORY_MANAGE_HEADER\r
540 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER\r
541\r
542Returns:\r
543\r
544 VOID\r
545\r
546--*/\r
547;\r
548\r
549EFI_STATUS\r
550InitialMemoryManagement (\r
551 IN USB2_HC_DEV *HcDev\r
552 )\r
553/*++\r
554\r
555Routine Description:\r
556\r
557 Initialize Memory Management\r
558\r
559Arguments:\r
560\r
561 HcDev - USB2_HC_DEV\r
562\r
563Returns:\r
564\r
565 EFI_SUCCESS Success\r
566 EFI_DEVICE_ERROR Fail\r
567\r
568--*/\r
569;\r
570\r
571EFI_STATUS\r
572DeinitialMemoryManagement (\r
573 IN USB2_HC_DEV *HcDev\r
574 )\r
575/*++\r
576\r
577Routine Description:\r
578\r
579 Deinitialize Memory Management\r
580\r
581Arguments:\r
582\r
583 HcDev - USB2_HC_DEV\r
584\r
585Returns:\r
586\r
587 EFI_SUCCESS Success\r
588 EFI_DEVICE_ERROR Fail\r
589 \r
590--*/\r
591;\r
592\r
593EFI_STATUS\r
594EhciAllocatePool (\r
595 IN USB2_HC_DEV *HcDev,\r
596 OUT UINT8 **Pool,\r
597 IN UINTN AllocSize\r
598 )\r
599/*++\r
600\r
601Routine Description:\r
602\r
603 Ehci Allocate Pool\r
604\r
605Arguments:\r
606\r
607 HcDev - USB2_HC_DEV\r
608 Pool - Place to store pointer to the memory buffer\r
609 AllocSize - Alloc Size\r
610\r
611Returns:\r
612\r
613 EFI_SUCCESS Success\r
614 EFI_DEVICE_ERROR Fail\r
615 \r
616--*/\r
617;\r
618\r
619VOID\r
620EhciFreePool (\r
621 IN USB2_HC_DEV *HcDev,\r
622 IN UINT8 *Pool,\r
623 IN UINTN AllocSize\r
624 )\r
625/*++\r
626\r
627Routine Description:\r
628\r
629 Uhci Free Pool\r
630\r
631Arguments:\r
632\r
633 HcDev - USB_HC_DEV\r
634 Pool - Pool to free\r
635 AllocSize - Pool size\r
636\r
637Returns:\r
638\r
639 VOID\r
640\r
641--*/\r
642;\r
643\r
644//\r
645// EhciReg Functions\r
646//\r
647EFI_STATUS\r
648ReadEhcCapabiltiyReg (\r
649 IN USB2_HC_DEV *HcDev,\r
650 IN UINT32 CapabiltiyRegAddr,\r
651 IN OUT UINT32 *Data\r
652 )\r
653/*++\r
654\r
655Routine Description:\r
656\r
657 Read Ehc Capabitlity register\r
658 \r
659Arguments:\r
660\r
661 HcDev - USB2_HC_DEV \r
662 CapabiltiyRegAddr - Ehc Capability register address\r
663 Data - A pointer to data read from register\r
664 \r
665Returns:\r
666\r
667 EFI_SUCCESS Success\r
668 EFI_DEVICE_ERROR Fail\r
669 \r
670--*/\r
671;\r
672\r
673EFI_STATUS\r
674ReadEhcOperationalReg (\r
675 IN USB2_HC_DEV *HcDev,\r
676 IN UINT32 OperationalRegAddr,\r
677 IN OUT UINT32 *Data\r
678 )\r
679/*++\r
680\r
681Routine Description:\r
682\r
683 Read Ehc Operation register\r
684 \r
685Arguments:\r
686\r
687 HcDev - USB2_HC_DEV \r
688 OperationalRegAddr - Ehc Operation register address\r
689 Data - A pointer to data read from register\r
690 \r
691Returns:\r
692\r
693 EFI_SUCCESS Success\r
694 EFI_DEVICE_ERROR Fail\r
695 \r
696--*/\r
697;\r
698\r
699EFI_STATUS\r
700WriteEhcOperationalReg (\r
701 IN USB2_HC_DEV *HcDev,\r
702 IN UINT32 OperationalRegAddr,\r
703 IN UINT32 Data\r
704 )\r
705/*++\r
706\r
707Routine Description:\r
708\r
709 Write Ehc Operation register\r
710 \r
711Arguments:\r
712\r
713 HcDev - USB2_HC_DEV \r
714 OperationalRegAddr - Ehc Operation register address\r
715 Data - 32bit write to register\r
716 \r
717Returns:\r
718\r
719 EFI_SUCCESS Success\r
720 EFI_DEVICE_ERROR Fail\r
721 \r
722--*/\r
723;\r
724\r
725EFI_STATUS\r
726SetEhcDoorbell (\r
727 IN USB2_HC_DEV *HcDev\r
728 )\r
729/*++\r
730\r
731Routine Description:\r
732\r
733 Set Ehc door bell bit\r
734 \r
735Arguments:\r
736\r
737 HcDev - USB2_HC_DEV \r
738 \r
739Returns:\r
740\r
741 EFI_SUCCESS Success\r
742 EFI_DEVICE_ERROR Fail\r
743 \r
744--*/\r
745;\r
746\r
747EFI_STATUS\r
748SetFrameListLen (\r
749 IN USB2_HC_DEV *HcDev,\r
750 IN UINTN Length\r
751 )\r
752/*++\r
753\r
754Routine Description:\r
755\r
756 Set the length of Frame List\r
757 \r
758Arguments:\r
759\r
760 HcDev - USB2_HC_DEV \r
761 Length - the required length of frame list\r
762 \r
763Returns:\r
764\r
765 EFI_SUCCESS Success\r
766 EFI_INVALID_PARAMETER Invalid parameter\r
767 EFI_DEVICE_ERROR Fail\r
768 \r
769--*/\r
770;\r
771\r
772BOOLEAN\r
773IsFrameListProgrammable (\r
774 IN USB2_HC_DEV *HcDev\r
775 )\r
776/*++\r
777\r
778Routine Description:\r
779\r
780 Whether frame list is programmable\r
781 \r
782Arguments:\r
783\r
784 HcDev - USB2_HC_DEV \r
785 \r
786Returns:\r
787\r
788 TRUE Programmable\r
789 FALSE Unprogrammable\r
790 \r
791--*/\r
792;\r
793\r
794BOOLEAN\r
795IsPeriodicScheduleEnabled (\r
796 IN USB2_HC_DEV *HcDev\r
797 )\r
798/*++\r
799\r
800Routine Description:\r
801\r
802 Whether periodic schedule is enabled\r
803 \r
804Arguments:\r
805\r
806 HcDev - USB2_HC_DEV \r
807 \r
808Returns:\r
809\r
810 TRUE Enabled\r
811 FALSE Disabled\r
812 \r
813--*/\r
814;\r
815\r
816BOOLEAN\r
817IsAsyncScheduleEnabled (\r
818 IN USB2_HC_DEV *HcDev\r
819 )\r
820/*++\r
821\r
822Routine Description:\r
823\r
824 Whether asynchronous schedule is enabled\r
825 \r
826Arguments:\r
827\r
828 HcDev - USB2_HC_DEV \r
829 \r
830Returns:\r
831\r
832 TRUE Enabled\r
833 FALSE Disabled\r
834 \r
835--*/\r
836;\r
837\r
838BOOLEAN\r
839IsEhcPortEnabled (\r
840 IN USB2_HC_DEV *HcDev,\r
841 IN UINT8 PortNum\r
842 )\r
843/*++\r
844\r
845Routine Description:\r
846\r
847 Whether port is enabled\r
848 \r
849Arguments:\r
850\r
851 HcDev - USB2_HC_DEV \r
852 \r
853Returns:\r
854\r
855 TRUE Enabled\r
856 FALSE Disabled\r
857 \r
858--*/\r
859;\r
860\r
861BOOLEAN\r
862IsEhcReseted (\r
863 IN USB2_HC_DEV *HcDev\r
864 )\r
865/*++\r
866\r
867Routine Description:\r
868\r
869 Whether Ehc is halted\r
870 \r
871Arguments:\r
872\r
873 HcDev - USB2_HC_DEV \r
874 \r
875Returns:\r
876\r
877 TRUE Reseted\r
878 FALSE Unreseted\r
879 \r
880--*/\r
881;\r
882\r
883BOOLEAN\r
884IsEhcHalted (\r
885 IN USB2_HC_DEV *HcDev\r
886 )\r
887/*++\r
888\r
889Routine Description:\r
890\r
891 Whether Ehc is halted\r
892 \r
893Arguments:\r
894\r
895 HcDev - USB2_HC_DEV \r
896 \r
897Returns:\r
898\r
899 TRUE Halted\r
900 FALSE Not halted\r
901 \r
902--*/\r
903;\r
904\r
905BOOLEAN\r
906IsEhcSysError (\r
907 IN USB2_HC_DEV *HcDev\r
908 )\r
909/*++\r
910\r
911Routine Description:\r
912\r
913 Whether Ehc is system error\r
914 \r
915Arguments:\r
916\r
917 HcDev - USB2_HC_DEV \r
918 \r
919Returns:\r
920\r
921 TRUE System error\r
922 FALSE No system error\r
923 \r
924--*/\r
925;\r
926\r
927BOOLEAN\r
928IsHighSpeedDevice (\r
929 IN EFI_USB2_HC_PROTOCOL *This,\r
930 IN UINT8 PortNum \r
931 )\r
932/*++\r
933\r
934Routine Description:\r
935\r
936 Whether high speed device attached\r
937 \r
938Arguments:\r
939\r
940 HcDev - USB2_HC_DEV \r
941 \r
942Returns:\r
943\r
944 TRUE High speed\r
945 FALSE Full speed\r
946 \r
947--*/\r
948;\r
949\r
950EFI_STATUS\r
951WaitForEhcReset (\r
952 IN USB2_HC_DEV *HcDev,\r
953 IN UINTN Timeout\r
954 )\r
955/*++\r
956\r
957Routine Description:\r
958\r
959 wait for Ehc reset or timeout\r
960 \r
961Arguments:\r
962\r
963 HcDev - USB2_HC_DEV \r
964 Timeout - timeout threshold\r
965 \r
966Returns:\r
967\r
968 EFI_SUCCESS Success\r
969 EFI_TIMEOUT Timeout\r
970 \r
971--*/\r
972;\r
973\r
974EFI_STATUS\r
975WaitForEhcHalt (\r
976 IN USB2_HC_DEV *HcDev,\r
977 IN UINTN Timeout\r
978 )\r
979/*++\r
980\r
981Routine Description:\r
982\r
983 wait for Ehc halt or timeout\r
984 \r
985Arguments:\r
986\r
987 HcDev - USB2_HC_DEV \r
988 Timeout - timeout threshold\r
989 \r
990Returns:\r
991\r
992 EFI_SUCCESS Success\r
993 EFI_TIMEOUT Timeout\r
994 \r
995--*/\r
996;\r
997\r
998EFI_STATUS\r
999WaitForEhcNotHalt (\r
1000 IN USB2_HC_DEV *HcDev,\r
1001 IN UINTN Timeout\r
1002 )\r
1003/*++\r
1004\r
1005Routine Description:\r
1006\r
1007 wait for Ehc not halt or timeout\r
1008 \r
1009Arguments:\r
1010\r
1011 HcDev - USB2_HC_DEV \r
1012 Timeout - timeout threshold\r
1013 \r
1014Returns:\r
1015\r
1016 EFI_SUCCESS Success\r
1017 EFI_TIMEOUT Timeout\r
1018 \r
1019--*/\r
1020;\r
1021\r
1022EFI_STATUS\r
1023WaitForEhcDoorbell (\r
1024 IN USB2_HC_DEV *HcDev,\r
1025 IN UINTN Timeout\r
1026 )\r
1027/*++\r
1028\r
1029Routine Description:\r
1030\r
1031 Wait for periodic schedule disable or timeout\r
1032\r
1033Arguments:\r
1034\r
1035 HcDev - USB2_HC_DEV \r
1036 Timeout - timeout threshold\r
1037\r
1038Returns:\r
1039\r
1040 EFI_SUCCESS Success\r
1041 EFI_TIMEOUT Timeout\r
1042 \r
1043--*/\r
1044;\r
1045\r
1046EFI_STATUS\r
1047WaitForAsyncScheduleEnable (\r
1048 IN USB2_HC_DEV *HcDev,\r
1049 IN UINTN Timeout\r
1050 )\r
1051/*++\r
1052\r
1053Routine Description:\r
1054\r
1055 Wait for Ehc asynchronous schedule enable or timeout\r
1056 \r
1057Arguments:\r
1058\r
1059 HcDev - USB2_HC_DEV \r
1060 Timeout - timeout threshold\r
1061 \r
1062Returns:\r
1063\r
1064 EFI_SUCCESS Success\r
1065 EFI_TIMEOUT Timeout\r
1066 \r
1067--*/\r
1068;\r
1069\r
1070EFI_STATUS\r
1071WaitForAsyncScheduleDisable (\r
1072 IN USB2_HC_DEV *HcDev,\r
1073 IN UINTN Timeout\r
1074 )\r
1075/*++\r
1076\r
1077Routine Description:\r
1078\r
1079 Wait for Ehc asynchronous schedule disable or timeout\r
1080 \r
1081Arguments:\r
1082\r
1083 HcDev - USB2_HC_DEV \r
1084 Timeout - timeout threshold\r
1085 \r
1086Returns:\r
1087\r
1088 EFI_SUCCESS Success\r
1089 EFI_TIMEOUT Timeout\r
1090 \r
1091--*/\r
1092;\r
1093\r
1094EFI_STATUS\r
1095WaitForPeriodicScheduleEnable (\r
1096 IN USB2_HC_DEV *HcDev,\r
1097 IN UINTN Timeout\r
1098 )\r
1099/*++\r
1100\r
1101Routine Description:\r
1102\r
1103 Wait for Ehc periodic schedule enable or timeout\r
1104 \r
1105Arguments:\r
1106\r
1107 HcDev - USB2_HC_DEV \r
1108 Timeout - timeout threshold\r
1109 \r
1110Returns:\r
1111\r
1112 EFI_SUCCESS Success\r
1113 EFI_TIMEOUT Timeout\r
1114 \r
1115--*/\r
1116;\r
1117\r
1118EFI_STATUS\r
1119WaitForPeriodicScheduleDisable (\r
1120 IN USB2_HC_DEV *HcDev,\r
1121 IN UINTN Timeout\r
1122 )\r
1123/*++\r
1124\r
1125Routine Description:\r
1126\r
1127 Wait for periodic schedule disable or timeout\r
1128 \r
1129Arguments:\r
1130\r
1131 HcDev - USB2_HC_DEV \r
1132 Timeout - timeout threshold\r
1133 \r
1134Returns:\r
1135\r
1136 EFI_SUCCESS Success\r
1137 EFI_TIMEOUT Timeout\r
1138 \r
1139--*/\r
1140;\r
1141\r
1142EFI_STATUS\r
1143GetCapabilityLen (\r
1144 IN USB2_HC_DEV *HcDev\r
1145 )\r
1146/*++\r
1147\r
1148Routine Description:\r
1149\r
1150 Get the length of capability register\r
1151 \r
1152Arguments:\r
1153\r
1154 HcDev - USB2_HC_DEV \r
1155 \r
1156Returns:\r
1157\r
1158 EFI_SUCCESS Success\r
1159 EFI_DEVICE_ERROR Fail\r
1160 \r
1161--*/\r
1162;\r
1163\r
1164EFI_STATUS\r
1165SetFrameListBaseAddr (\r
1166 IN USB2_HC_DEV *HcDev,\r
1167 IN UINT32 FrameBuffer\r
1168 )\r
1169/*++\r
1170\r
1171Routine Description:\r
1172\r
1173 Set base address of frame list first entry\r
1174 \r
1175Arguments:\r
1176\r
1177 HcDev - USB2_HC_DEV \r
1178 FrameBuffer - base address of first entry of frame list\r
1179 \r
1180Returns:\r
1181\r
1182 EFI_SUCCESS Success\r
1183 EFI_DEVICE_ERROR Fail\r
1184 \r
1185--*/\r
1186;\r
1187\r
1188EFI_STATUS\r
1189SetAsyncListAddr (\r
1190 IN USB2_HC_DEV *HcDev,\r
1191 IN EHCI_QH_ENTITY *QhPtr\r
1192 )\r
1193/*++\r
1194\r
1195Routine Description:\r
1196\r
1197 Set address of first Async schedule Qh\r
1198 \r
1199Arguments:\r
1200\r
1201 HcDev - USB2_HC_DEV \r
1202 QhPtr - A pointer to first Qh in the Async schedule\r
1203 \r
1204Returns:\r
1205\r
1206 EFI_SUCCESS Success\r
1207 EFI_DEVICE_ERROR Fail\r
1208 \r
1209--*/\r
1210;\r
1211\r
1212EFI_STATUS\r
1213SetCtrlDataStructSeg (\r
1214 IN USB2_HC_DEV *HcDev\r
1215 )\r
1216/*++\r
1217\r
1218Routine Description:\r
1219\r
1220 Set address of first Async schedule Qh\r
1221 \r
1222Arguments:\r
1223\r
1224 HcDev - USB2_HC_DEV \r
1225 QhPtr - A pointer to first Qh in the Async schedule\r
1226 \r
1227Returns:\r
1228\r
1229 EFI_SUCCESS Success\r
1230 EFI_DEVICE_ERROR Fail\r
1231 \r
1232--*/\r
1233;\r
1234\r
1235EFI_STATUS\r
1236SetPortRoutingEhc (\r
1237 IN USB2_HC_DEV *HcDev\r
1238 )\r
1239/*++\r
1240\r
1241Routine Description:\r
1242\r
1243 Set Ehc port routing bit\r
1244 \r
1245Arguments:\r
1246\r
1247 HcDev - USB2_HC_DEV \r
1248 \r
1249Returns:\r
1250\r
1251 EFI_SUCCESS Success\r
1252 EFI_DEVICE_ERROR Fail\r
1253 \r
1254--*/\r
1255;\r
1256\r
1257EFI_STATUS\r
1258EnablePeriodicSchedule (\r
1259 IN USB2_HC_DEV *HcDev\r
1260 )\r
1261/*++\r
1262\r
1263Routine Description:\r
1264\r
1265 Enable periodic schedule\r
1266 \r
1267Arguments:\r
1268\r
1269 HcDev - USB2_HC_DEV \r
1270 \r
1271Returns:\r
1272\r
1273 EFI_SUCCESS Success\r
1274 EFI_DEVICE_ERROR Fail\r
1275 \r
1276--*/\r
1277;\r
1278\r
1279EFI_STATUS\r
1280DisablePeriodicSchedule (\r
1281 IN USB2_HC_DEV *HcDev\r
1282 )\r
1283/*++\r
1284\r
1285Routine Description:\r
1286\r
1287 Disable periodic schedule\r
1288 \r
1289Arguments:\r
1290\r
1291 HcDev - USB2_HC_DEV \r
1292 \r
1293Returns:\r
1294\r
1295 EFI_SUCCESS Success\r
1296 EFI_DEVICE_ERROR Fail\r
1297 \r
1298--*/\r
1299;\r
1300\r
1301EFI_STATUS\r
1302EnableAsynchronousSchedule (\r
1303 IN USB2_HC_DEV *HcDev\r
1304 )\r
1305/*++\r
1306\r
1307Routine Description:\r
1308\r
1309 Enable asynchrounous schedule\r
1310 \r
1311Arguments:\r
1312\r
1313 HcDev - USB2_HC_DEV \r
1314 \r
1315Returns:\r\r
1316\r
1317 EFI_SUCCESS Success\r
1318 EFI_DEVICE_ERROR Fail\r
1319 \r
1320--*/\r
1321;\r
1322\r
1323EFI_STATUS\r
1324DisableAsynchronousSchedule (\r
1325 IN USB2_HC_DEV *HcDev\r
1326 )\r
1327/*++\r
1328\r
1329Routine Description:\r
1330\r
1331 Disable asynchrounous schedule\r
1332 \r
1333Arguments:\r
1334\r
1335 HcDev - USB2_HC_DEV \r
1336 \r
1337Returns:\r
1338\r
1339 EFI_SUCCESS Success\r
1340 EFI_DEVICE_ERROR Fail\r
1341 \r
1342--*/\r
1343;\r
1344\r
1345EFI_STATUS\r
1346StartScheduleExecution (\r
1347 IN USB2_HC_DEV *HcDev\r
1348 )\r
1349/*++\r
1350\r
1351Routine Description:\r
1352\r
1353 Start Ehc schedule execution\r
1354 \r
1355Arguments:\r
1356\r
1357 HcDev - USB2_HC_DEV \r
1358 \r
1359Returns:\r
1360\r
1361 EFI_SUCCESS Success\r
1362 EFI_DEVICE_ERROR Fail\r
1363 \r
1364--*/\r
1365;\r
1366\r
1367EFI_STATUS\r
1368ResetEhc (\r
1369 IN USB2_HC_DEV *HcDev\r
1370 )\r
1371/*++\r
1372\r
1373Routine Description:\r
1374\r
1375 Reset Ehc\r
1376 \r
1377Arguments:\r
1378\r
1379 HcDev - USB2_HC_DEV \r
1380 \r
1381Returns:\r
1382\r
1383 EFI_SUCCESS Success\r
1384 EFI_DEVICE_ERROR Fail\r
1385 \r
1386--*/\r
1387;\r
1388\r
1389EFI_STATUS\r
1390ClearEhcAllStatus (\r
1391 IN USB2_HC_DEV *HcDev\r
1392 )\r
1393/*++\r
1394\r
1395Routine Description:\r
1396\r
1397 Clear Ehc all status bits\r
1398 \r
1399Arguments:\r
1400\r
1401 HcDev - USB2_HC_DEV \r
1402 \r
1403Returns:\r
1404\r
1405 EFI_SUCCESS Success\r
1406 EFI_DEVICE_ERROR Fail\r
1407 \r
1408--*/\r
1409;\r
1410\r
1411//\r
1412// EhciSched Functions\r
1413//\r
1414EFI_STATUS\r
1415InitialPeriodicFrameList (\r
1416 IN USB2_HC_DEV *HcDev,\r
1417 IN UINTN Length\r
1418 )\r
1419/*++\r
1420\r
1421Routine Description:\r
1422\r
1423 Initialize Periodic Schedule Frame List\r
1424\r
1425Arguments:\r
1426\r
1427 HcDev - USB2_HC_DEV\r
1428 Length - Frame List Length\r
1429 \r
1430Returns:\r
1431\r
1432 EFI_SUCCESS Success\r
1433 EFI_DEVICE_ERROR Fail\r
1434 \r
1435--*/\r
1436;\r
1437\r
1438VOID\r
1439DeinitialPeriodicFrameList (\r
1440 IN USB2_HC_DEV *HcDev\r
1441 )\r
1442/*++\r
1443\r
1444Routine Description:\r
1445\r
1446 Deinitialize Periodic Schedule Frame List\r
1447\r
1448Arguments:\r
1449\r
1450 HcDev - USB2_HC_DEV\r
1451\r
1452Returns:\r
1453\r
1454 VOID\r
1455 \r
1456--*/\r
1457;\r
1458\r
1459EFI_STATUS\r
1460CreatePollingTimer (\r
1461 IN USB2_HC_DEV *HcDev,\r
1462 IN EFI_EVENT_NOTIFY NotifyFunction\r
1463 )\r
1464/*++\r
1465\r
1466Routine Description:\r
1467\r
1468 Create Async Request Polling Timer\r
1469\r
1470Arguments:\r
1471\r
1472 HcDev - USB2_HC_DEV\r
1473 NotifyFunction - Timer Notify Function\r
1474 \r
1475Returns:\r
1476\r
1477 EFI_SUCCESS Success\r
1478 EFI_DEVICE_ERROR Fail\r
1479 \r
1480--*/\r
1481;\r
1482\r
1483EFI_STATUS\r
1484DestoryPollingTimer (\r
1485 IN USB2_HC_DEV *HcDev\r
1486 )\r
1487/*++\r
1488\r
1489Routine Description:\r
1490\r
1491 Destory Async Request Polling Timer\r
1492\r
1493Arguments:\r
1494\r
1495 HcDev - USB2_HC_DEV\r
1496 \r
1497Returns:\r
1498\r
1499 EFI_SUCCESS Success\r
1500 EFI_DEVICE_ERROR Fail\r
1501 \r
1502--*/\r
1503;\r
1504\r
1505EFI_STATUS\r
1506StartPollingTimer (\r
1507 IN USB2_HC_DEV *HcDev\r
1508 )\r
1509/*++\r
1510\r
1511Routine Description:\r
1512\r
1513 Start Async Request Polling Timer\r
1514\r
1515Arguments:\r
1516\r
1517 HcDev - USB2_HC_DEV\r
1518 \r
1519Returns:\r
1520\r
1521 EFI_SUCCESS Success\r
1522 EFI_DEVICE_ERROR Fail\r
1523 \r
1524--*/\r
1525;\r
1526\r
1527EFI_STATUS\r
1528StopPollingTimer (\r
1529 IN USB2_HC_DEV *HcDev\r
1530 )\r
1531/*++\r
1532\r
1533Routine Description:\r
1534\r
1535 Stop Async Request Polling Timer\r
1536\r
1537Arguments:\r
1538\r
1539 HcDev - USB2_HC_DEV\r
1540 \r
1541Returns:\r
1542\r
1543 EFI_SUCCESS Success\r
1544 EFI_DEVICE_ERROR Fail\r
1545 \r
1546--*/\r
1547;\r
1548\r
1549EFI_STATUS\r
1550CreateQh (\r
1551 IN USB2_HC_DEV *HcDev,\r
1552 IN UINT8 DeviceAddr,\r
1553 IN UINT8 Endpoint,\r
1554 IN UINT8 DeviceSpeed,\r
1555 IN UINTN MaxPacketLen,\r
1556 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1557 )\r
1558/*++\r
1559\r
1560Routine Description:\r
1561\r
1562 Create Qh Structure and Pre-Initialize\r
1563\r
1564Arguments:\r
1565\r
1566 HcDev - USB2_HC_DEV \r
1567 DeviceAddr - Address of Device\r
1568 Endpoint - Endpoint Number\r
1569 DeviceSpeed - Device Speed\r
1570 MaxPacketLen - Max Length of one Packet\r
1571 QhPtrPtr - A pointer of pointer to Qh for return\r
1572 \r
1573Returns:\r
1574\r
1575 EFI_SUCCESS Success\r
1576 EFI_DEVICE_ERROR Fail\r
1577 \r
1578--*/\r
1579;\r
1580\r
1581EFI_STATUS\r
1582CreateControlQh (\r
1583 IN USB2_HC_DEV *HcDev,\r
1584 IN UINT8 DeviceAddr,\r
1585 IN UINT8 DeviceSpeed,\r
1586 IN UINTN MaxPacketLen,\r
1587 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1588 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1589 )\r
1590/*++\r
1591\r
1592Routine Description:\r
1593\r
1594 Create Qh for Control Transfer\r
1595\r
1596Arguments:\r
1597\r
1598 HcDev - USB2_HC_DEV \r
1599 DeviceAddr - Address of Device\r
1600 DeviceSpeed - Device Speed\r
1601 MaxPacketLen - Max Length of one Packet\r
1602 Translator - Translator Transaction for SplitX\r
1603 QhPtrPtr - A pointer of pointer to Qh for return\r
1604 \r
1605Returns:\r
1606\r
1607 EFI_SUCCESS Success\r
1608 EFI_DEVICE_ERROR Fail\r
1609 \r
1610--*/\r
1611;\r
1612\r
1613EFI_STATUS\r
1614CreateBulkQh (\r
1615 IN USB2_HC_DEV *HcDev,\r
1616 IN UINT8 DeviceAddr,\r
1617 IN UINT8 EndPointAddr,\r
1618 IN UINT8 DeviceSpeed,\r
1619 IN UINT8 DataToggle,\r
1620 IN UINTN MaxPacketLen,\r
1621 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1622 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1623 )\r
1624/*++\r
1625\r
1626Routine Description:\r
1627\r
1628 Create Qh for Bulk Transfer\r
1629\r
1630Arguments:\r
1631\r
1632 HcDev - USB2_HC_DEV \r
1633 DeviceAddr - Address of Device\r
1634 EndPointAddr - Address of Endpoint\r
1635 DeviceSpeed - Device Speed\r
1636 MaxPacketLen - Max Length of one Packet\r
1637 Translator - Translator Transaction for SplitX\r
1638 QhPtrPtr - A pointer of pointer to Qh for return\r
1639 \r
1640Returns:\r
1641\r
1642 EFI_SUCCESS Success\r
1643 EFI_DEVICE_ERROR Fail\r
1644 \r
1645--*/\r
1646;\r
1647\r
1648EFI_STATUS\r
1649CreateInterruptQh (\r
1650 IN USB2_HC_DEV *HcDev,\r
1651 IN UINT8 DeviceAddr,\r
1652 IN UINT8 EndPointAddr,\r
1653 IN UINT8 DeviceSpeed,\r
1654 IN UINT8 DataToggle,\r
1655 IN UINTN MaxPacketLen,\r
1656 IN UINTN Interval,\r
1657 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1658 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1659 )\r
1660/*++\r
1661\r
1662Routine Description:\r
1663\r
1664 Create Qh for Control Transfer\r
1665\r
1666Arguments:\r
1667\r
1668 HcDev - USB2_HC_DEV \r
1669 DeviceAddr - Address of Device\r
1670 EndPointAddr - Address of Endpoint\r
1671 DeviceSpeed - Device Speed\r
1672 MaxPacketLen - Max Length of one Packet\r
1673 Interval - value of interval\r
1674 Translator - Translator Transaction for SplitX\r
1675 QhPtrPtr - A pointer of pointer to Qh for return\r
1676 \r
1677Returns:\r
1678\r
1679 EFI_SUCCESS Success\r
1680 EFI_DEVICE_ERROR Fail\r
1681 \r
1682--*/\r
1683;\r
1684\r
1685VOID\r
1686DestoryQh (\r
1687 IN USB2_HC_DEV *HcDev,\r
1688 IN EHCI_QH_ENTITY *QhPtr\r
1689 )\r
1690/*++\r
1691\r
1692Routine Description:\r
1693\r
1694 Destory Qh Structure \r
1695 \r
1696Arguments:\r
1697\r
1698 HcDev - USB2_HC_DEV \r
1699 QhPtr - A pointer to Qh\r
1700 \r
1701Returns:\r
1702\r
1703 VOID\r
1704 \r
1705--*/\r
1706;\r
1707\r
1708EFI_STATUS\r
1709CreateQtd (\r
1710 IN USB2_HC_DEV *HcDev,\r
1711 IN UINT8 *DataPtr,\r
1712 IN UINTN DataLen,\r
1713 IN UINT8 PktId,\r
1714 IN UINT8 Toggle,\r
1715 IN UINT8 QtdStatus,\r
1716 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1717 )\r
1718/*++\r
1719\r
1720Routine Description:\r
1721\r
1722 Create Qtd Structure and Pre-Initialize it\r
1723\r
1724Arguments:\r
1725\r
1726 HcDev - USB2_HC_DEV \r
1727 DataPtr - A pointer to user data buffer to transfer\r
1728 DataLen - Length of user data to transfer\r
1729 PktId - Packet Identification of this Qtd\r
1730 Toggle - Data Toggle of this Qtd\r
1731 QtdStatus - Default value of status of this Qtd\r
1732 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1733 \r
1734Returns:\r
1735\r
1736 EFI_SUCCESS Success\r
1737 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1738 \r
1739--*/\r
1740;\r
1741\r
1742EFI_STATUS\r
1743CreateSetupQtd (\r
1744 IN USB2_HC_DEV *HcDev,\r
1745 IN UINT8 *DevReqPtr,\r
1746 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1747 )\r
1748/*++\r
1749\r
1750Routine Description:\r
1751\r
1752 Create Qtd Structure for Setup \r
1753\r
1754Arguments:\r
1755\r
1756 HcDev - USB2_HC_DEV \r
1757 DevReqPtr - A pointer to Device Request Data\r
1758 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1759 \r
1760Returns:\r
1761\r
1762 EFI_SUCCESS Success\r
1763 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1764 \r
1765--*/\r
1766;\r
1767\r
1768EFI_STATUS\r
1769CreateDataQtd (\r
1770 IN USB2_HC_DEV *HcDev,\r
1771 IN UINT8 *DataPtr,\r
1772 IN UINTN DataLen,\r
1773 IN UINT8 PktId,\r
1774 IN UINT8 Toggle,\r
1775 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1776 )\r
1777/*++\r
1778\r
1779Routine Description:\r
1780\r
1781 Create Qtd Structure for data \r
1782\r
1783Arguments:\r
1784\r
1785 HcDev - USB2_HC_DEV \r
1786 DataPtr - A pointer to user data buffer to transfer\r
1787 DataLen - Length of user data to transfer\r
1788 PktId - Packet Identification of this Qtd\r
1789 Toggle - Data Toggle of this Qtd\r
1790 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1791 \r
1792Returns:\r
1793\r
1794 EFI_SUCCESS Success\r
1795 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1796 \r
1797--*/\r
1798;\r
1799\r
1800EFI_STATUS\r
1801CreateStatusQtd (\r
1802 IN USB2_HC_DEV *HcDev,\r
1803 IN UINT8 PktId,\r
1804 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1805 )\r
1806/*++\r
1807\r
1808Routine Description:\r
1809\r
1810 Create Qtd Structure for status \r
1811\r
1812Arguments:\r
1813\r
1814 HcDev - USB2_HC_DEV \r
1815 PktId - Packet Identification of this Qtd\r
1816 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1817 \r
1818Returns:\r
1819\r
1820 EFI_SUCCESS Success\r
1821 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1822 \r
1823--*/\r
1824;\r
1825\r
1826EFI_STATUS\r
1827CreateAltQtd (\r
1828 IN USB2_HC_DEV *HcDev,\r
1829 IN UINT8 PktId,\r
1830 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1831 )\r
1832/*++\r
1833\r
1834Routine Description:\r
1835\r
1836 Create Qtd Structure for Alternative \r
1837\r
1838Arguments:\r
1839\r
1840 HcDev - USB2_HC_DEV \r
1841 PktId - Packet Identification of this Qtd\r
1842 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1843 \r
1844Returns:\r
1845\r
1846 EFI_SUCCESS Success\r
1847 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1848 \r
1849--*/\r
1850;\r
1851\r
1852EFI_STATUS\r
1853CreateControlQtds (\r
1854 IN USB2_HC_DEV *HcDev,\r
1855 IN UINT8 DataPktId,\r
1856 IN UINT8 *RequestCursor,\r
1857 IN UINT8 *DataCursor,\r
1858 IN UINTN DataLen,\r
1859 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1860 OUT EHCI_QTD_ENTITY **ControlQtdsHead\r
1861 )\r
1862/*++\r
1863\r
1864Routine Description:\r
1865\r
1866 Create Qtds list for Control Transfer \r
1867\r
1868Arguments:\r
1869\r
1870 HcDev - USB2_HC_DEV \r
1871 DataPktId - Packet Identification of Data Qtds\r
1872 RequestCursor - A pointer to request structure buffer to transfer\r
1873 DataCursor - A pointer to user data buffer to transfer\r
1874 DataLen - Length of user data to transfer\r
1875 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1876 \r
1877Returns:\r
1878\r
1879 EFI_SUCCESS Success\r
1880 EFI_DEVICE_ERROR Fail\r
1881 \r
1882--*/\r
1883;\r
1884\r
1885EFI_STATUS\r
1886CreateBulkOrInterruptQtds (\r
1887 IN USB2_HC_DEV *HcDev,\r
1888 IN UINT8 PktId,\r
1889 IN UINT8 *DataCursor,\r
1890 IN UINTN DataLen,\r
1891 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1892 OUT EHCI_QTD_ENTITY **QtdsHead\r
1893 )\r
1894/*++\r
1895\r
1896Routine Description:\r
1897\r
1898 Create Qtds list for Bulk or Interrupt Transfer \r
1899\r
1900Arguments:\r
1901\r
1902 HcDev - USB2_HC_DEV \r
1903 PktId - Packet Identification of Qtds\r
1904 DataCursor - A pointer to user data buffer to transfer\r
1905 DataLen - Length of user data to transfer\r
1906 DataToggle - Data Toggle to start\r
1907 Translator - Translator Transaction for SplitX\r
1908 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1909 \r
1910Returns:\r
1911\r
1912 EFI_SUCCESS Success\r
1913 EFI_DEVICE_ERROR Fail\r
1914 \r
1915--*/\r
1916;\r
1917\r
1918VOID\r
1919DestoryQtds (\r
1920 IN USB2_HC_DEV *HcDev,\r
1921 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
1922 )\r
1923/*++\r
1924\r
1925Routine Description:\r
1926\r
1927 Destory all Qtds in the list\r
1928\r
1929Arguments:\r
1930\r
1931 HcDev - USB2_HC_DEV \r
1932 FirstQtdPtr - A pointer to first Qtd in the list \r
1933 \r
1934Returns:\r
1935\r
1936 VOID\r
1937\r
1938--*/\r
1939;\r
1940\r
1941VOID\r
1942LinkQtdToQtd (\r
1943 IN EHCI_QTD_ENTITY *PreQtdPtr,\r
1944 IN EHCI_QTD_ENTITY *QtdPtr\r
1945 )\r
1946/*++\r
1947\r
1948Routine Description:\r
1949\r
1950 Link Qtds together\r
1951 \r
1952Arguments:\r
1953\r
1954 PreQtdPtr - A pointer to pre Qtd\r
1955 QtdPtr - A pointer to next Qtd\r
1956 \r
1957Returns:\r
1958\r
1959 VOID\r
1960\r
1961--*/\r
1962;\r
1963\r
1964VOID\r
1965LinkQtdsToAltQtd (\r
1966 IN EHCI_QTD_ENTITY *FirstQtdPtr,\r
1967 IN EHCI_QTD_ENTITY *AltQtdPtr\r
1968 )\r
1969/*++\r
1970\r
1971Routine Description:\r
1972\r
1973 Link AlterQtds together\r
1974 \r
1975Arguments:\r
1976\r
1977 FirstQtdPtr - A pointer to first Qtd in the list\r
1978 AltQtdPtr - A pointer to alternative Qtd\r
1979 \r
1980Returns:\r
1981 VOID\r
1982\r
1983--*/\r
1984;\r
1985\r
1986VOID\r
1987LinkQtdToQh (\r
1988 IN EHCI_QH_ENTITY *QhPtr,\r
1989 IN EHCI_QTD_ENTITY *QtdEntryPtr\r
1990 )\r
1991/*++\r
1992\r
1993Routine Description:\r
1994\r
1995 Link Qtds list to Qh\r
1996 \r
1997Arguments:\r
1998\r
1999 QhPtr - A pointer to Qh\r
2000 QtdPtr - A pointer to first Qtd in the list\r
2001 \r
2002Returns:\r
2003\r
2004 VOID\r
2005\r
2006--*/\r
2007;\r
2008\r
2009EFI_STATUS\r
2010LinkQhToAsyncList (\r
2011 IN USB2_HC_DEV *HcDev,\r
2012 IN EHCI_QH_ENTITY *QhPtr\r
2013 )\r
2014/*++\r
2015\r
2016Routine Description:\r
2017\r
2018 Link Qh to Async Schedule List\r
2019 \r
2020Arguments:\r
2021\r
2022 HcDev - USB2_HC_DEV \r
2023 QhPtr - A pointer to Qh\r
2024 \r
2025Returns:\r
2026\r
2027 EFI_SUCCESS Success\r
2028 EFI_DEVICE_ERROR Fail\r
2029 \r
2030--*/\r
2031;\r
2032\r
2033EFI_STATUS\r
2034UnlinkQhFromAsyncList (\r
2035 IN USB2_HC_DEV *HcDev,\r
2036 IN EHCI_QH_ENTITY *QhPtr\r
2037 )\r
2038/*++\r
2039\r
2040Routine Description:\r
2041\r
2042 Unlink Qh from Async Schedule List\r
2043 \r
2044Arguments:\r
2045\r
2046 HcDev - USB2_HC_DEV \r
2047 QhPtr - A pointer to Qh\r
2048 \r
2049Returns:\r
2050\r
2051 EFI_SUCCESS Success\r
2052 EFI_DEVICE_ERROR Fail\r
2053 \r
2054--*/\r
2055;\r
2056\r
2057VOID\r
2058LinkQhToPeriodicList (\r
2059 IN USB2_HC_DEV *HcDev,\r
2060 IN EHCI_QH_ENTITY *QhPtr\r
2061 )\r
2062/*++\r
2063\r
2064Routine Description:\r
2065\r
2066 Link Qh to Periodic Schedule List\r
2067 \r
2068Arguments:\r
2069\r
2070 HcDev - USB2_HC_DEV \r
2071 QhPtr - A pointer to Qh\r
2072 \r
2073Returns:\r
2074\r
2075 VOID\r
2076\r
2077--*/\r
2078;\r
2079\r
2080VOID\r
2081UnlinkQhFromPeriodicList (\r
2082 IN USB2_HC_DEV *HcDev,\r
2083 IN EHCI_QH_ENTITY *QhPtr,\r
2084 IN UINTN Interval\r
2085 )\r
2086/*++\r
2087\r
2088Routine Description:\r
2089\r
2090 Unlink Qh from Periodic Schedule List\r
2091 \r
2092Arguments:\r
2093\r
2094 HcDev - USB2_HC_DEV \r
2095 QhPtr - A pointer to Qh\r
2096 Interval - Interval of this periodic transfer\r
2097 \r
2098Returns:\r
2099\r
2100 VOID\r
2101 \r
2102--*/\r
2103;\r
2104\r
2105VOID\r
2106LinkToAsyncReqeust (\r
2107 IN USB2_HC_DEV *HcDev,\r
2108 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2109 )\r
2110/*++\r
2111\r
2112Routine Description:\r
2113\r
2114 Llink AsyncRequest Entry to Async Request List\r
2115 \r
2116Arguments:\r
2117\r
2118 HcDev - USB2_HC_DEV \r
2119 AsyncRequestPtr - A pointer to Async Request Entry\r
2120 \r
2121Returns:\r
2122\r
2123 VOID\r
2124 \r
2125--*/\r
2126;\r
2127\r
2128VOID\r
2129UnlinkFromAsyncReqeust (\r
2130 IN USB2_HC_DEV *HcDev,\r
2131 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2132 )\r
2133/*++\r
2134\r
2135Routine Description:\r
2136\r
2137 Unlink AsyncRequest Entry from Async Request List\r
2138 \r
2139Arguments:\r
2140\r
2141 HcDev - USB2_HC_DEV \r
2142 AsyncRequestPtr - A pointer to Async Request Entry\r
2143 \r
2144Returns:\r
2145\r
2146 VOID\r
2147 \r
2148--*/\r
2149;\r
2150\r
2151UINTN\r
2152GetNumberOfQtd (\r
2153 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2154 )\r
2155/*++\r
2156\r
2157Routine Description:\r
2158\r
2159 Number of Qtds in the list\r
2160 \r
2161Arguments:\r
2162\r
2163 FirstQtdPtr - A pointer to first Qtd in the list\r
2164 \r
2165Returns:\r
2166\r
2167 Number of Qtds in the list\r
2168\r
2169--*/\r
2170;\r
2171\r
2172UINTN\r
2173GetNumberOfTransaction (\r
2174 IN UINTN SizeOfData,\r
2175 IN UINTN SizeOfTransaction\r
2176 )\r
2177/*++\r
2178\r
2179Routine Description:\r
2180\r
2181 Number of Transactions in one Qtd\r
2182 \r
2183Arguments:\r
2184\r
2185 SizeOfData - Size of one Qtd\r
2186 SizeOfTransaction - Size of one Transaction\r
2187 \r
2188Returns:\r
2189\r
2190 Number of Transactions in this Qtd\r
2191\r
2192--*/\r
2193;\r
2194\r
2195UINTN\r
2196GetCapacityOfQtd (\r
2197 IN UINT8 *BufferCursor\r
2198 )\r
2199/*++\r
2200\r
2201Routine Description:\r
2202\r
2203 Get Capacity of Qtd\r
2204 \r
2205Arguments:\r
2206\r
2207 BufferCursor - BufferCursor of the Qtd\r
2208 \r
2209Returns:\r
2210\r
2211 Capacity of Qtd\r
2212\r
2213--*/\r
2214;\r
2215\r
2216UINTN\r
2217GetApproxiOfInterval (\r
2218 IN UINTN Interval\r
2219 )\r
2220/*++\r
2221\r
2222Routine Description:\r
2223\r
2224 Get the approximate value in the 2 index sequence\r
2225 \r
2226Arguments:\r
2227\r
2228 Interval - the value of interval\r
2229 \r
2230Returns:\r
2231\r
2232 approximate value of interval in the 2 index sequence\r
2233 \r
2234--*/\r
2235;\r
2236\r
2237EHCI_QTD_HW *\r
2238GetQtdNextPointer (\r
2239 IN EHCI_QTD_HW *HwQtdPtr\r
2240 )\r
2241/*++\r
2242\r
2243Routine Description:\r
2244\r
2245 Get Qtd next pointer field\r
2246 \r
2247Arguments:\r
2248\r
2249 HwQtdPtr - A pointer to hardware Qtd structure\r
2250 \r
2251Returns:\r
2252\r
2253 A pointer to next hardware Qtd structure\r
2254 \r
2255--*/\r
2256;\r
2257\r
2258BOOLEAN\r
2259IsQtdStatusActive (\r
2260 IN EHCI_QTD_HW *HwQtdPtr\r
2261 )\r
2262/*++\r
2263\r
2264Routine Description:\r
2265\r
2266 Whether Qtd status is active or not\r
2267 \r
2268Arguments:\r
2269\r
2270 HwQtdPtr - A pointer to hardware Qtd structure\r
2271 \r
2272Returns:\r
2273\r
2274 TRUE Active\r
2275 FALSE Inactive\r
2276 \r
2277--*/\r
2278;\r
2279\r
2280BOOLEAN\r
2281IsQtdStatusHalted (\r
2282 IN EHCI_QTD_HW *HwQtdPtr\r
2283 )\r
2284/*++\r
2285\r
2286Routine Description:\r
2287\r
2288 Whether Qtd status is halted or not\r
2289 \r
2290Arguments:\r
2291\r
2292 HwQtdPtr - A pointer to hardware Qtd structure\r
2293 \r
2294Returns:\r\r
2295\r
2296 TRUE Halted\r
2297 FALSE Not halted\r
2298 \r
2299--*/\r
2300;\r
2301\r
2302BOOLEAN\r
2303IsQtdStatusBufferError (\r
2304 IN EHCI_QTD_HW *HwQtdPtr\r
2305 )\r
2306/*++\r
2307\r
2308Routine Description:\r
2309\r
2310 Whether Qtd status is buffer error or not\r
2311 \r
2312Arguments:\r
2313\r
2314 HwQtdPtr - A pointer to hardware Qtd structure\r
2315 \r
2316Returns:\r
2317\r
2318 TRUE Buffer error\r
2319 FALSE No buffer error\r
2320 \r
2321--*/\r
2322;\r
2323\r
2324BOOLEAN\r
2325IsQtdStatusBabbleError (\r
2326 IN EHCI_QTD_HW *HwQtdPtr\r
2327 )\r
2328/*++\r
2329\r
2330Routine Description:\r
2331\r
2332 Whether Qtd status is babble error or not\r
2333 \r
2334Arguments:\r
2335\r
2336 HwQtdPtr - A pointer to hardware Qtd structure\r
2337 \r
2338Returns:\r
2339\r
2340 TRUE Babble error\r
2341 FALSE No babble error\r
2342 \r
2343--*/\r
2344;\r
2345\r
2346BOOLEAN\r
2347IsQtdStatusTransactionError (\r
2348 IN EHCI_QTD_HW *HwQtdPtr\r
2349 )\r
2350/*++\r
2351\r
2352Routine Description:\r
2353\r
2354 Whether Qtd status is transaction error or not\r
2355 \r
2356Arguments:\r
2357\r
2358 HwQtdPtr - A pointer to hardware Qtd structure\r
2359 \r
2360Returns:\r
2361\r
2362 TRUE Transaction error\r
2363 FALSE No transaction error\r
2364 \r
2365--*/\r
2366;\r
2367\r
2368BOOLEAN\r
2369IsDataInTransfer (\r
2370 IN UINT8 EndPointAddress\r
2371 )\r
2372/*++\r
2373\r
2374Routine Description:\r
2375\r
2376 Whether is a DataIn direction transfer\r
2377 \r
2378Arguments:\r
2379\r
2380 EndPointAddress - address of the endpoint \r
2381 \r
2382Returns:\r
2383\r
2384 TRUE DataIn\r
2385 FALSE DataOut\r
2386 \r
2387--*/\r
2388;\r
2389\r
2390EFI_STATUS\r
2391MapDataBuffer (\r
2392 IN USB2_HC_DEV *HcDev,\r
2393 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
2394 IN OUT VOID *Data,\r
2395 IN OUT UINTN *DataLength,\r
2396 OUT UINT8 *PktId,\r
2397 OUT UINT8 **DataCursor,\r
2398 OUT VOID **DataMap\r
2399 )\r
2400/*++\r
2401\r
2402Routine Description:\r
2403\r
2404 Map address of user data buffer\r
2405 \r
2406Arguments:\r
2407\r
2408 HcDev - USB2_HC_DEV \r
2409 TransferDirection - direction of transfer\r
2410 Data - A pointer to user data buffer \r
2411 DataLength - length of user data\r
2412 PktId - Packte Identificaion\r
2413 DataCursor - mapped address to return\r
2414 DataMap - identificaion of this mapping to return\r
2415 \r
2416Returns:\r
2417\r
2418 EFI_SUCCESS Success\r
2419 EFI_DEVICE_ERROR Fail\r
2420 \r
2421--*/\r
2422;\r
2423\r
2424EFI_STATUS\r
2425MapRequestBuffer (\r
2426 IN USB2_HC_DEV *HcDev,\r
2427 IN OUT VOID *Request,\r
2428 OUT UINT8 **RequestCursor,\r
2429 OUT VOID **RequestMap\r
2430 )\r
2431/*++\r
2432\r
2433Routine Description:\r
2434\r
2435 Map address of request structure buffer\r
2436 \r
2437Arguments:\r
2438\r
2439 HcDev - USB2_HC_DEV \r
2440 Request - A pointer to request structure\r
2441 RequestCursor - Mapped address of request structure to return\r
2442 RequestMap - Identificaion of this mapping to return\r
2443 \r
2444Returns:\r
2445\r
2446 EFI_SUCCESS Success\r
2447 EFI_DEVICE_ERROR Fail\r
2448 \r
2449--*/\r
2450;\r
2451\r
2452VOID\r
2453SetQtdBufferPointer (\r
2454 IN EHCI_QTD_HW *QtdHwPtr,\r
2455 IN VOID *DataPtr,\r
2456 IN UINTN DataLen\r
2457 )\r
2458/*++\r
2459\r
2460Routine Description:\r
2461\r
2462 Set data buffer pointers in Qtd\r
2463\r
2464Arguments:\r
2465\r
2466 QtdHwPtr - A pointer to Qtd hardware structure \r
2467 DataPtr - A pointer to user data buffer\r
2468 DataLen - Length of the user data buffer\r
2469 \r
2470Returns:\r
2471\r
2472 VOID\r
2473\r
2474--*/\r
2475;\r
2476\r
2477EHCI_QTD_HW *\r
2478GetQtdAlternateNextPointer (\r
2479 IN EHCI_QTD_HW *HwQtdPtr\r
2480 )\r
2481/*++\r
2482\r
2483Routine Description:\r
2484\r
2485 Get Qtd alternate next pointer field\r
2486 \r
2487Arguments:\r
2488\r
2489 HwQtdPtr - A pointer to hardware Qtd structure\r
2490 \r
2491Returns:\r
2492\r
2493 A pointer to hardware alternate Qtd\r
2494 \r
2495--*/\r
2496;\r
2497\r
2498VOID\r
2499ZeroOutQhOverlay (\r
2500 IN EHCI_QH_ENTITY *QhPtr\r
2501 )\r
2502/*++\r
2503\r
2504Routine Description:\r
2505\r
2506 Zero out the fields in Qh structure\r
2507 \r
2508Arguments:\r
2509\r
2510 QhPtr - A pointer to Qh structure\r
2511 \r
2512Returns:\r
2513\r
2514 VOID\r
2515 \r
2516--*/\r
2517;\r
2518\r
2519VOID\r
2520UpdateAsyncRequestTransfer (\r
2521 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,\r
2522 IN UINT32 TransferResult,\r
2523 IN UINTN ErrTDPos\r
2524 )\r
2525/*++\r
2526\r
2527Routine Description:\r
2528\r
2529 Update asynchronous request transfer\r
2530 \r
2531Arguments:\r
2532\r
2533 AsyncRequestPtr - A pointer to async request \r
2534 TransferResult - transfer result \r
2535 ErrQtdPos - postion of error Qtd\r
2536 \r
2537Returns:\r
2538\r
2539 VOID\r
2540 \r
2541--*/\r
2542;\r
2543\r
2544\r
2545EFI_STATUS\r
2546DeleteAsyncRequestTransfer (\r
2547 IN USB2_HC_DEV *HcDev,\r
2548 IN UINT8 DeviceAddress,\r
2549 IN UINT8 EndPointAddress,\r
2550 OUT UINT8 *DataToggle\r
2551 )\r
2552/*++\r
2553\r
2554Routine Description:\r
2555\r
2556 Delete all asynchronous request transfer\r
2557 \r
2558Arguments:\r
2559\r
2560 HcDev - USB2_HC_DEV \r
2561 DeviceAddress - address of usb device\r
2562 EndPointAddress - address of endpoint\r
2563 DataToggle - stored data toggle\r
2564 \r
2565Returns:\r
2566\r
2567 EFI_SUCCESS Success\r
2568 EFI_DEVICE_ERROR Fail\r
2569\r
2570--*/\r
2571;\r
2572\r
2573VOID\r
2574CleanUpAllAsyncRequestTransfer (\r
2575 IN USB2_HC_DEV *HcDev\r
2576 )\r
2577/*++\r
2578\r
2579Routine Description:\r
2580\r
2581 Clean up all asynchronous request transfer\r
2582 \r
2583Arguments:\r
2584\r
2585 HcDev - USB2_HC_DEV \r
2586 \r
2587Returns:\r
2588 VOID\r
2589 \r
2590--*/\r
2591;\r
2592\r
2593EFI_STATUS\r
2594ExecuteTransfer (\r
2595 IN USB2_HC_DEV *HcDev,\r
2596 IN BOOLEAN IsControl,\r
2597 IN EHCI_QH_ENTITY *QhPtr,\r
2598 IN OUT UINTN *ActualLen,\r
2599 OUT UINT8 *DataToggle,\r
2600 IN UINTN TimeOut,\r
2601 OUT UINT32 *TransferResult\r
2602 )\r
2603/*++\r
2604\r
2605Routine Description:\r
2606\r
2607 Execute Bulk or SyncInterrupt Transfer\r
2608\r
2609Arguments:\r
2610\r
2611 HcDev - USB2_HC_DEV\r
2612 IsControl - Is control transfer or not\r
2613 QhPtr - A pointer to Qh\r
2614 ActualLen - Actual transfered Len \r
2615 DataToggle - Data Toggle\r
2616 TimeOut - TimeOut threshold\r
2617 TransferResult - Transfer result\r
2618 \r
2619Returns:\r
2620\r
2621 EFI_SUCCESS Sucess\r
2622 EFI_DEVICE_ERROR Error\r
2623 \r
2624--*/\r
2625;\r
2626\r
2627BOOLEAN\r
2628CheckQtdsTransferResult (\r
2629 IN BOOLEAN IsControl,\r
2630 IN EHCI_QH_ENTITY *QhPtr,\r
2631 OUT UINT32 *Result,\r
2632 OUT UINTN *ErrQtdPos,\r
2633 OUT UINTN *ActualLen\r
2634 )\r
2635/*++\r
2636\r
2637Routine Description:\r
2638\r
2639 Check transfer result of Qtds\r
2640\r
2641Arguments:\r
2642\r
2643 IsControl - Is control transfer or not\r
2644 QhPtr - A pointer to Qh\r
2645 Result - Transfer result\r
2646 ErrQtdPos - Error TD Position\r
2647 ActualLen - Actual Transfer Size\r
2648\r
2649Returns:\r
2650\r
2651 TRUE Qtds finished\r
2652 FALSE Not finish\r
2653 \r
2654--*/\r
2655;\r
2656\r
2657EFI_STATUS\r
2658AsyncRequestMoniter (\r
2659 IN EFI_EVENT Event,\r
2660 IN VOID *Context\r
2661 )\r
2662/*++\r
2663\r
2664Routine Description:\r
2665 \r
2666 Interrupt transfer periodic check handler\r
2667 \r
2668Arguments:\r
2669\r
2670 Event - Interrupt event\r
2671 Context - Pointer to USB2_HC_DEV\r
2672 \r
2673Returns:\r
2674 \r
2675 EFI_SUCCESS Success\r
2676 EFI_DEVICE_ERROR Fail\r
2677 \r
2678--*/\r
2679;\r
2680\r
2681#endif\r