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562d2849 1/*++\r
2\r
3Copyright (c) 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 Ehci.h\r
15 \r
16Abstract: \r
17 \r
18\r
19Revision History\r
20--*/\r
21\r
22#ifndef _EHCI_H\r
23#define _EHCI_H\r
24\r
25//\r
26// Universal Host Controller Interface data structures and defines\r
27//\r
28#include <IndustryStandard/pci22.h>\r
29\r
562d2849 30extern UINTN gEHCDebugLevel;\r
31extern UINTN gEHCErrorLevel;\r
562d2849 32\r
33#define STALL_1_MACRO_SECOND 1\r
34#define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND\r
35#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r
36\r
37#define SETUP_PACKET_PID_CODE 0x02\r
38#define INPUT_PACKET_PID_CODE 0x01\r
39#define OUTPUT_PACKET_PID_CODE 0x0\r
40\r
41#define ITD_SELECT_TYPE 0x0\r
42#define QH_SELECT_TYPE 0x01\r
43#define SITD_SELECT_TYPE 0x02\r
44#define FSTN_SELECT_TYPE 0x03\r
45\r
46#define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND\r
47#define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND\r
48#define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND\r
49#define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND\r
50#define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND\r
51#define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND\r
52\r
53#define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */\r
54\r
55#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1\r
56\r
57#define EHCI_MIN_PACKET_SIZE 8\r
58#define EHCI_MAX_PACKET_SIZE 1024\r
59#define EHCI_MAX_FRAME_LIST_LENGTH 1024\r
60#define EHCI_BLOCK_SIZE_WITH_TT 64\r
61#define EHCI_BLOCK_SIZE 512\r
62#define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)\r
63\r
64#define NAK_COUNT_RELOAD 3\r
65#define QTD_ERROR_COUNTER 1\r
66#define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1\r
67\r
68#define QTD_STATUS_ACTIVE 0x80\r
69#define QTD_STATUS_HALTED 0x40\r
70#define QTD_STATUS_BUFFER_ERR 0x20\r
71#define QTD_STATUS_BABBLE_ERR 0x10\r
72#define QTD_STATUS_TRANSACTION_ERR 0x08\r
73#define QTD_STATUS_DO_STOP_SPLIT 0x02\r
74#define QTD_STATUS_DO_START_SPLIT 0\r
75#define QTD_STATUS_DO_PING 0x01\r
76#define QTD_STATUS_DO_OUT 0\r
77\r
78#define DATA0 0\r
79#define DATA1 1\r
80\r
81#define MICRO_FRAME_0_CHANNEL 0x01\r
82#define MICRO_FRAME_1_CHANNEL 0x02\r
83#define MICRO_FRAME_2_CHANNEL 0x04\r
84#define MICRO_FRAME_3_CHANNEL 0x08\r
85#define MICRO_FRAME_4_CHANNEL 0x10\r
86#define MICRO_FRAME_5_CHANNEL 0x20\r
87#define MICRO_FRAME_6_CHANNEL 0x40\r
88#define MICRO_FRAME_7_CHANNEL 0x80\r
89\r
90#define CONTROL_TRANSFER 0x01\r
91#define BULK_TRANSFER 0x02\r
92#define SYNC_INTERRUPT_TRANSFER 0x04\r
93#define ASYNC_INTERRUPT_TRANSFER 0x08\r
94#define SYNC_ISOCHRONOUS_TRANSFER 0x10\r
95#define ASYNC_ISOCHRONOUS_TRANSFER 0x20\r
96\r
97\r
98//\r
99// Enhanced Host Controller Registers definitions\r
100//\r
101extern UINT32 mUsbCapabilityLen;\r
102extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
103extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
104\r
105#define USBCMD 0x0 /* Command Register Offset 00-03h */\r
106#define USBCMD_RS 0x01 /* Run / Stop */\r
107#define USBCMD_HCRESET 0x02 /* Host controller reset */\r
108#define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */\r
109#define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */\r
110#define USBCMD_PSE 0x10 /* Periodic schedule enable */\r
111#define USBCMD_ASE 0x20 /* Asynchronous schedule enable */\r
112#define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */\r
113\r
114#define USBSTS 0x04 /* Statue Register Offset 04-07h */\r
115#define USBSTS_HSE 0x10 /* Host system error */\r
116#define USBSTS_IAA 0x20 /* Interrupt on async advance */\r
117#define USBSTS_HCH 0x1000 /* Host controller halted */\r
118#define USBSTS_PSS 0x4000 /* Periodic schedule status */\r
119#define USBSTS_ASS 0x8000 /* Asynchronous schedule status */\r
120\r
121#define USBINTR 0x08 /* Command Register Offset 08-0bh */\r
122\r
123#define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */\r
124\r
125#define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */\r
126\r
127#define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */\r
128\r
129#define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */\r
130\r
131#define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */\r
132#define CONFIGFLAG_CF 0x01 /* Configure Flag */\r
133\r
134#define PORTSC 0x44 /* Port Status/Control Offset 44-47h */\r
135#define PORTSC_CCS 0x01 /* Current Connect Status*/\r
136#define PORTSC_CSC 0x02 /* Connect Status Change */\r
137#define PORTSC_PED 0x04 /* Port Enable / Disable */\r
138#define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */\r
139#define PORTSC_OCA 0x10 /* Over current Active */\r
140#define PORTSC_OCC 0x20 /* Over current Change */\r
141#define PORTSC_FPR 0x40 /* Force Port Resume */\r
142#define PORTSC_SUSP 0x80 /* Port Suspend State */\r
143#define PORTSC_PR 0x100 /* Port Reset */\r
144#define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */\r
145#define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */\r
146#define PORTSC_PP 0x1000 /* Port Power */\r
147#define PORTSC_PO 0x2000 /* Port Owner */\r
148\r
149#define CAPLENGTH 0 /* Capability Register Length 00h */\r
150\r
151#define HCIVERSION 0x02 /* Interface Version Number 02-03h */\r
152\r
153#define HCSPARAMS 0x04 /* Structural Parameters 04-07h */\r
154#define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */\r
155\r
156#define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */\r
157#define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */\r
158#define HCCP_PFLF 0x02 /* Programmable Frame List Flag */\r
159#define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */\r
160\r
161#define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */\r
162\r
163#define CLASSC 0x09 /* Class Code 09-0bh */\r
164\r
165#define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */\r
166\r
167#define SBRN 0x60 /* Serial Bus Release Number 60h */\r
168\r
169#define FLADJ 0x61 /* Frame Length Adjustment Register 61h */\r
170\r
171#define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */\r
172\r
173//\r
174// PCI Configuration Registers\r
175//\r
176#define EHCI_PCI_CLASSC 0x09\r
177#define EHCI_PCI_MEMORY_BASE 0x10\r
178\r
179//\r
180// Memory Offset Registers\r
181//\r
182#define EHCI_MEMORY_CAPLENGTH 0x0\r
183#define EHCI_MEMORY_CONFIGFLAG 0x40\r
184\r
185//\r
186// USB Base Class Code,Sub-Class Code and Programming Interface\r
187//\r
188#define PCI_CLASSC_PI_EHCI 0x20\r
189\r
190#define SETUP_PACKET_ID 0x2D\r
191#define INPUT_PACKET_ID 0x69\r
192#define OUTPUT_PACKET_ID 0xE1\r
193#define ERROR_PACKET_ID 0x55\r
194\r
195#define bit(a) 1 << (a)\r
196\r
197#define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))\r
198#define GET_32B_TO_63B(Addr) ((((UINTN) Addr) >> 32) & (0xffffffff))\r
199\r
200\r
201//\r
202// Ehci Data and Ctrl Structures\r
203//\r
204#pragma pack(1)\r
205\r
206typedef struct {\r
207 UINT8 PI;\r
208 UINT8 SubClassCode;\r
209 UINT8 BaseCode;\r
210} USB_CLASSC;\r
211\r
212typedef struct {\r
213 UINT32 NextQtdTerminate : 1;\r
214 UINT32 Rsvd1 : 4;\r
215 UINT32 NextQtdPointer : 27;\r
216\r
217 UINT32 AltNextQtdTerminate : 1;\r
218 UINT32 Rsvd2 : 4;\r
219 UINT32 AltNextQtdPointer : 27;\r
220\r
221 UINT32 Status : 8;\r
222 UINT32 PidCode : 2;\r
223 UINT32 ErrorCount : 2;\r
224 UINT32 CurrentPage : 3;\r
225 UINT32 InterruptOnComplete : 1;\r
226 UINT32 TotalBytes : 15;\r
227 UINT32 DataToggle : 1;\r
228\r
229 UINT32 CurrentOffset : 12;\r
230 UINT32 BufferPointer0 : 20;\r
231\r
232 UINT32 Rsvd3 : 12;\r
233 UINT32 BufferPointer1 : 20;\r
234\r
235 UINT32 Rsvd4 : 12;\r
236 UINT32 BufferPointer2 : 20;\r
237\r
238 UINT32 Rsvd5 : 12;\r
239 UINT32 BufferPointer3 : 20;\r
240\r
241 UINT32 Rsvd6 : 12;\r
242 UINT32 BufferPointer4 : 20;\r
243\r
244 UINT32 ExtBufferPointer0;\r
245 UINT32 ExtBufferPointer1;\r
246 UINT32 ExtBufferPointer2;\r
247 UINT32 ExtBufferPointer3;\r
248 UINT32 ExtBufferPointer4;\r
249} EHCI_QTD_HW;\r
250\r
251typedef struct {\r
252 UINT32 QhTerminate : 1;\r
253 UINT32 SelectType : 2;\r
254 UINT32 Rsvd1 : 2;\r
255 UINT32 QhHorizontalPointer : 27;\r
256\r
257 UINT32 DeviceAddr : 7;\r
258 UINT32 Inactive : 1;\r
259 UINT32 EndpointNum : 4;\r
260 UINT32 EndpointSpeed : 2;\r
261 UINT32 DataToggleControl : 1;\r
262 UINT32 HeadReclamationFlag : 1;\r
263 UINT32 MaxPacketLen : 11;\r
264 UINT32 ControlEndpointFlag : 1;\r
265 UINT32 NakCountReload : 4;\r
266\r
267 UINT32 InerruptScheduleMask : 8;\r
268 UINT32 SplitComletionMask : 8;\r
269 UINT32 HubAddr : 7;\r
270 UINT32 PortNum : 7;\r
271 UINT32 Multiplier : 2;\r
272\r
273 UINT32 Rsvd2 : 5;\r
274 UINT32 CurrentQtdPointer : 27;\r
275\r
276 UINT32 NextQtdTerminate : 1;\r
277 UINT32 Rsvd3 : 4;\r
278 UINT32 NextQtdPointer : 27;\r
279\r
280 UINT32 AltNextQtdTerminate : 1;\r
281 UINT32 NakCount : 4;\r
282 UINT32 AltNextQtdPointer : 27;\r
283\r
284 UINT32 Status : 8;\r
285 UINT32 PidCode : 2;\r
286 UINT32 ErrorCount : 2;\r
287 UINT32 CurrentPage : 3;\r
288 UINT32 InterruptOnComplete : 1;\r
289 UINT32 TotalBytes : 15;\r
290 UINT32 DataToggle : 1;\r
291\r
292 UINT32 CurrentOffset : 12;\r
293 UINT32 BufferPointer0 : 20;\r
294\r
295 UINT32 CompleteSplitMask : 8;\r
296 UINT32 Rsvd4 : 4;\r
297 UINT32 BufferPointer1 : 20;\r
298\r
299 UINT32 FrameTag : 5;\r
300 UINT32 SplitBytes : 7;\r
301 UINT32 BufferPointer2 : 20;\r
302\r
303 UINT32 Rsvd5 : 12;\r
304 UINT32 BufferPointer3 : 20;\r
305\r
306 UINT32 Rsvd6 : 12;\r
307 UINT32 BufferPointer4 : 20;\r
308\r
309 UINT32 ExtBufferPointer0;\r
310 UINT32 ExtBufferPointer1;\r
311 UINT32 ExtBufferPointer2;\r
312 UINT32 ExtBufferPointer3;\r
313 UINT32 ExtBufferPointer4;\r
314} EHCI_QH_HW;\r
315\r
316typedef struct {\r
317 UINT32 LinkTerminate : 1;\r
318 UINT32 SelectType : 2;\r
319 UINT32 Rsvd : 2;\r
320 UINT32 LinkPointer : 27;\r
321} FRAME_LIST_ENTRY;\r
322\r
323#pragma pack()\r
324\r
325typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;\r
326typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;\r
327typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;\r
328\r
329typedef struct _EHCI_QTD_ENTITY {\r
330 EHCI_QTD_HW Qtd;\r
331 UINT32 TotalBytes;\r
332 UINT32 StaticTotalBytes;\r
333 UINT32 StaticCurrentOffset;\r
334 EHCI_QTD_ENTITY *Prev;\r
335 EHCI_QTD_ENTITY *Next;\r
336 EHCI_QTD_ENTITY *AltNext;\r
337 EHCI_QH_ENTITY *SelfQh;\r
338} EHCI_QTD_ENTITY;\r
339\r
340typedef struct _EHCI_QH_ENTITY {\r
341 EHCI_QH_HW Qh;\r
342 EHCI_QH_ENTITY *Next;\r
343 EHCI_QH_ENTITY *Prev;\r
344 EHCI_QTD_ENTITY *FirstQtdPtr;\r
345 EHCI_QTD_ENTITY *LastQtdPtr;\r
346 EHCI_QTD_ENTITY *AltQtdPtr;\r
347 UINTN Interval;\r
348 UINT8 TransferType;\r
349} EHCI_QH_ENTITY;\r
350\r
351#define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)\r
352#define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)\r
353\r
354\r
355//\r
356// Ehci Managment Structures\r
357//\r
358#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
359\r
360#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
361\r
362typedef struct _LIST_HEAD {\r
363 struct _LIST_HEAD *pre;\r
364 struct _LIST_HEAD *next;\r
365} LIST_HEAD;\r
366\r
367typedef struct _EHCI_ASYNC_REQUEST {\r
368 UINT8 TransferType;\r
369 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;\r
370 VOID *Context;\r
371 EHCI_ASYNC_REQUEST *Prev;\r
372 EHCI_ASYNC_REQUEST *Next;\r
373 EHCI_QH_ENTITY *QhPtr;\r
374} EHCI_ASYNC_REQUEST;\r
375\r
376typedef struct _MEMORY_MANAGE_HEADER {\r
377 UINT8 *BitArrayPtr;\r
378 UINTN BitArraySizeInBytes;\r
379 UINT8 *MemoryBlockPtr;\r
380 UINTN MemoryBlockSizeInBytes;\r
381 VOID *Mapping;\r
382 struct _MEMORY_MANAGE_HEADER *Next;\r
383} MEMORY_MANAGE_HEADER;\r
384\r
385typedef struct _USB2_HC_DEV {\r
386 UINTN Signature;\r
387 EFI_PCI_IO_PROTOCOL *PciIo;\r
388 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
389 UINTN PeriodicFrameListLength;\r
390 VOID *PeriodicFrameListBuffer;\r
391 VOID *PeriodicFrameListMap;\r
392 VOID *AsyncList;\r
393 EHCI_ASYNC_REQUEST *AsyncRequestList;\r
394 EFI_EVENT AsyncRequestEvent;\r
395 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
396 MEMORY_MANAGE_HEADER *MemoryHeader;\r
397 UINT8 Is64BitCapable;\r
398 UINT32 High32BitAddr;\r
399} USB2_HC_DEV;\r
400\r
401\r
402//\r
403// Internal Functions Declaration\r
404//\r
405\r
406//\r
407// EhciMem Functions\r
408//\r
409EFI_STATUS\r
410CreateMemoryBlock (\r
411 IN USB2_HC_DEV *HcDev,\r
412 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
413 IN UINTN MemoryBlockSizeInPages\r
414 )\r
415/*++\r
416\r
417Routine Description:\r
418\r
419 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,\r
420 and use PciIo->Map to map the common buffer for Bus Master Read/Write.\r
421\r
422Arguments:\r
423\r
424 HcDev - USB2_HC_DEV\r
425 MemoryHeader - MEMORY_MANAGE_HEADER to output\r
426 MemoryBlockSizeInPages - MemoryBlockSizeInPages\r
427 \r
428Returns:\r
429\r
430 EFI_SUCCESS Success\r
431 EFI_OUT_OF_RESOURCES Fail for no resources\r
432 EFI_UNSUPPORTED Unsupported currently\r
433 \r
434--*/\r
435;\r
436\r
437EFI_STATUS\r
438FreeMemoryHeader (\r
439 IN USB2_HC_DEV *HcDev,\r
440 IN MEMORY_MANAGE_HEADER *MemoryHeader\r
441 )\r
442/*++\r
443\r
444Routine Description:\r
445\r
446 Free Memory Header\r
447\r
448Arguments:\r
449\r
450 HcDev - USB2_HC_DEV\r
451 MemoryHeader - MemoryHeader to be freed\r
452\r
453Returns:\r
454\r
455 EFI_SUCCESS Success\r
456 EFI_INVALID_PARAMETER Parameter is error\r
457\r
458--*/\r
459;\r
460\r
461VOID\r
462InsertMemoryHeaderToList (\r
463 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
464 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
465 )\r
466/*++\r
467\r
468Routine Description:\r
469\r
470 Insert Memory Header To List\r
471\r
472Arguments:\r
473\r
474 MemoryHeader - MEMORY_MANAGE_HEADER\r
475 NewMemoryHeader - MEMORY_MANAGE_HEADER\r
476\r
477Returns:\r
478\r
479 VOID\r
480\r
481--*/\r
482;\r
483\r
484EFI_STATUS\r
485AllocMemInMemoryBlock (\r
486 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
487 OUT VOID **Pool,\r
488 IN UINTN NumberOfMemoryUnit\r
489 )\r
490/*++\r
491\r
492Routine Description:\r
493\r
494 Alloc Memory In MemoryBlock\r
495\r
496Arguments:\r
497\r
498 MemoryHeader - MEMORY_MANAGE_HEADER\r
499 Pool - Place to store pointer to memory\r
500 NumberOfMemoryUnit - Number Of Memory Unit\r
501\r
502Returns:\r
503\r
504 EFI_SUCCESS Success\r
505 EFI_NOT_FOUND Can't find the free memory \r
506\r
507--*/\r
508;\r
509\r
510BOOLEAN\r
511IsMemoryBlockEmptied (\r
512 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
513 )\r
514/*++\r
515\r
516Routine Description:\r
517\r
518 Is Memory Block Emptied\r
519\r
520Arguments:\r
521\r
522 MemoryHeaderPtr - MEMORY_MANAGE_HEADER\r
523\r
524Returns:\r
525\r
526 TRUE Empty\r
527 FALSE Not Empty \r
528\r
529--*/\r
530;\r
531\r
532VOID\r
533DelinkMemoryBlock (\r
534 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
535 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader\r
536 )\r
537/*++\r
538\r
539Routine Description:\r
540\r
541 Delink Memory Block\r
542\r
543Arguments:\r
544\r
545 FirstMemoryHeader - MEMORY_MANAGE_HEADER\r
546 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER\r
547\r
548Returns:\r
549\r
550 VOID\r
551\r
552--*/\r
553;\r
554\r
555EFI_STATUS\r
556InitialMemoryManagement (\r
557 IN USB2_HC_DEV *HcDev\r
558 )\r
559/*++\r
560\r
561Routine Description:\r
562\r
563 Initialize Memory Management\r
564\r
565Arguments:\r
566\r
567 HcDev - USB2_HC_DEV\r
568\r
569Returns:\r
570\r
571 EFI_SUCCESS Success\r
572 EFI_DEVICE_ERROR Fail\r
573\r
574--*/\r
575;\r
576\r
577EFI_STATUS\r
578DeinitialMemoryManagement (\r
579 IN USB2_HC_DEV *HcDev\r
580 )\r
581/*++\r
582\r
583Routine Description:\r
584\r
585 Deinitialize Memory Management\r
586\r
587Arguments:\r
588\r
589 HcDev - USB2_HC_DEV\r
590\r
591Returns:\r
592\r
593 EFI_SUCCESS Success\r
594 EFI_DEVICE_ERROR Fail\r
595 \r
596--*/\r
597;\r
598\r
599EFI_STATUS\r
600EhciAllocatePool (\r
601 IN USB2_HC_DEV *HcDev,\r
602 OUT UINT8 **Pool,\r
603 IN UINTN AllocSize\r
604 )\r
605/*++\r
606\r
607Routine Description:\r
608\r
609 Ehci Allocate Pool\r
610\r
611Arguments:\r
612\r
613 HcDev - USB2_HC_DEV\r
614 Pool - Place to store pointer to the memory buffer\r
615 AllocSize - Alloc Size\r
616\r
617Returns:\r
618\r
619 EFI_SUCCESS Success\r
620 EFI_DEVICE_ERROR Fail\r
621 \r
622--*/\r
623;\r
624\r
625VOID\r
626EhciFreePool (\r
627 IN USB2_HC_DEV *HcDev,\r
628 IN UINT8 *Pool,\r
629 IN UINTN AllocSize\r
630 )\r
631/*++\r
632\r
633Routine Description:\r
634\r
635 Uhci Free Pool\r
636\r
637Arguments:\r
638\r
639 HcDev - USB_HC_DEV\r
640 Pool - Pool to free\r
641 AllocSize - Pool size\r
642\r
643Returns:\r
644\r
645 VOID\r
646\r
647--*/\r
648;\r
649\r
650//\r
651// EhciReg Functions\r
652//\r
653EFI_STATUS\r
654ReadEhcCapabiltiyReg (\r
655 IN USB2_HC_DEV *HcDev,\r
656 IN UINT32 CapabiltiyRegAddr,\r
657 IN OUT UINT32 *Data\r
658 )\r
659/*++\r
660\r
661Routine Description:\r
662\r
663 Read Ehc Capabitlity register\r
664 \r
665Arguments:\r
666\r
667 HcDev - USB2_HC_DEV \r
668 CapabiltiyRegAddr - Ehc Capability register address\r
669 Data - A pointer to data read from register\r
670 \r
671Returns:\r
672\r
673 EFI_SUCCESS Success\r
674 EFI_DEVICE_ERROR Fail\r
675 \r
676--*/\r
677;\r
678\r
679EFI_STATUS\r
680ReadEhcOperationalReg (\r
681 IN USB2_HC_DEV *HcDev,\r
682 IN UINT32 OperationalRegAddr,\r
683 IN OUT UINT32 *Data\r
684 )\r
685/*++\r
686\r
687Routine Description:\r
688\r
689 Read Ehc Operation register\r
690 \r
691Arguments:\r
692\r
693 HcDev - USB2_HC_DEV \r
694 OperationalRegAddr - Ehc Operation register address\r
695 Data - A pointer to data read from register\r
696 \r
697Returns:\r
698\r
699 EFI_SUCCESS Success\r
700 EFI_DEVICE_ERROR Fail\r
701 \r
702--*/\r
703;\r
704\r
705EFI_STATUS\r
706WriteEhcOperationalReg (\r
707 IN USB2_HC_DEV *HcDev,\r
708 IN UINT32 OperationalRegAddr,\r
709 IN UINT32 Data\r
710 )\r
711/*++\r
712\r
713Routine Description:\r
714\r
715 Write Ehc Operation register\r
716 \r
717Arguments:\r
718\r
719 HcDev - USB2_HC_DEV \r
720 OperationalRegAddr - Ehc Operation register address\r
721 Data - 32bit write to register\r
722 \r
723Returns:\r
724\r
725 EFI_SUCCESS Success\r
726 EFI_DEVICE_ERROR Fail\r
727 \r
728--*/\r
729;\r
730\r
731EFI_STATUS\r
732SetEhcDoorbell (\r
733 IN USB2_HC_DEV *HcDev\r
734 )\r
735/*++\r
736\r
737Routine Description:\r
738\r
739 Set Ehc door bell bit\r
740 \r
741Arguments:\r
742\r
743 HcDev - USB2_HC_DEV \r
744 \r
745Returns:\r
746\r
747 EFI_SUCCESS Success\r
748 EFI_DEVICE_ERROR Fail\r
749 \r
750--*/\r
751;\r
752\r
753EFI_STATUS\r
754SetFrameListLen (\r
755 IN USB2_HC_DEV *HcDev,\r
756 IN UINTN Length\r
757 )\r
758/*++\r
759\r
760Routine Description:\r
761\r
762 Set the length of Frame List\r
763 \r
764Arguments:\r
765\r
766 HcDev - USB2_HC_DEV \r
767 Length - the required length of frame list\r
768 \r
769Returns:\r
770\r
771 EFI_SUCCESS Success\r
772 EFI_INVALID_PARAMETER Invalid parameter\r
773 EFI_DEVICE_ERROR Fail\r
774 \r
775--*/\r
776;\r
777\r
778BOOLEAN\r
779IsFrameListProgrammable (\r
780 IN USB2_HC_DEV *HcDev\r
781 )\r
782/*++\r
783\r
784Routine Description:\r
785\r
786 Whether frame list is programmable\r
787 \r
788Arguments:\r
789\r
790 HcDev - USB2_HC_DEV \r
791 \r
792Returns:\r
793\r
794 TRUE Programmable\r
795 FALSE Unprogrammable\r
796 \r
797--*/\r
798;\r
799\r
800BOOLEAN\r
801IsPeriodicScheduleEnabled (\r
802 IN USB2_HC_DEV *HcDev\r
803 )\r
804/*++\r
805\r
806Routine Description:\r
807\r
808 Whether periodic schedule is enabled\r
809 \r
810Arguments:\r
811\r
812 HcDev - USB2_HC_DEV \r
813 \r
814Returns:\r
815\r
816 TRUE Enabled\r
817 FALSE Disabled\r
818 \r
819--*/\r
820;\r
821\r
822BOOLEAN\r
823IsAsyncScheduleEnabled (\r
824 IN USB2_HC_DEV *HcDev\r
825 )\r
826/*++\r
827\r
828Routine Description:\r
829\r
830 Whether asynchronous schedule is enabled\r
831 \r
832Arguments:\r
833\r
834 HcDev - USB2_HC_DEV \r
835 \r
836Returns:\r
837\r
838 TRUE Enabled\r
839 FALSE Disabled\r
840 \r
841--*/\r
842;\r
843\r
844BOOLEAN\r
845IsEhcPortEnabled (\r
846 IN USB2_HC_DEV *HcDev,\r
847 IN UINT8 PortNum\r
848 )\r
849/*++\r
850\r
851Routine Description:\r
852\r
853 Whether port is enabled\r
854 \r
855Arguments:\r
856\r
857 HcDev - USB2_HC_DEV \r
858 \r
859Returns:\r
860\r
861 TRUE Enabled\r
862 FALSE Disabled\r
863 \r
864--*/\r
865;\r
866\r
867BOOLEAN\r
868IsEhcReseted (\r
869 IN USB2_HC_DEV *HcDev\r
870 )\r
871/*++\r
872\r
873Routine Description:\r
874\r
875 Whether Ehc is halted\r
876 \r
877Arguments:\r
878\r
879 HcDev - USB2_HC_DEV \r
880 \r
881Returns:\r
882\r
883 TRUE Reseted\r
884 FALSE Unreseted\r
885 \r
886--*/\r
887;\r
888\r
889BOOLEAN\r
890IsEhcHalted (\r
891 IN USB2_HC_DEV *HcDev\r
892 )\r
893/*++\r
894\r
895Routine Description:\r
896\r
897 Whether Ehc is halted\r
898 \r
899Arguments:\r
900\r
901 HcDev - USB2_HC_DEV \r
902 \r
903Returns:\r
904\r
905 TRUE Halted\r
906 FALSE Not halted\r
907 \r
908--*/\r
909;\r
910\r
911BOOLEAN\r
912IsEhcSysError (\r
913 IN USB2_HC_DEV *HcDev\r
914 )\r
915/*++\r
916\r
917Routine Description:\r
918\r
919 Whether Ehc is system error\r
920 \r
921Arguments:\r
922\r
923 HcDev - USB2_HC_DEV \r
924 \r
925Returns:\r
926\r
927 TRUE System error\r
928 FALSE No system error\r
929 \r
930--*/\r
931;\r
932\r
933BOOLEAN\r
934IsHighSpeedDevice (\r
935 IN EFI_USB2_HC_PROTOCOL *This,\r
936 IN UINT8 PortNum \r
937 )\r
938/*++\r
939\r
940Routine Description:\r
941\r
942 Whether high speed device attached\r
943 \r
944Arguments:\r
945\r
946 HcDev - USB2_HC_DEV \r
947 \r
948Returns:\r
949\r
950 TRUE High speed\r
951 FALSE Full speed\r
952 \r
953--*/\r
954;\r
955\r
956EFI_STATUS\r
957WaitForEhcReset (\r
958 IN USB2_HC_DEV *HcDev,\r
959 IN UINTN Timeout\r
960 )\r
961/*++\r
962\r
963Routine Description:\r
964\r
965 wait for Ehc reset or timeout\r
966 \r
967Arguments:\r
968\r
969 HcDev - USB2_HC_DEV \r
970 Timeout - timeout threshold\r
971 \r
972Returns:\r
973\r
974 EFI_SUCCESS Success\r
975 EFI_TIMEOUT Timeout\r
976 \r
977--*/\r
978;\r
979\r
980EFI_STATUS\r
981WaitForEhcHalt (\r
982 IN USB2_HC_DEV *HcDev,\r
983 IN UINTN Timeout\r
984 )\r
985/*++\r
986\r
987Routine Description:\r
988\r
989 wait for Ehc halt or timeout\r
990 \r
991Arguments:\r
992\r
993 HcDev - USB2_HC_DEV \r
994 Timeout - timeout threshold\r
995 \r
996Returns:\r
997\r
998 EFI_SUCCESS Success\r
999 EFI_TIMEOUT Timeout\r
1000 \r
1001--*/\r
1002;\r
1003\r
1004EFI_STATUS\r
1005WaitForEhcNotHalt (\r
1006 IN USB2_HC_DEV *HcDev,\r
1007 IN UINTN Timeout\r
1008 )\r
1009/*++\r
1010\r
1011Routine Description:\r
1012\r
1013 wait for Ehc not halt or timeout\r
1014 \r
1015Arguments:\r
1016\r
1017 HcDev - USB2_HC_DEV \r
1018 Timeout - timeout threshold\r
1019 \r
1020Returns:\r
1021\r
1022 EFI_SUCCESS Success\r
1023 EFI_TIMEOUT Timeout\r
1024 \r
1025--*/\r
1026;\r
1027\r
1028EFI_STATUS\r
1029WaitForEhcDoorbell (\r
1030 IN USB2_HC_DEV *HcDev,\r
1031 IN UINTN Timeout\r
1032 )\r
1033/*++\r
1034\r
1035Routine Description:\r
1036\r
1037 Wait for periodic schedule disable or timeout\r
1038\r
1039Arguments:\r
1040\r
1041 HcDev - USB2_HC_DEV \r
1042 Timeout - timeout threshold\r
1043\r
1044Returns:\r
1045\r
1046 EFI_SUCCESS Success\r
1047 EFI_TIMEOUT Timeout\r
1048 \r
1049--*/\r
1050;\r
1051\r
1052EFI_STATUS\r
1053WaitForAsyncScheduleEnable (\r
1054 IN USB2_HC_DEV *HcDev,\r
1055 IN UINTN Timeout\r
1056 )\r
1057/*++\r
1058\r
1059Routine Description:\r
1060\r
1061 Wait for Ehc asynchronous schedule enable or timeout\r
1062 \r
1063Arguments:\r
1064\r
1065 HcDev - USB2_HC_DEV \r
1066 Timeout - timeout threshold\r
1067 \r
1068Returns:\r
1069\r
1070 EFI_SUCCESS Success\r
1071 EFI_TIMEOUT Timeout\r
1072 \r
1073--*/\r
1074;\r
1075\r
1076EFI_STATUS\r
1077WaitForAsyncScheduleDisable (\r
1078 IN USB2_HC_DEV *HcDev,\r
1079 IN UINTN Timeout\r
1080 )\r
1081/*++\r
1082\r
1083Routine Description:\r
1084\r
1085 Wait for Ehc asynchronous schedule disable or timeout\r
1086 \r
1087Arguments:\r
1088\r
1089 HcDev - USB2_HC_DEV \r
1090 Timeout - timeout threshold\r
1091 \r
1092Returns:\r
1093\r
1094 EFI_SUCCESS Success\r
1095 EFI_TIMEOUT Timeout\r
1096 \r
1097--*/\r
1098;\r
1099\r
1100EFI_STATUS\r
1101WaitForPeriodicScheduleEnable (\r
1102 IN USB2_HC_DEV *HcDev,\r
1103 IN UINTN Timeout\r
1104 )\r
1105/*++\r
1106\r
1107Routine Description:\r
1108\r
1109 Wait for Ehc periodic schedule enable or timeout\r
1110 \r
1111Arguments:\r
1112\r
1113 HcDev - USB2_HC_DEV \r
1114 Timeout - timeout threshold\r
1115 \r
1116Returns:\r
1117\r
1118 EFI_SUCCESS Success\r
1119 EFI_TIMEOUT Timeout\r
1120 \r
1121--*/\r
1122;\r
1123\r
1124EFI_STATUS\r
1125WaitForPeriodicScheduleDisable (\r
1126 IN USB2_HC_DEV *HcDev,\r
1127 IN UINTN Timeout\r
1128 )\r
1129/*++\r
1130\r
1131Routine Description:\r
1132\r
1133 Wait for periodic schedule disable or timeout\r
1134 \r
1135Arguments:\r
1136\r
1137 HcDev - USB2_HC_DEV \r
1138 Timeout - timeout threshold\r
1139 \r
1140Returns:\r
1141\r
1142 EFI_SUCCESS Success\r
1143 EFI_TIMEOUT Timeout\r
1144 \r
1145--*/\r
1146;\r
1147\r
1148EFI_STATUS\r
1149GetCapabilityLen (\r
1150 IN USB2_HC_DEV *HcDev\r
1151 )\r
1152/*++\r
1153\r
1154Routine Description:\r
1155\r
1156 Get the length of capability register\r
1157 \r
1158Arguments:\r
1159\r
1160 HcDev - USB2_HC_DEV \r
1161 \r
1162Returns:\r
1163\r
1164 EFI_SUCCESS Success\r
1165 EFI_DEVICE_ERROR Fail\r
1166 \r
1167--*/\r
1168;\r
1169\r
1170EFI_STATUS\r
1171SetFrameListBaseAddr (\r
1172 IN USB2_HC_DEV *HcDev,\r
1173 IN UINT32 FrameBuffer\r
1174 )\r
1175/*++\r
1176\r
1177Routine Description:\r
1178\r
1179 Set base address of frame list first entry\r
1180 \r
1181Arguments:\r
1182\r
1183 HcDev - USB2_HC_DEV \r
1184 FrameBuffer - base address of first entry of frame list\r
1185 \r
1186Returns:\r
1187\r
1188 EFI_SUCCESS Success\r
1189 EFI_DEVICE_ERROR Fail\r
1190 \r
1191--*/\r
1192;\r
1193\r
1194EFI_STATUS\r
1195SetAsyncListAddr (\r
1196 IN USB2_HC_DEV *HcDev,\r
1197 IN EHCI_QH_ENTITY *QhPtr\r
1198 )\r
1199/*++\r
1200\r
1201Routine Description:\r
1202\r
1203 Set address of first Async schedule Qh\r
1204 \r
1205Arguments:\r
1206\r
1207 HcDev - USB2_HC_DEV \r
1208 QhPtr - A pointer to first Qh in the Async schedule\r
1209 \r
1210Returns:\r
1211\r
1212 EFI_SUCCESS Success\r
1213 EFI_DEVICE_ERROR Fail\r
1214 \r
1215--*/\r
1216;\r
1217\r
1218EFI_STATUS\r
1219SetCtrlDataStructSeg (\r
1220 IN USB2_HC_DEV *HcDev\r
1221 )\r
1222/*++\r
1223\r
1224Routine Description:\r
1225\r
1226 Set address of first Async schedule Qh\r
1227 \r
1228Arguments:\r
1229\r
1230 HcDev - USB2_HC_DEV \r
1231 QhPtr - A pointer to first Qh in the Async schedule\r
1232 \r
1233Returns:\r
1234\r
1235 EFI_SUCCESS Success\r
1236 EFI_DEVICE_ERROR Fail\r
1237 \r
1238--*/\r
1239;\r
1240\r
1241EFI_STATUS\r
1242SetPortRoutingEhc (\r
1243 IN USB2_HC_DEV *HcDev\r
1244 )\r
1245/*++\r
1246\r
1247Routine Description:\r
1248\r
1249 Set Ehc port routing bit\r
1250 \r
1251Arguments:\r
1252\r
1253 HcDev - USB2_HC_DEV \r
1254 \r
1255Returns:\r
1256\r
1257 EFI_SUCCESS Success\r
1258 EFI_DEVICE_ERROR Fail\r
1259 \r
1260--*/\r
1261;\r
1262\r
1263EFI_STATUS\r
1264EnablePeriodicSchedule (\r
1265 IN USB2_HC_DEV *HcDev\r
1266 )\r
1267/*++\r
1268\r
1269Routine Description:\r
1270\r
1271 Enable periodic schedule\r
1272 \r
1273Arguments:\r
1274\r
1275 HcDev - USB2_HC_DEV \r
1276 \r
1277Returns:\r
1278\r
1279 EFI_SUCCESS Success\r
1280 EFI_DEVICE_ERROR Fail\r
1281 \r
1282--*/\r
1283;\r
1284\r
1285EFI_STATUS\r
1286DisablePeriodicSchedule (\r
1287 IN USB2_HC_DEV *HcDev\r
1288 )\r
1289/*++\r
1290\r
1291Routine Description:\r
1292\r
1293 Disable periodic schedule\r
1294 \r
1295Arguments:\r
1296\r
1297 HcDev - USB2_HC_DEV \r
1298 \r
1299Returns:\r
1300\r
1301 EFI_SUCCESS Success\r
1302 EFI_DEVICE_ERROR Fail\r
1303 \r
1304--*/\r
1305;\r
1306\r
1307EFI_STATUS\r
1308EnableAsynchronousSchedule (\r
1309 IN USB2_HC_DEV *HcDev\r
1310 )\r
1311/*++\r
1312\r
1313Routine Description:\r
1314\r
1315 Enable asynchrounous schedule\r
1316 \r
1317Arguments:\r
1318\r
1319 HcDev - USB2_HC_DEV \r
1320 \r
1321Returns:\r\r
1322\r
1323 EFI_SUCCESS Success\r
1324 EFI_DEVICE_ERROR Fail\r
1325 \r
1326--*/\r
1327;\r
1328\r
1329EFI_STATUS\r
1330DisableAsynchronousSchedule (\r
1331 IN USB2_HC_DEV *HcDev\r
1332 )\r
1333/*++\r
1334\r
1335Routine Description:\r
1336\r
1337 Disable asynchrounous schedule\r
1338 \r
1339Arguments:\r
1340\r
1341 HcDev - USB2_HC_DEV \r
1342 \r
1343Returns:\r
1344\r
1345 EFI_SUCCESS Success\r
1346 EFI_DEVICE_ERROR Fail\r
1347 \r
1348--*/\r
1349;\r
1350\r
1351EFI_STATUS\r
1352StartScheduleExecution (\r
1353 IN USB2_HC_DEV *HcDev\r
1354 )\r
1355/*++\r
1356\r
1357Routine Description:\r
1358\r
1359 Start Ehc schedule execution\r
1360 \r
1361Arguments:\r
1362\r
1363 HcDev - USB2_HC_DEV \r
1364 \r
1365Returns:\r
1366\r
1367 EFI_SUCCESS Success\r
1368 EFI_DEVICE_ERROR Fail\r
1369 \r
1370--*/\r
1371;\r
1372\r
1373EFI_STATUS\r
1374ResetEhc (\r
1375 IN USB2_HC_DEV *HcDev\r
1376 )\r
1377/*++\r
1378\r
1379Routine Description:\r
1380\r
1381 Reset Ehc\r
1382 \r
1383Arguments:\r
1384\r
1385 HcDev - USB2_HC_DEV \r
1386 \r
1387Returns:\r
1388\r
1389 EFI_SUCCESS Success\r
1390 EFI_DEVICE_ERROR Fail\r
1391 \r
1392--*/\r
1393;\r
1394\r
1395EFI_STATUS\r
1396ClearEhcAllStatus (\r
1397 IN USB2_HC_DEV *HcDev\r
1398 )\r
1399/*++\r
1400\r
1401Routine Description:\r
1402\r
1403 Clear Ehc all status bits\r
1404 \r
1405Arguments:\r
1406\r
1407 HcDev - USB2_HC_DEV \r
1408 \r
1409Returns:\r
1410\r
1411 EFI_SUCCESS Success\r
1412 EFI_DEVICE_ERROR Fail\r
1413 \r
1414--*/\r
1415;\r
1416\r
1417//\r
1418// EhciSched Functions\r
1419//\r
1420EFI_STATUS\r
1421InitialPeriodicFrameList (\r
1422 IN USB2_HC_DEV *HcDev,\r
1423 IN UINTN Length\r
1424 )\r
1425/*++\r
1426\r
1427Routine Description:\r
1428\r
1429 Initialize Periodic Schedule Frame List\r
1430\r
1431Arguments:\r
1432\r
1433 HcDev - USB2_HC_DEV\r
1434 Length - Frame List Length\r
1435 \r
1436Returns:\r
1437\r
1438 EFI_SUCCESS Success\r
1439 EFI_DEVICE_ERROR Fail\r
1440 \r
1441--*/\r
1442;\r
1443\r
1444VOID\r
1445DeinitialPeriodicFrameList (\r
1446 IN USB2_HC_DEV *HcDev\r
1447 )\r
1448/*++\r
1449\r
1450Routine Description:\r
1451\r
1452 Deinitialize Periodic Schedule Frame List\r
1453\r
1454Arguments:\r
1455\r
1456 HcDev - USB2_HC_DEV\r
1457\r
1458Returns:\r
1459\r
1460 VOID\r
1461 \r
1462--*/\r
1463;\r
1464\r
1465EFI_STATUS\r
1466CreatePollingTimer (\r
1467 IN USB2_HC_DEV *HcDev,\r
1468 IN EFI_EVENT_NOTIFY NotifyFunction\r
1469 )\r
1470/*++\r
1471\r
1472Routine Description:\r
1473\r
1474 Create Async Request Polling Timer\r
1475\r
1476Arguments:\r
1477\r
1478 HcDev - USB2_HC_DEV\r
1479 NotifyFunction - Timer Notify Function\r
1480 \r
1481Returns:\r
1482\r
1483 EFI_SUCCESS Success\r
1484 EFI_DEVICE_ERROR Fail\r
1485 \r
1486--*/\r
1487;\r
1488\r
1489EFI_STATUS\r
1490DestoryPollingTimer (\r
1491 IN USB2_HC_DEV *HcDev\r
1492 )\r
1493/*++\r
1494\r
1495Routine Description:\r
1496\r
1497 Destory Async Request Polling Timer\r
1498\r
1499Arguments:\r
1500\r
1501 HcDev - USB2_HC_DEV\r
1502 \r
1503Returns:\r
1504\r
1505 EFI_SUCCESS Success\r
1506 EFI_DEVICE_ERROR Fail\r
1507 \r
1508--*/\r
1509;\r
1510\r
1511EFI_STATUS\r
1512StartPollingTimer (\r
1513 IN USB2_HC_DEV *HcDev\r
1514 )\r
1515/*++\r
1516\r
1517Routine Description:\r
1518\r
1519 Start Async Request Polling Timer\r
1520\r
1521Arguments:\r
1522\r
1523 HcDev - USB2_HC_DEV\r
1524 \r
1525Returns:\r
1526\r
1527 EFI_SUCCESS Success\r
1528 EFI_DEVICE_ERROR Fail\r
1529 \r
1530--*/\r
1531;\r
1532\r
1533EFI_STATUS\r
1534StopPollingTimer (\r
1535 IN USB2_HC_DEV *HcDev\r
1536 )\r
1537/*++\r
1538\r
1539Routine Description:\r
1540\r
1541 Stop Async Request Polling Timer\r
1542\r
1543Arguments:\r
1544\r
1545 HcDev - USB2_HC_DEV\r
1546 \r
1547Returns:\r
1548\r
1549 EFI_SUCCESS Success\r
1550 EFI_DEVICE_ERROR Fail\r
1551 \r
1552--*/\r
1553;\r
1554\r
1555EFI_STATUS\r
1556CreateQh (\r
1557 IN USB2_HC_DEV *HcDev,\r
1558 IN UINT8 DeviceAddr,\r
1559 IN UINT8 Endpoint,\r
1560 IN UINT8 DeviceSpeed,\r
1561 IN UINTN MaxPacketLen,\r
1562 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1563 )\r
1564/*++\r
1565\r
1566Routine Description:\r
1567\r
1568 Create Qh Structure and Pre-Initialize\r
1569\r
1570Arguments:\r
1571\r
1572 HcDev - USB2_HC_DEV \r
1573 DeviceAddr - Address of Device\r
1574 Endpoint - Endpoint Number\r
1575 DeviceSpeed - Device Speed\r
1576 MaxPacketLen - Max Length of one Packet\r
1577 QhPtrPtr - A pointer of pointer to Qh for return\r
1578 \r
1579Returns:\r
1580\r
1581 EFI_SUCCESS Success\r
1582 EFI_DEVICE_ERROR Fail\r
1583 \r
1584--*/\r
1585;\r
1586\r
1587EFI_STATUS\r
1588CreateControlQh (\r
1589 IN USB2_HC_DEV *HcDev,\r
1590 IN UINT8 DeviceAddr,\r
1591 IN UINT8 DeviceSpeed,\r
1592 IN UINTN MaxPacketLen,\r
1593 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1594 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1595 )\r
1596/*++\r
1597\r
1598Routine Description:\r
1599\r
1600 Create Qh for Control Transfer\r
1601\r
1602Arguments:\r
1603\r
1604 HcDev - USB2_HC_DEV \r
1605 DeviceAddr - Address of Device\r
1606 DeviceSpeed - Device Speed\r
1607 MaxPacketLen - Max Length of one Packet\r
1608 Translator - Translator Transaction for SplitX\r
1609 QhPtrPtr - A pointer of pointer to Qh for return\r
1610 \r
1611Returns:\r
1612\r
1613 EFI_SUCCESS Success\r
1614 EFI_DEVICE_ERROR Fail\r
1615 \r
1616--*/\r
1617;\r
1618\r
1619EFI_STATUS\r
1620CreateBulkQh (\r
1621 IN USB2_HC_DEV *HcDev,\r
1622 IN UINT8 DeviceAddr,\r
1623 IN UINT8 EndPointAddr,\r
1624 IN UINT8 DeviceSpeed,\r
1625 IN UINT8 DataToggle,\r
1626 IN UINTN MaxPacketLen,\r
1627 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1628 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1629 )\r
1630/*++\r
1631\r
1632Routine Description:\r
1633\r
1634 Create Qh for Bulk Transfer\r
1635\r
1636Arguments:\r
1637\r
1638 HcDev - USB2_HC_DEV \r
1639 DeviceAddr - Address of Device\r
1640 EndPointAddr - Address of Endpoint\r
1641 DeviceSpeed - Device Speed\r
1642 MaxPacketLen - Max Length of one Packet\r
1643 Translator - Translator Transaction for SplitX\r
1644 QhPtrPtr - A pointer of pointer to Qh for return\r
1645 \r
1646Returns:\r
1647\r
1648 EFI_SUCCESS Success\r
1649 EFI_DEVICE_ERROR Fail\r
1650 \r
1651--*/\r
1652;\r
1653\r
1654EFI_STATUS\r
1655CreateInterruptQh (\r
1656 IN USB2_HC_DEV *HcDev,\r
1657 IN UINT8 DeviceAddr,\r
1658 IN UINT8 EndPointAddr,\r
1659 IN UINT8 DeviceSpeed,\r
1660 IN UINT8 DataToggle,\r
1661 IN UINTN MaxPacketLen,\r
1662 IN UINTN Interval,\r
1663 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1664 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1665 )\r
1666/*++\r
1667\r
1668Routine Description:\r
1669\r
1670 Create Qh for Control Transfer\r
1671\r
1672Arguments:\r
1673\r
1674 HcDev - USB2_HC_DEV \r
1675 DeviceAddr - Address of Device\r
1676 EndPointAddr - Address of Endpoint\r
1677 DeviceSpeed - Device Speed\r
1678 MaxPacketLen - Max Length of one Packet\r
1679 Interval - value of interval\r
1680 Translator - Translator Transaction for SplitX\r
1681 QhPtrPtr - A pointer of pointer to Qh for return\r
1682 \r
1683Returns:\r
1684\r
1685 EFI_SUCCESS Success\r
1686 EFI_DEVICE_ERROR Fail\r
1687 \r
1688--*/\r
1689;\r
1690\r
1691VOID\r
1692DestoryQh (\r
1693 IN USB2_HC_DEV *HcDev,\r
1694 IN EHCI_QH_ENTITY *QhPtr\r
1695 )\r
1696/*++\r
1697\r
1698Routine Description:\r
1699\r
1700 Destory Qh Structure \r
1701 \r
1702Arguments:\r
1703\r
1704 HcDev - USB2_HC_DEV \r
1705 QhPtr - A pointer to Qh\r
1706 \r
1707Returns:\r
1708\r
1709 VOID\r
1710 \r
1711--*/\r
1712;\r
1713\r
1714EFI_STATUS\r
1715CreateQtd (\r
1716 IN USB2_HC_DEV *HcDev,\r
1717 IN UINT8 *DataPtr,\r
1718 IN UINTN DataLen,\r
1719 IN UINT8 PktId,\r
1720 IN UINT8 Toggle,\r
1721 IN UINT8 QtdStatus,\r
1722 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1723 )\r
1724/*++\r
1725\r
1726Routine Description:\r
1727\r
1728 Create Qtd Structure and Pre-Initialize it\r
1729\r
1730Arguments:\r
1731\r
1732 HcDev - USB2_HC_DEV \r
1733 DataPtr - A pointer to user data buffer to transfer\r
1734 DataLen - Length of user data to transfer\r
1735 PktId - Packet Identification of this Qtd\r
1736 Toggle - Data Toggle of this Qtd\r
1737 QtdStatus - Default value of status of this Qtd\r
1738 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1739 \r
1740Returns:\r
1741\r
1742 EFI_SUCCESS Success\r
1743 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1744 \r
1745--*/\r
1746;\r
1747\r
1748EFI_STATUS\r
1749CreateSetupQtd (\r
1750 IN USB2_HC_DEV *HcDev,\r
1751 IN UINT8 *DevReqPtr,\r
1752 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1753 )\r
1754/*++\r
1755\r
1756Routine Description:\r
1757\r
1758 Create Qtd Structure for Setup \r
1759\r
1760Arguments:\r
1761\r
1762 HcDev - USB2_HC_DEV \r
1763 DevReqPtr - A pointer to Device Request Data\r
1764 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1765 \r
1766Returns:\r
1767\r
1768 EFI_SUCCESS Success\r
1769 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1770 \r
1771--*/\r
1772;\r
1773\r
1774EFI_STATUS\r
1775CreateDataQtd (\r
1776 IN USB2_HC_DEV *HcDev,\r
1777 IN UINT8 *DataPtr,\r
1778 IN UINTN DataLen,\r
1779 IN UINT8 PktId,\r
1780 IN UINT8 Toggle,\r
1781 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1782 )\r
1783/*++\r
1784\r
1785Routine Description:\r
1786\r
1787 Create Qtd Structure for data \r
1788\r
1789Arguments:\r
1790\r
1791 HcDev - USB2_HC_DEV \r
1792 DataPtr - A pointer to user data buffer to transfer\r
1793 DataLen - Length of user data to transfer\r
1794 PktId - Packet Identification of this Qtd\r
1795 Toggle - Data Toggle of this Qtd\r
1796 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1797 \r
1798Returns:\r
1799\r
1800 EFI_SUCCESS Success\r
1801 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1802 \r
1803--*/\r
1804;\r
1805\r
1806EFI_STATUS\r
1807CreateStatusQtd (\r
1808 IN USB2_HC_DEV *HcDev,\r
1809 IN UINT8 PktId,\r
1810 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1811 )\r
1812/*++\r
1813\r
1814Routine Description:\r
1815\r
1816 Create Qtd Structure for status \r
1817\r
1818Arguments:\r
1819\r
1820 HcDev - USB2_HC_DEV \r
1821 PktId - Packet Identification of this Qtd\r
1822 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1823 \r
1824Returns:\r
1825\r
1826 EFI_SUCCESS Success\r
1827 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1828 \r
1829--*/\r
1830;\r
1831\r
1832EFI_STATUS\r
1833CreateAltQtd (\r
1834 IN USB2_HC_DEV *HcDev,\r
1835 IN UINT8 PktId,\r
1836 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1837 )\r
1838/*++\r
1839\r
1840Routine Description:\r
1841\r
1842 Create Qtd Structure for Alternative \r
1843\r
1844Arguments:\r
1845\r
1846 HcDev - USB2_HC_DEV \r
1847 PktId - Packet Identification of this Qtd\r
1848 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1849 \r
1850Returns:\r
1851\r
1852 EFI_SUCCESS Success\r
1853 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1854 \r
1855--*/\r
1856;\r
1857\r
1858EFI_STATUS\r
1859CreateControlQtds (\r
1860 IN USB2_HC_DEV *HcDev,\r
1861 IN UINT8 DataPktId,\r
1862 IN UINT8 *RequestCursor,\r
1863 IN UINT8 *DataCursor,\r
1864 IN UINTN DataLen,\r
1865 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1866 OUT EHCI_QTD_ENTITY **ControlQtdsHead\r
1867 )\r
1868/*++\r
1869\r
1870Routine Description:\r
1871\r
1872 Create Qtds list for Control Transfer \r
1873\r
1874Arguments:\r
1875\r
1876 HcDev - USB2_HC_DEV \r
1877 DataPktId - Packet Identification of Data Qtds\r
1878 RequestCursor - A pointer to request structure buffer to transfer\r
1879 DataCursor - A pointer to user data buffer to transfer\r
1880 DataLen - Length of user data to transfer\r
1881 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1882 \r
1883Returns:\r
1884\r
1885 EFI_SUCCESS Success\r
1886 EFI_DEVICE_ERROR Fail\r
1887 \r
1888--*/\r
1889;\r
1890\r
1891EFI_STATUS\r
1892CreateBulkOrInterruptQtds (\r
1893 IN USB2_HC_DEV *HcDev,\r
1894 IN UINT8 PktId,\r
1895 IN UINT8 *DataCursor,\r
1896 IN UINTN DataLen,\r
1897 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1898 OUT EHCI_QTD_ENTITY **QtdsHead\r
1899 )\r
1900/*++\r
1901\r
1902Routine Description:\r
1903\r
1904 Create Qtds list for Bulk or Interrupt Transfer \r
1905\r
1906Arguments:\r
1907\r
1908 HcDev - USB2_HC_DEV \r
1909 PktId - Packet Identification of Qtds\r
1910 DataCursor - A pointer to user data buffer to transfer\r
1911 DataLen - Length of user data to transfer\r
1912 DataToggle - Data Toggle to start\r
1913 Translator - Translator Transaction for SplitX\r
1914 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1915 \r
1916Returns:\r
1917\r
1918 EFI_SUCCESS Success\r
1919 EFI_DEVICE_ERROR Fail\r
1920 \r
1921--*/\r
1922;\r
1923\r
1924VOID\r
1925DestoryQtds (\r
1926 IN USB2_HC_DEV *HcDev,\r
1927 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
1928 )\r
1929/*++\r
1930\r
1931Routine Description:\r
1932\r
1933 Destory all Qtds in the list\r
1934\r
1935Arguments:\r
1936\r
1937 HcDev - USB2_HC_DEV \r
1938 FirstQtdPtr - A pointer to first Qtd in the list \r
1939 \r
1940Returns:\r
1941\r
1942 VOID\r
1943\r
1944--*/\r
1945;\r
1946\r
1947VOID\r
1948LinkQtdToQtd (\r
1949 IN EHCI_QTD_ENTITY *PreQtdPtr,\r
1950 IN EHCI_QTD_ENTITY *QtdPtr\r
1951 )\r
1952/*++\r
1953\r
1954Routine Description:\r
1955\r
1956 Link Qtds together\r
1957 \r
1958Arguments:\r
1959\r
1960 PreQtdPtr - A pointer to pre Qtd\r
1961 QtdPtr - A pointer to next Qtd\r
1962 \r
1963Returns:\r
1964\r
1965 VOID\r
1966\r
1967--*/\r
1968;\r
1969\r
1970VOID\r
1971LinkQtdsToAltQtd (\r
1972 IN EHCI_QTD_ENTITY *FirstQtdPtr,\r
1973 IN EHCI_QTD_ENTITY *AltQtdPtr\r
1974 )\r
1975/*++\r
1976\r
1977Routine Description:\r
1978\r
1979 Link AlterQtds together\r
1980 \r
1981Arguments:\r
1982\r
1983 FirstQtdPtr - A pointer to first Qtd in the list\r
1984 AltQtdPtr - A pointer to alternative Qtd\r
1985 \r
1986Returns:\r
1987 VOID\r
1988\r
1989--*/\r
1990;\r
1991\r
1992VOID\r
1993LinkQtdToQh (\r
1994 IN EHCI_QH_ENTITY *QhPtr,\r
1995 IN EHCI_QTD_ENTITY *QtdEntryPtr\r
1996 )\r
1997/*++\r
1998\r
1999Routine Description:\r
2000\r
2001 Link Qtds list to Qh\r
2002 \r
2003Arguments:\r
2004\r
2005 QhPtr - A pointer to Qh\r
2006 QtdPtr - A pointer to first Qtd in the list\r
2007 \r
2008Returns:\r
2009\r
2010 VOID\r
2011\r
2012--*/\r
2013;\r
2014\r
2015EFI_STATUS\r
2016LinkQhToAsyncList (\r
2017 IN USB2_HC_DEV *HcDev,\r
2018 IN EHCI_QH_ENTITY *QhPtr\r
2019 )\r
2020/*++\r
2021\r
2022Routine Description:\r
2023\r
2024 Link Qh to Async Schedule List\r
2025 \r
2026Arguments:\r
2027\r
2028 HcDev - USB2_HC_DEV \r
2029 QhPtr - A pointer to Qh\r
2030 \r
2031Returns:\r
2032\r
2033 EFI_SUCCESS Success\r
2034 EFI_DEVICE_ERROR Fail\r
2035 \r
2036--*/\r
2037;\r
2038\r
2039EFI_STATUS\r
2040UnlinkQhFromAsyncList (\r
2041 IN USB2_HC_DEV *HcDev,\r
2042 IN EHCI_QH_ENTITY *QhPtr\r
2043 )\r
2044/*++\r
2045\r
2046Routine Description:\r
2047\r
2048 Unlink Qh from Async Schedule List\r
2049 \r
2050Arguments:\r
2051\r
2052 HcDev - USB2_HC_DEV \r
2053 QhPtr - A pointer to Qh\r
2054 \r
2055Returns:\r
2056\r
2057 EFI_SUCCESS Success\r
2058 EFI_DEVICE_ERROR Fail\r
2059 \r
2060--*/\r
2061;\r
2062\r
2063VOID\r
2064LinkQhToPeriodicList (\r
2065 IN USB2_HC_DEV *HcDev,\r
2066 IN EHCI_QH_ENTITY *QhPtr\r
2067 )\r
2068/*++\r
2069\r
2070Routine Description:\r
2071\r
2072 Link Qh to Periodic Schedule List\r
2073 \r
2074Arguments:\r
2075\r
2076 HcDev - USB2_HC_DEV \r
2077 QhPtr - A pointer to Qh\r
2078 \r
2079Returns:\r
2080\r
2081 VOID\r
2082\r
2083--*/\r
2084;\r
2085\r
2086VOID\r
2087UnlinkQhFromPeriodicList (\r
2088 IN USB2_HC_DEV *HcDev,\r
2089 IN EHCI_QH_ENTITY *QhPtr,\r
2090 IN UINTN Interval\r
2091 )\r
2092/*++\r
2093\r
2094Routine Description:\r
2095\r
2096 Unlink Qh from Periodic Schedule List\r
2097 \r
2098Arguments:\r
2099\r
2100 HcDev - USB2_HC_DEV \r
2101 QhPtr - A pointer to Qh\r
2102 Interval - Interval of this periodic transfer\r
2103 \r
2104Returns:\r
2105\r
2106 VOID\r
2107 \r
2108--*/\r
2109;\r
2110\r
2111VOID\r
2112LinkToAsyncReqeust (\r
2113 IN USB2_HC_DEV *HcDev,\r
2114 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2115 )\r
2116/*++\r
2117\r
2118Routine Description:\r
2119\r
2120 Llink AsyncRequest Entry to Async Request List\r
2121 \r
2122Arguments:\r
2123\r
2124 HcDev - USB2_HC_DEV \r
2125 AsyncRequestPtr - A pointer to Async Request Entry\r
2126 \r
2127Returns:\r
2128\r
2129 VOID\r
2130 \r
2131--*/\r
2132;\r
2133\r
2134VOID\r
2135UnlinkFromAsyncReqeust (\r
2136 IN USB2_HC_DEV *HcDev,\r
2137 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2138 )\r
2139/*++\r
2140\r
2141Routine Description:\r
2142\r
2143 Unlink AsyncRequest Entry from Async Request List\r
2144 \r
2145Arguments:\r
2146\r
2147 HcDev - USB2_HC_DEV \r
2148 AsyncRequestPtr - A pointer to Async Request Entry\r
2149 \r
2150Returns:\r
2151\r
2152 VOID\r
2153 \r
2154--*/\r
2155;\r
2156\r
2157UINTN\r
2158GetNumberOfQtd (\r
2159 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2160 )\r
2161/*++\r
2162\r
2163Routine Description:\r
2164\r
2165 Number of Qtds in the list\r
2166 \r
2167Arguments:\r
2168\r
2169 FirstQtdPtr - A pointer to first Qtd in the list\r
2170 \r
2171Returns:\r
2172\r
2173 Number of Qtds in the list\r
2174\r
2175--*/\r
2176;\r
2177\r
2178UINTN\r
2179GetNumberOfTransaction (\r
2180 IN UINTN SizeOfData,\r
2181 IN UINTN SizeOfTransaction\r
2182 )\r
2183/*++\r
2184\r
2185Routine Description:\r
2186\r
2187 Number of Transactions in one Qtd\r
2188 \r
2189Arguments:\r
2190\r
2191 SizeOfData - Size of one Qtd\r
2192 SizeOfTransaction - Size of one Transaction\r
2193 \r
2194Returns:\r
2195\r
2196 Number of Transactions in this Qtd\r
2197\r
2198--*/\r
2199;\r
2200\r
2201UINTN\r
2202GetCapacityOfQtd (\r
2203 IN UINT8 *BufferCursor\r
2204 )\r
2205/*++\r
2206\r
2207Routine Description:\r
2208\r
2209 Get Capacity of Qtd\r
2210 \r
2211Arguments:\r
2212\r
2213 BufferCursor - BufferCursor of the Qtd\r
2214 \r
2215Returns:\r
2216\r
2217 Capacity of Qtd\r
2218\r
2219--*/\r
2220;\r
2221\r
2222UINTN\r
2223GetApproxiOfInterval (\r
2224 IN UINTN Interval\r
2225 )\r
2226/*++\r
2227\r
2228Routine Description:\r
2229\r
2230 Get the approximate value in the 2 index sequence\r
2231 \r
2232Arguments:\r
2233\r
2234 Interval - the value of interval\r
2235 \r
2236Returns:\r
2237\r
2238 approximate value of interval in the 2 index sequence\r
2239 \r
2240--*/\r
2241;\r
2242\r
2243EHCI_QTD_HW *\r
2244GetQtdNextPointer (\r
2245 IN EHCI_QTD_HW *HwQtdPtr\r
2246 )\r
2247/*++\r
2248\r
2249Routine Description:\r
2250\r
2251 Get Qtd next pointer field\r
2252 \r
2253Arguments:\r
2254\r
2255 HwQtdPtr - A pointer to hardware Qtd structure\r
2256 \r
2257Returns:\r
2258\r
2259 A pointer to next hardware Qtd structure\r
2260 \r
2261--*/\r
2262;\r
2263\r
2264BOOLEAN\r
2265IsQtdStatusActive (\r
2266 IN EHCI_QTD_HW *HwQtdPtr\r
2267 )\r
2268/*++\r
2269\r
2270Routine Description:\r
2271\r
2272 Whether Qtd status is active or not\r
2273 \r
2274Arguments:\r
2275\r
2276 HwQtdPtr - A pointer to hardware Qtd structure\r
2277 \r
2278Returns:\r
2279\r
2280 TRUE Active\r
2281 FALSE Inactive\r
2282 \r
2283--*/\r
2284;\r
2285\r
2286BOOLEAN\r
2287IsQtdStatusHalted (\r
2288 IN EHCI_QTD_HW *HwQtdPtr\r
2289 )\r
2290/*++\r
2291\r
2292Routine Description:\r
2293\r
2294 Whether Qtd status is halted or not\r
2295 \r
2296Arguments:\r
2297\r
2298 HwQtdPtr - A pointer to hardware Qtd structure\r
2299 \r
2300Returns:\r\r
2301\r
2302 TRUE Halted\r
2303 FALSE Not halted\r
2304 \r
2305--*/\r
2306;\r
2307\r
2308BOOLEAN\r
2309IsQtdStatusBufferError (\r
2310 IN EHCI_QTD_HW *HwQtdPtr\r
2311 )\r
2312/*++\r
2313\r
2314Routine Description:\r
2315\r
2316 Whether Qtd status is buffer error or not\r
2317 \r
2318Arguments:\r
2319\r
2320 HwQtdPtr - A pointer to hardware Qtd structure\r
2321 \r
2322Returns:\r
2323\r
2324 TRUE Buffer error\r
2325 FALSE No buffer error\r
2326 \r
2327--*/\r
2328;\r
2329\r
2330BOOLEAN\r
2331IsQtdStatusBabbleError (\r
2332 IN EHCI_QTD_HW *HwQtdPtr\r
2333 )\r
2334/*++\r
2335\r
2336Routine Description:\r
2337\r
2338 Whether Qtd status is babble error or not\r
2339 \r
2340Arguments:\r
2341\r
2342 HwQtdPtr - A pointer to hardware Qtd structure\r
2343 \r
2344Returns:\r
2345\r
2346 TRUE Babble error\r
2347 FALSE No babble error\r
2348 \r
2349--*/\r
2350;\r
2351\r
2352BOOLEAN\r
2353IsQtdStatusTransactionError (\r
2354 IN EHCI_QTD_HW *HwQtdPtr\r
2355 )\r
2356/*++\r
2357\r
2358Routine Description:\r
2359\r
2360 Whether Qtd status is transaction error or not\r
2361 \r
2362Arguments:\r
2363\r
2364 HwQtdPtr - A pointer to hardware Qtd structure\r
2365 \r
2366Returns:\r
2367\r
2368 TRUE Transaction error\r
2369 FALSE No transaction error\r
2370 \r
2371--*/\r
2372;\r
2373\r
2374BOOLEAN\r
2375IsDataInTransfer (\r
2376 IN UINT8 EndPointAddress\r
2377 )\r
2378/*++\r
2379\r
2380Routine Description:\r
2381\r
2382 Whether is a DataIn direction transfer\r
2383 \r
2384Arguments:\r
2385\r
2386 EndPointAddress - address of the endpoint \r
2387 \r
2388Returns:\r
2389\r
2390 TRUE DataIn\r
2391 FALSE DataOut\r
2392 \r
2393--*/\r
2394;\r
2395\r
2396EFI_STATUS\r
2397MapDataBuffer (\r
2398 IN USB2_HC_DEV *HcDev,\r
2399 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
2400 IN OUT VOID *Data,\r
2401 IN OUT UINTN *DataLength,\r
2402 OUT UINT8 *PktId,\r
2403 OUT UINT8 **DataCursor,\r
2404 OUT VOID **DataMap\r
2405 )\r
2406/*++\r
2407\r
2408Routine Description:\r
2409\r
2410 Map address of user data buffer\r
2411 \r
2412Arguments:\r
2413\r
2414 HcDev - USB2_HC_DEV \r
2415 TransferDirection - direction of transfer\r
2416 Data - A pointer to user data buffer \r
2417 DataLength - length of user data\r
2418 PktId - Packte Identificaion\r
2419 DataCursor - mapped address to return\r
2420 DataMap - identificaion of this mapping to return\r
2421 \r
2422Returns:\r
2423\r
2424 EFI_SUCCESS Success\r
2425 EFI_DEVICE_ERROR Fail\r
2426 \r
2427--*/\r
2428;\r
2429\r
2430EFI_STATUS\r
2431MapRequestBuffer (\r
2432 IN USB2_HC_DEV *HcDev,\r
2433 IN OUT VOID *Request,\r
2434 OUT UINT8 **RequestCursor,\r
2435 OUT VOID **RequestMap\r
2436 )\r
2437/*++\r
2438\r
2439Routine Description:\r
2440\r
2441 Map address of request structure buffer\r
2442 \r
2443Arguments:\r
2444\r
2445 HcDev - USB2_HC_DEV \r
2446 Request - A pointer to request structure\r
2447 RequestCursor - Mapped address of request structure to return\r
2448 RequestMap - Identificaion of this mapping to return\r
2449 \r
2450Returns:\r
2451\r
2452 EFI_SUCCESS Success\r
2453 EFI_DEVICE_ERROR Fail\r
2454 \r
2455--*/\r
2456;\r
2457\r
2458VOID\r
2459SetQtdBufferPointer (\r
2460 IN EHCI_QTD_HW *QtdHwPtr,\r
2461 IN VOID *DataPtr,\r
2462 IN UINTN DataLen\r
2463 )\r
2464/*++\r
2465\r
2466Routine Description:\r
2467\r
2468 Set data buffer pointers in Qtd\r
2469\r
2470Arguments:\r
2471\r
2472 QtdHwPtr - A pointer to Qtd hardware structure \r
2473 DataPtr - A pointer to user data buffer\r
2474 DataLen - Length of the user data buffer\r
2475 \r
2476Returns:\r
2477\r
2478 VOID\r
2479\r
2480--*/\r
2481;\r
2482\r
2483EHCI_QTD_HW *\r
2484GetQtdAlternateNextPointer (\r
2485 IN EHCI_QTD_HW *HwQtdPtr\r
2486 )\r
2487/*++\r
2488\r
2489Routine Description:\r
2490\r
2491 Get Qtd alternate next pointer field\r
2492 \r
2493Arguments:\r
2494\r
2495 HwQtdPtr - A pointer to hardware Qtd structure\r
2496 \r
2497Returns:\r
2498\r
2499 A pointer to hardware alternate Qtd\r
2500 \r
2501--*/\r
2502;\r
2503\r
2504VOID\r
2505ZeroOutQhOverlay (\r
2506 IN EHCI_QH_ENTITY *QhPtr\r
2507 )\r
2508/*++\r
2509\r
2510Routine Description:\r
2511\r
2512 Zero out the fields in Qh structure\r
2513 \r
2514Arguments:\r
2515\r
2516 QhPtr - A pointer to Qh structure\r
2517 \r
2518Returns:\r
2519\r
2520 VOID\r
2521 \r
2522--*/\r
2523;\r
2524\r
2525VOID\r
2526UpdateAsyncRequestTransfer (\r
2527 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,\r
2528 IN UINT32 TransferResult,\r
2529 IN UINTN ErrTDPos\r
2530 )\r
2531/*++\r
2532\r
2533Routine Description:\r
2534\r
2535 Update asynchronous request transfer\r
2536 \r
2537Arguments:\r
2538\r
2539 AsyncRequestPtr - A pointer to async request \r
2540 TransferResult - transfer result \r
2541 ErrQtdPos - postion of error Qtd\r
2542 \r
2543Returns:\r
2544\r
2545 VOID\r
2546 \r
2547--*/\r
2548;\r
2549\r
2550\r
2551EFI_STATUS\r
2552DeleteAsyncRequestTransfer (\r
2553 IN USB2_HC_DEV *HcDev,\r
2554 IN UINT8 DeviceAddress,\r
2555 IN UINT8 EndPointAddress,\r
2556 OUT UINT8 *DataToggle\r
2557 )\r
2558/*++\r
2559\r
2560Routine Description:\r
2561\r
2562 Delete all asynchronous request transfer\r
2563 \r
2564Arguments:\r
2565\r
2566 HcDev - USB2_HC_DEV \r
2567 DeviceAddress - address of usb device\r
2568 EndPointAddress - address of endpoint\r
2569 DataToggle - stored data toggle\r
2570 \r
2571Returns:\r
2572\r
2573 EFI_SUCCESS Success\r
2574 EFI_DEVICE_ERROR Fail\r
2575\r
2576--*/\r
2577;\r
2578\r
2579VOID\r
2580CleanUpAllAsyncRequestTransfer (\r
2581 IN USB2_HC_DEV *HcDev\r
2582 )\r
2583/*++\r
2584\r
2585Routine Description:\r
2586\r
2587 Clean up all asynchronous request transfer\r
2588 \r
2589Arguments:\r
2590\r
2591 HcDev - USB2_HC_DEV \r
2592 \r
2593Returns:\r
2594 VOID\r
2595 \r
2596--*/\r
2597;\r
2598\r
2599EFI_STATUS\r
2600ExecuteTransfer (\r
2601 IN USB2_HC_DEV *HcDev,\r
2602 IN BOOLEAN IsControl,\r
2603 IN EHCI_QH_ENTITY *QhPtr,\r
2604 IN OUT UINTN *ActualLen,\r
2605 OUT UINT8 *DataToggle,\r
2606 IN UINTN TimeOut,\r
2607 OUT UINT32 *TransferResult\r
2608 )\r
2609/*++\r
2610\r
2611Routine Description:\r
2612\r
2613 Execute Bulk or SyncInterrupt Transfer\r
2614\r
2615Arguments:\r
2616\r
2617 HcDev - USB2_HC_DEV\r
2618 IsControl - Is control transfer or not\r
2619 QhPtr - A pointer to Qh\r
2620 ActualLen - Actual transfered Len \r
2621 DataToggle - Data Toggle\r
2622 TimeOut - TimeOut threshold\r
2623 TransferResult - Transfer result\r
2624 \r
2625Returns:\r
2626\r
2627 EFI_SUCCESS Sucess\r
2628 EFI_DEVICE_ERROR Error\r
2629 \r
2630--*/\r
2631;\r
2632\r
2633BOOLEAN\r
2634CheckQtdsTransferResult (\r
2635 IN BOOLEAN IsControl,\r
2636 IN EHCI_QH_ENTITY *QhPtr,\r
2637 OUT UINT32 *Result,\r
2638 OUT UINTN *ErrQtdPos,\r
2639 OUT UINTN *ActualLen\r
2640 )\r
2641/*++\r
2642\r
2643Routine Description:\r
2644\r
2645 Check transfer result of Qtds\r
2646\r
2647Arguments:\r
2648\r
2649 IsControl - Is control transfer or not\r
2650 QhPtr - A pointer to Qh\r
2651 Result - Transfer result\r
2652 ErrQtdPos - Error TD Position\r
2653 ActualLen - Actual Transfer Size\r
2654\r
2655Returns:\r
2656\r
2657 TRUE Qtds finished\r
2658 FALSE Not finish\r
2659 \r
2660--*/\r
2661;\r
2662\r
2663EFI_STATUS\r
2664AsyncRequestMoniter (\r
2665 IN EFI_EVENT Event,\r
2666 IN VOID *Context\r
2667 )\r
2668/*++\r
2669\r
2670Routine Description:\r
2671 \r
2672 Interrupt transfer periodic check handler\r
2673 \r
2674Arguments:\r
2675\r
2676 Event - Interrupt event\r
2677 Context - Pointer to USB2_HC_DEV\r
2678 \r
2679Returns:\r
2680 \r
2681 EFI_SUCCESS Success\r
2682 EFI_DEVICE_ERROR Fail\r
2683 \r
2684--*/\r
2685;\r
2686\r
2687#endif\r
EFI Development Kit II mirror for PVE