]> git.proxmox.com Git - mirror_edk2.git/blame - EdkModulePkg/Bus/Pci/Ehci/Dxe/Ehci.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Remove two global variable: mUsbCapabilityLen and mDeviceSpeed and integrate them...
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
CommitLineData
562d2849 1/*++\r
2\r
3Copyright (c) 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 Ehci.h\r
15 \r
16Abstract: \r
17 \r
18\r
19Revision History\r
20--*/\r
21\r
22#ifndef _EHCI_H\r
23#define _EHCI_H\r
24\r
25//\r
26// Universal Host Controller Interface data structures and defines\r
27//\r
28#include <IndustryStandard/pci22.h>\r
29\r
71a62114 30\r
713ace4c 31extern UINTN gEHCDebugLevel;\r
32extern UINTN gEHCErrorLevel;\r
71a62114 33\r
562d2849 34\r
35#define STALL_1_MACRO_SECOND 1\r
36#define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND\r
37#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r
38\r
39#define SETUP_PACKET_PID_CODE 0x02\r
40#define INPUT_PACKET_PID_CODE 0x01\r
41#define OUTPUT_PACKET_PID_CODE 0x0\r
42\r
43#define ITD_SELECT_TYPE 0x0\r
44#define QH_SELECT_TYPE 0x01\r
45#define SITD_SELECT_TYPE 0x02\r
46#define FSTN_SELECT_TYPE 0x03\r
47\r
48#define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND\r
49#define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND\r
50#define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND\r
51#define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND\r
52#define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND\r
53#define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND\r
54\r
55#define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */\r
56\r
57#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1\r
58\r
59#define EHCI_MIN_PACKET_SIZE 8\r
60#define EHCI_MAX_PACKET_SIZE 1024\r
61#define EHCI_MAX_FRAME_LIST_LENGTH 1024\r
62#define EHCI_BLOCK_SIZE_WITH_TT 64\r
63#define EHCI_BLOCK_SIZE 512\r
64#define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)\r
65\r
66#define NAK_COUNT_RELOAD 3\r
67#define QTD_ERROR_COUNTER 1\r
68#define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1\r
69\r
70#define QTD_STATUS_ACTIVE 0x80\r
71#define QTD_STATUS_HALTED 0x40\r
72#define QTD_STATUS_BUFFER_ERR 0x20\r
73#define QTD_STATUS_BABBLE_ERR 0x10\r
74#define QTD_STATUS_TRANSACTION_ERR 0x08\r
75#define QTD_STATUS_DO_STOP_SPLIT 0x02\r
76#define QTD_STATUS_DO_START_SPLIT 0\r
77#define QTD_STATUS_DO_PING 0x01\r
78#define QTD_STATUS_DO_OUT 0\r
79\r
80#define DATA0 0\r
81#define DATA1 1\r
82\r
83#define MICRO_FRAME_0_CHANNEL 0x01\r
84#define MICRO_FRAME_1_CHANNEL 0x02\r
85#define MICRO_FRAME_2_CHANNEL 0x04\r
86#define MICRO_FRAME_3_CHANNEL 0x08\r
87#define MICRO_FRAME_4_CHANNEL 0x10\r
88#define MICRO_FRAME_5_CHANNEL 0x20\r
89#define MICRO_FRAME_6_CHANNEL 0x40\r
90#define MICRO_FRAME_7_CHANNEL 0x80\r
91\r
92#define CONTROL_TRANSFER 0x01\r
93#define BULK_TRANSFER 0x02\r
94#define SYNC_INTERRUPT_TRANSFER 0x04\r
95#define ASYNC_INTERRUPT_TRANSFER 0x08\r
96#define SYNC_ISOCHRONOUS_TRANSFER 0x10\r
97#define ASYNC_ISOCHRONOUS_TRANSFER 0x20\r
98\r
99\r
100//\r
101// Enhanced Host Controller Registers definitions\r
102//\r
562d2849 103extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
104extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
105\r
106#define USBCMD 0x0 /* Command Register Offset 00-03h */\r
107#define USBCMD_RS 0x01 /* Run / Stop */\r
108#define USBCMD_HCRESET 0x02 /* Host controller reset */\r
109#define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */\r
110#define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */\r
111#define USBCMD_PSE 0x10 /* Periodic schedule enable */\r
112#define USBCMD_ASE 0x20 /* Asynchronous schedule enable */\r
113#define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */\r
114\r
115#define USBSTS 0x04 /* Statue Register Offset 04-07h */\r
116#define USBSTS_HSE 0x10 /* Host system error */\r
117#define USBSTS_IAA 0x20 /* Interrupt on async advance */\r
118#define USBSTS_HCH 0x1000 /* Host controller halted */\r
119#define USBSTS_PSS 0x4000 /* Periodic schedule status */\r
120#define USBSTS_ASS 0x8000 /* Asynchronous schedule status */\r
121\r
122#define USBINTR 0x08 /* Command Register Offset 08-0bh */\r
123\r
124#define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */\r
125\r
126#define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */\r
127\r
128#define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */\r
129\r
130#define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */\r
131\r
132#define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */\r
133#define CONFIGFLAG_CF 0x01 /* Configure Flag */\r
134\r
135#define PORTSC 0x44 /* Port Status/Control Offset 44-47h */\r
136#define PORTSC_CCS 0x01 /* Current Connect Status*/\r
137#define PORTSC_CSC 0x02 /* Connect Status Change */\r
138#define PORTSC_PED 0x04 /* Port Enable / Disable */\r
139#define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */\r
140#define PORTSC_OCA 0x10 /* Over current Active */\r
141#define PORTSC_OCC 0x20 /* Over current Change */\r
142#define PORTSC_FPR 0x40 /* Force Port Resume */\r
143#define PORTSC_SUSP 0x80 /* Port Suspend State */\r
144#define PORTSC_PR 0x100 /* Port Reset */\r
145#define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */\r
146#define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */\r
147#define PORTSC_PP 0x1000 /* Port Power */\r
148#define PORTSC_PO 0x2000 /* Port Owner */\r
149\r
150#define CAPLENGTH 0 /* Capability Register Length 00h */\r
151\r
152#define HCIVERSION 0x02 /* Interface Version Number 02-03h */\r
153\r
154#define HCSPARAMS 0x04 /* Structural Parameters 04-07h */\r
155#define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */\r
156\r
157#define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */\r
158#define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */\r
159#define HCCP_PFLF 0x02 /* Programmable Frame List Flag */\r
160#define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */\r
161\r
162#define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */\r
163\r
164#define CLASSC 0x09 /* Class Code 09-0bh */\r
165\r
166#define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */\r
167\r
168#define SBRN 0x60 /* Serial Bus Release Number 60h */\r
169\r
170#define FLADJ 0x61 /* Frame Length Adjustment Register 61h */\r
171\r
172#define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */\r
173\r
174//\r
175// PCI Configuration Registers\r
176//\r
177#define EHCI_PCI_CLASSC 0x09\r
178#define EHCI_PCI_MEMORY_BASE 0x10\r
179\r
180//\r
181// Memory Offset Registers\r
182//\r
183#define EHCI_MEMORY_CAPLENGTH 0x0\r
184#define EHCI_MEMORY_CONFIGFLAG 0x40\r
185\r
186//\r
187// USB Base Class Code,Sub-Class Code and Programming Interface\r
188//\r
189#define PCI_CLASSC_PI_EHCI 0x20\r
190\r
191#define SETUP_PACKET_ID 0x2D\r
192#define INPUT_PACKET_ID 0x69\r
193#define OUTPUT_PACKET_ID 0xE1\r
194#define ERROR_PACKET_ID 0x55\r
195\r
71a62114 196#define bit(a) (1 << (a))\r
197\r
198#define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))\r
199#define GET_32B_TO_63B(Addr) ((UINTN)RShiftU64((UINTN) Addr, 32) & (0xffffffff))\r
562d2849 200\r
201\r
202//\r
203// Ehci Data and Ctrl Structures\r
204//\r
205#pragma pack(1)\r
206\r
207typedef struct {\r
208 UINT8 PI;\r
209 UINT8 SubClassCode;\r
210 UINT8 BaseCode;\r
211} USB_CLASSC;\r
212\r
213typedef struct {\r
214 UINT32 NextQtdTerminate : 1;\r
215 UINT32 Rsvd1 : 4;\r
216 UINT32 NextQtdPointer : 27;\r
217\r
218 UINT32 AltNextQtdTerminate : 1;\r
219 UINT32 Rsvd2 : 4;\r
220 UINT32 AltNextQtdPointer : 27;\r
221\r
222 UINT32 Status : 8;\r
223 UINT32 PidCode : 2;\r
224 UINT32 ErrorCount : 2;\r
225 UINT32 CurrentPage : 3;\r
226 UINT32 InterruptOnComplete : 1;\r
227 UINT32 TotalBytes : 15;\r
228 UINT32 DataToggle : 1;\r
229\r
230 UINT32 CurrentOffset : 12;\r
231 UINT32 BufferPointer0 : 20;\r
232\r
233 UINT32 Rsvd3 : 12;\r
234 UINT32 BufferPointer1 : 20;\r
235\r
236 UINT32 Rsvd4 : 12;\r
237 UINT32 BufferPointer2 : 20;\r
238\r
239 UINT32 Rsvd5 : 12;\r
240 UINT32 BufferPointer3 : 20;\r
241\r
242 UINT32 Rsvd6 : 12;\r
243 UINT32 BufferPointer4 : 20;\r
244\r
245 UINT32 ExtBufferPointer0;\r
246 UINT32 ExtBufferPointer1;\r
247 UINT32 ExtBufferPointer2;\r
248 UINT32 ExtBufferPointer3;\r
249 UINT32 ExtBufferPointer4;\r
250} EHCI_QTD_HW;\r
251\r
252typedef struct {\r
253 UINT32 QhTerminate : 1;\r
254 UINT32 SelectType : 2;\r
255 UINT32 Rsvd1 : 2;\r
256 UINT32 QhHorizontalPointer : 27;\r
257\r
258 UINT32 DeviceAddr : 7;\r
259 UINT32 Inactive : 1;\r
260 UINT32 EndpointNum : 4;\r
261 UINT32 EndpointSpeed : 2;\r
262 UINT32 DataToggleControl : 1;\r
263 UINT32 HeadReclamationFlag : 1;\r
264 UINT32 MaxPacketLen : 11;\r
265 UINT32 ControlEndpointFlag : 1;\r
266 UINT32 NakCountReload : 4;\r
267\r
268 UINT32 InerruptScheduleMask : 8;\r
269 UINT32 SplitComletionMask : 8;\r
270 UINT32 HubAddr : 7;\r
271 UINT32 PortNum : 7;\r
272 UINT32 Multiplier : 2;\r
273\r
274 UINT32 Rsvd2 : 5;\r
275 UINT32 CurrentQtdPointer : 27;\r
276\r
277 UINT32 NextQtdTerminate : 1;\r
278 UINT32 Rsvd3 : 4;\r
279 UINT32 NextQtdPointer : 27;\r
280\r
281 UINT32 AltNextQtdTerminate : 1;\r
282 UINT32 NakCount : 4;\r
283 UINT32 AltNextQtdPointer : 27;\r
284\r
285 UINT32 Status : 8;\r
286 UINT32 PidCode : 2;\r
287 UINT32 ErrorCount : 2;\r
288 UINT32 CurrentPage : 3;\r
289 UINT32 InterruptOnComplete : 1;\r
290 UINT32 TotalBytes : 15;\r
291 UINT32 DataToggle : 1;\r
292\r
293 UINT32 CurrentOffset : 12;\r
294 UINT32 BufferPointer0 : 20;\r
295\r
296 UINT32 CompleteSplitMask : 8;\r
297 UINT32 Rsvd4 : 4;\r
298 UINT32 BufferPointer1 : 20;\r
299\r
300 UINT32 FrameTag : 5;\r
301 UINT32 SplitBytes : 7;\r
302 UINT32 BufferPointer2 : 20;\r
303\r
304 UINT32 Rsvd5 : 12;\r
305 UINT32 BufferPointer3 : 20;\r
306\r
307 UINT32 Rsvd6 : 12;\r
308 UINT32 BufferPointer4 : 20;\r
309\r
310 UINT32 ExtBufferPointer0;\r
311 UINT32 ExtBufferPointer1;\r
312 UINT32 ExtBufferPointer2;\r
313 UINT32 ExtBufferPointer3;\r
314 UINT32 ExtBufferPointer4;\r
315} EHCI_QH_HW;\r
316\r
317typedef struct {\r
318 UINT32 LinkTerminate : 1;\r
319 UINT32 SelectType : 2;\r
320 UINT32 Rsvd : 2;\r
321 UINT32 LinkPointer : 27;\r
322} FRAME_LIST_ENTRY;\r
323\r
324#pragma pack()\r
325\r
326typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;\r
327typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;\r
328typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;\r
329\r
ffac4bcb 330struct _EHCI_QTD_ENTITY {\r
562d2849 331 EHCI_QTD_HW Qtd;\r
332 UINT32 TotalBytes;\r
333 UINT32 StaticTotalBytes;\r
334 UINT32 StaticCurrentOffset;\r
335 EHCI_QTD_ENTITY *Prev;\r
336 EHCI_QTD_ENTITY *Next;\r
337 EHCI_QTD_ENTITY *AltNext;\r
338 EHCI_QH_ENTITY *SelfQh;\r
ffac4bcb 339};\r
562d2849 340\r
ffac4bcb 341struct _EHCI_QH_ENTITY {\r
562d2849 342 EHCI_QH_HW Qh;\r
343 EHCI_QH_ENTITY *Next;\r
344 EHCI_QH_ENTITY *Prev;\r
345 EHCI_QTD_ENTITY *FirstQtdPtr;\r
346 EHCI_QTD_ENTITY *LastQtdPtr;\r
347 EHCI_QTD_ENTITY *AltQtdPtr;\r
348 UINTN Interval;\r
349 UINT8 TransferType;\r
ffac4bcb 350};\r
562d2849 351\r
352#define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)\r
353#define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)\r
354\r
355\r
356//\r
357// Ehci Managment Structures\r
358//\r
359#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
360\r
361#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
362\r
ffac4bcb 363struct _EHCI_ASYNC_REQUEST {\r
562d2849 364 UINT8 TransferType;\r
365 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;\r
366 VOID *Context;\r
367 EHCI_ASYNC_REQUEST *Prev;\r
368 EHCI_ASYNC_REQUEST *Next;\r
369 EHCI_QH_ENTITY *QhPtr;\r
ffac4bcb 370};\r
562d2849 371\r
372typedef struct _MEMORY_MANAGE_HEADER {\r
373 UINT8 *BitArrayPtr;\r
374 UINTN BitArraySizeInBytes;\r
375 UINT8 *MemoryBlockPtr;\r
376 UINTN MemoryBlockSizeInBytes;\r
377 VOID *Mapping;\r
378 struct _MEMORY_MANAGE_HEADER *Next;\r
379} MEMORY_MANAGE_HEADER;\r
380\r
381typedef struct _USB2_HC_DEV {\r
382 UINTN Signature;\r
383 EFI_PCI_IO_PROTOCOL *PciIo;\r
384 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
385 UINTN PeriodicFrameListLength;\r
386 VOID *PeriodicFrameListBuffer;\r
387 VOID *PeriodicFrameListMap;\r
388 VOID *AsyncList;\r
389 EHCI_ASYNC_REQUEST *AsyncRequestList;\r
390 EFI_EVENT AsyncRequestEvent;\r
391 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
392 MEMORY_MANAGE_HEADER *MemoryHeader;\r
393 UINT8 Is64BitCapable;\r
394 UINT32 High32BitAddr;\r
37279806 395 UINT32 UsbCapabilityLen;\r
396 UINT16 DeviceSpeed[16];\r
562d2849 397} USB2_HC_DEV;\r
398\r
399\r
400//\r
401// Internal Functions Declaration\r
402//\r
403\r
404//\r
405// EhciMem Functions\r
406//\r
407EFI_STATUS\r
408CreateMemoryBlock (\r
409 IN USB2_HC_DEV *HcDev,\r
410 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
411 IN UINTN MemoryBlockSizeInPages\r
412 )\r
413/*++\r
414\r
415Routine Description:\r
416\r
417 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,\r
418 and use PciIo->Map to map the common buffer for Bus Master Read/Write.\r
419\r
420Arguments:\r
421\r
422 HcDev - USB2_HC_DEV\r
423 MemoryHeader - MEMORY_MANAGE_HEADER to output\r
424 MemoryBlockSizeInPages - MemoryBlockSizeInPages\r
425 \r
426Returns:\r
427\r
428 EFI_SUCCESS Success\r
429 EFI_OUT_OF_RESOURCES Fail for no resources\r
430 EFI_UNSUPPORTED Unsupported currently\r
431 \r
432--*/\r
433;\r
434\r
435EFI_STATUS\r
436FreeMemoryHeader (\r
437 IN USB2_HC_DEV *HcDev,\r
438 IN MEMORY_MANAGE_HEADER *MemoryHeader\r
439 )\r
440/*++\r
441\r
442Routine Description:\r
443\r
444 Free Memory Header\r
445\r
446Arguments:\r
447\r
448 HcDev - USB2_HC_DEV\r
449 MemoryHeader - MemoryHeader to be freed\r
450\r
451Returns:\r
452\r
453 EFI_SUCCESS Success\r
454 EFI_INVALID_PARAMETER Parameter is error\r
455\r
456--*/\r
457;\r
458\r
459VOID\r
460InsertMemoryHeaderToList (\r
461 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
462 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
463 )\r
464/*++\r
465\r
466Routine Description:\r
467\r
468 Insert Memory Header To List\r
469\r
470Arguments:\r
471\r
472 MemoryHeader - MEMORY_MANAGE_HEADER\r
473 NewMemoryHeader - MEMORY_MANAGE_HEADER\r
474\r
475Returns:\r
476\r
477 VOID\r
478\r
479--*/\r
480;\r
481\r
482EFI_STATUS\r
483AllocMemInMemoryBlock (\r
484 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
485 OUT VOID **Pool,\r
486 IN UINTN NumberOfMemoryUnit\r
487 )\r
488/*++\r
489\r
490Routine Description:\r
491\r
492 Alloc Memory In MemoryBlock\r
493\r
494Arguments:\r
495\r
496 MemoryHeader - MEMORY_MANAGE_HEADER\r
497 Pool - Place to store pointer to memory\r
498 NumberOfMemoryUnit - Number Of Memory Unit\r
499\r
500Returns:\r
501\r
502 EFI_SUCCESS Success\r
503 EFI_NOT_FOUND Can't find the free memory \r
504\r
505--*/\r
506;\r
507\r
508BOOLEAN\r
509IsMemoryBlockEmptied (\r
510 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
511 )\r
512/*++\r
513\r
514Routine Description:\r
515\r
516 Is Memory Block Emptied\r
517\r
518Arguments:\r
519\r
520 MemoryHeaderPtr - MEMORY_MANAGE_HEADER\r
521\r
522Returns:\r
523\r
524 TRUE Empty\r
525 FALSE Not Empty \r
526\r
527--*/\r
528;\r
529\r
530VOID\r
531DelinkMemoryBlock (\r
532 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
533 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader\r
534 )\r
535/*++\r
536\r
537Routine Description:\r
538\r
539 Delink Memory Block\r
540\r
541Arguments:\r
542\r
543 FirstMemoryHeader - MEMORY_MANAGE_HEADER\r
544 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER\r
545\r
546Returns:\r
547\r
548 VOID\r
549\r
550--*/\r
551;\r
552\r
553EFI_STATUS\r
554InitialMemoryManagement (\r
555 IN USB2_HC_DEV *HcDev\r
556 )\r
557/*++\r
558\r
559Routine Description:\r
560\r
561 Initialize Memory Management\r
562\r
563Arguments:\r
564\r
565 HcDev - USB2_HC_DEV\r
566\r
567Returns:\r
568\r
569 EFI_SUCCESS Success\r
570 EFI_DEVICE_ERROR Fail\r
571\r
572--*/\r
573;\r
574\r
575EFI_STATUS\r
576DeinitialMemoryManagement (\r
577 IN USB2_HC_DEV *HcDev\r
578 )\r
579/*++\r
580\r
581Routine Description:\r
582\r
583 Deinitialize Memory Management\r
584\r
585Arguments:\r
586\r
587 HcDev - USB2_HC_DEV\r
588\r
589Returns:\r
590\r
591 EFI_SUCCESS Success\r
592 EFI_DEVICE_ERROR Fail\r
593 \r
594--*/\r
595;\r
596\r
597EFI_STATUS\r
598EhciAllocatePool (\r
599 IN USB2_HC_DEV *HcDev,\r
600 OUT UINT8 **Pool,\r
601 IN UINTN AllocSize\r
602 )\r
603/*++\r
604\r
605Routine Description:\r
606\r
607 Ehci Allocate Pool\r
608\r
609Arguments:\r
610\r
611 HcDev - USB2_HC_DEV\r
612 Pool - Place to store pointer to the memory buffer\r
613 AllocSize - Alloc Size\r
614\r
615Returns:\r
616\r
617 EFI_SUCCESS Success\r
618 EFI_DEVICE_ERROR Fail\r
619 \r
620--*/\r
621;\r
622\r
623VOID\r
624EhciFreePool (\r
625 IN USB2_HC_DEV *HcDev,\r
626 IN UINT8 *Pool,\r
627 IN UINTN AllocSize\r
628 )\r
629/*++\r
630\r
631Routine Description:\r
632\r
633 Uhci Free Pool\r
634\r
635Arguments:\r
636\r
637 HcDev - USB_HC_DEV\r
638 Pool - Pool to free\r
639 AllocSize - Pool size\r
640\r
641Returns:\r
642\r
643 VOID\r
644\r
645--*/\r
646;\r
647\r
648//\r
649// EhciReg Functions\r
650//\r
651EFI_STATUS\r
652ReadEhcCapabiltiyReg (\r
653 IN USB2_HC_DEV *HcDev,\r
654 IN UINT32 CapabiltiyRegAddr,\r
655 IN OUT UINT32 *Data\r
656 )\r
657/*++\r
658\r
659Routine Description:\r
660\r
661 Read Ehc Capabitlity register\r
662 \r
663Arguments:\r
664\r
665 HcDev - USB2_HC_DEV \r
666 CapabiltiyRegAddr - Ehc Capability register address\r
667 Data - A pointer to data read from register\r
668 \r
669Returns:\r
670\r
671 EFI_SUCCESS Success\r
672 EFI_DEVICE_ERROR Fail\r
673 \r
674--*/\r
675;\r
676\r
677EFI_STATUS\r
678ReadEhcOperationalReg (\r
679 IN USB2_HC_DEV *HcDev,\r
680 IN UINT32 OperationalRegAddr,\r
681 IN OUT UINT32 *Data\r
682 )\r
683/*++\r
684\r
685Routine Description:\r
686\r
687 Read Ehc Operation register\r
688 \r
689Arguments:\r
690\r
691 HcDev - USB2_HC_DEV \r
692 OperationalRegAddr - Ehc Operation register address\r
693 Data - A pointer to data read from register\r
694 \r
695Returns:\r
696\r
697 EFI_SUCCESS Success\r
698 EFI_DEVICE_ERROR Fail\r
699 \r
700--*/\r
701;\r
702\r
703EFI_STATUS\r
704WriteEhcOperationalReg (\r
705 IN USB2_HC_DEV *HcDev,\r
706 IN UINT32 OperationalRegAddr,\r
707 IN UINT32 Data\r
708 )\r
709/*++\r
710\r
711Routine Description:\r
712\r
713 Write Ehc Operation register\r
714 \r
715Arguments:\r
716\r
717 HcDev - USB2_HC_DEV \r
718 OperationalRegAddr - Ehc Operation register address\r
719 Data - 32bit write to register\r
720 \r
721Returns:\r
722\r
723 EFI_SUCCESS Success\r
724 EFI_DEVICE_ERROR Fail\r
725 \r
726--*/\r
727;\r
728\r
729EFI_STATUS\r
730SetEhcDoorbell (\r
731 IN USB2_HC_DEV *HcDev\r
732 )\r
733/*++\r
734\r
735Routine Description:\r
736\r
737 Set Ehc door bell bit\r
738 \r
739Arguments:\r
740\r
741 HcDev - USB2_HC_DEV \r
742 \r
743Returns:\r
744\r
745 EFI_SUCCESS Success\r
746 EFI_DEVICE_ERROR Fail\r
747 \r
748--*/\r
749;\r
750\r
751EFI_STATUS\r
752SetFrameListLen (\r
753 IN USB2_HC_DEV *HcDev,\r
754 IN UINTN Length\r
755 )\r
756/*++\r
757\r
758Routine Description:\r
759\r
760 Set the length of Frame List\r
761 \r
762Arguments:\r
763\r
764 HcDev - USB2_HC_DEV \r
765 Length - the required length of frame list\r
766 \r
767Returns:\r
768\r
769 EFI_SUCCESS Success\r
770 EFI_INVALID_PARAMETER Invalid parameter\r
771 EFI_DEVICE_ERROR Fail\r
772 \r
773--*/\r
774;\r
775\r
776BOOLEAN\r
777IsFrameListProgrammable (\r
778 IN USB2_HC_DEV *HcDev\r
779 )\r
780/*++\r
781\r
782Routine Description:\r
783\r
784 Whether frame list is programmable\r
785 \r
786Arguments:\r
787\r
788 HcDev - USB2_HC_DEV \r
789 \r
790Returns:\r
791\r
792 TRUE Programmable\r
793 FALSE Unprogrammable\r
794 \r
795--*/\r
796;\r
797\r
798BOOLEAN\r
799IsPeriodicScheduleEnabled (\r
800 IN USB2_HC_DEV *HcDev\r
801 )\r
802/*++\r
803\r
804Routine Description:\r
805\r
806 Whether periodic schedule is enabled\r
807 \r
808Arguments:\r
809\r
810 HcDev - USB2_HC_DEV \r
811 \r
812Returns:\r
813\r
814 TRUE Enabled\r
815 FALSE Disabled\r
816 \r
817--*/\r
818;\r
819\r
820BOOLEAN\r
821IsAsyncScheduleEnabled (\r
822 IN USB2_HC_DEV *HcDev\r
823 )\r
824/*++\r
825\r
826Routine Description:\r
827\r
828 Whether asynchronous schedule is enabled\r
829 \r
830Arguments:\r
831\r
832 HcDev - USB2_HC_DEV \r
833 \r
834Returns:\r
835\r
836 TRUE Enabled\r
837 FALSE Disabled\r
838 \r
839--*/\r
840;\r
841\r
842BOOLEAN\r
843IsEhcPortEnabled (\r
844 IN USB2_HC_DEV *HcDev,\r
845 IN UINT8 PortNum\r
846 )\r
847/*++\r
848\r
849Routine Description:\r
850\r
851 Whether port is enabled\r
852 \r
853Arguments:\r
854\r
855 HcDev - USB2_HC_DEV \r
856 \r
857Returns:\r
858\r
859 TRUE Enabled\r
860 FALSE Disabled\r
861 \r
862--*/\r
863;\r
864\r
865BOOLEAN\r
866IsEhcReseted (\r
867 IN USB2_HC_DEV *HcDev\r
868 )\r
869/*++\r
870\r
871Routine Description:\r
872\r
873 Whether Ehc is halted\r
874 \r
875Arguments:\r
876\r
877 HcDev - USB2_HC_DEV \r
878 \r
879Returns:\r
880\r
881 TRUE Reseted\r
882 FALSE Unreseted\r
883 \r
884--*/\r
885;\r
886\r
887BOOLEAN\r
888IsEhcHalted (\r
889 IN USB2_HC_DEV *HcDev\r
890 )\r
891/*++\r
892\r
893Routine Description:\r
894\r
895 Whether Ehc is halted\r
896 \r
897Arguments:\r
898\r
899 HcDev - USB2_HC_DEV \r
900 \r
901Returns:\r
902\r
903 TRUE Halted\r
904 FALSE Not halted\r
905 \r
906--*/\r
907;\r
908\r
909BOOLEAN\r
910IsEhcSysError (\r
911 IN USB2_HC_DEV *HcDev\r
912 )\r
913/*++\r
914\r
915Routine Description:\r
916\r
917 Whether Ehc is system error\r
918 \r
919Arguments:\r
920\r
921 HcDev - USB2_HC_DEV \r
922 \r
923Returns:\r
924\r
925 TRUE System error\r
926 FALSE No system error\r
927 \r
928--*/\r
929;\r
930\r
931BOOLEAN\r
932IsHighSpeedDevice (\r
933 IN EFI_USB2_HC_PROTOCOL *This,\r
934 IN UINT8 PortNum \r
935 )\r
936/*++\r
937\r
938Routine Description:\r
939\r
940 Whether high speed device attached\r
941 \r
942Arguments:\r
943\r
944 HcDev - USB2_HC_DEV \r
945 \r
946Returns:\r
947\r
948 TRUE High speed\r
949 FALSE Full speed\r
950 \r
951--*/\r
952;\r
953\r
954EFI_STATUS\r
955WaitForEhcReset (\r
956 IN USB2_HC_DEV *HcDev,\r
957 IN UINTN Timeout\r
958 )\r
959/*++\r
960\r
961Routine Description:\r
962\r
963 wait for Ehc reset or timeout\r
964 \r
965Arguments:\r
966\r
967 HcDev - USB2_HC_DEV \r
968 Timeout - timeout threshold\r
969 \r
970Returns:\r
971\r
972 EFI_SUCCESS Success\r
973 EFI_TIMEOUT Timeout\r
974 \r
975--*/\r
976;\r
977\r
978EFI_STATUS\r
979WaitForEhcHalt (\r
980 IN USB2_HC_DEV *HcDev,\r
981 IN UINTN Timeout\r
982 )\r
983/*++\r
984\r
985Routine Description:\r
986\r
987 wait for Ehc halt or timeout\r
988 \r
989Arguments:\r
990\r
991 HcDev - USB2_HC_DEV \r
992 Timeout - timeout threshold\r
993 \r
994Returns:\r
995\r
996 EFI_SUCCESS Success\r
997 EFI_TIMEOUT Timeout\r
998 \r
999--*/\r
1000;\r
1001\r
1002EFI_STATUS\r
1003WaitForEhcNotHalt (\r
1004 IN USB2_HC_DEV *HcDev,\r
1005 IN UINTN Timeout\r
1006 )\r
1007/*++\r
1008\r
1009Routine Description:\r
1010\r
1011 wait for Ehc not halt or timeout\r
1012 \r
1013Arguments:\r
1014\r
1015 HcDev - USB2_HC_DEV \r
1016 Timeout - timeout threshold\r
1017 \r
1018Returns:\r
1019\r
1020 EFI_SUCCESS Success\r
1021 EFI_TIMEOUT Timeout\r
1022 \r
1023--*/\r
1024;\r
1025\r
1026EFI_STATUS\r
1027WaitForEhcDoorbell (\r
1028 IN USB2_HC_DEV *HcDev,\r
1029 IN UINTN Timeout\r
1030 )\r
1031/*++\r
1032\r
1033Routine Description:\r
1034\r
1035 Wait for periodic schedule disable or timeout\r
1036\r
1037Arguments:\r
1038\r
1039 HcDev - USB2_HC_DEV \r
1040 Timeout - timeout threshold\r
1041\r
1042Returns:\r
1043\r
1044 EFI_SUCCESS Success\r
1045 EFI_TIMEOUT Timeout\r
1046 \r
1047--*/\r
1048;\r
1049\r
1050EFI_STATUS\r
1051WaitForAsyncScheduleEnable (\r
1052 IN USB2_HC_DEV *HcDev,\r
1053 IN UINTN Timeout\r
1054 )\r
1055/*++\r
1056\r
1057Routine Description:\r
1058\r
1059 Wait for Ehc asynchronous schedule enable or timeout\r
1060 \r
1061Arguments:\r
1062\r
1063 HcDev - USB2_HC_DEV \r
1064 Timeout - timeout threshold\r
1065 \r
1066Returns:\r
1067\r
1068 EFI_SUCCESS Success\r
1069 EFI_TIMEOUT Timeout\r
1070 \r
1071--*/\r
1072;\r
1073\r
1074EFI_STATUS\r
1075WaitForAsyncScheduleDisable (\r
1076 IN USB2_HC_DEV *HcDev,\r
1077 IN UINTN Timeout\r
1078 )\r
1079/*++\r
1080\r
1081Routine Description:\r
1082\r
1083 Wait for Ehc asynchronous schedule disable or timeout\r
1084 \r
1085Arguments:\r
1086\r
1087 HcDev - USB2_HC_DEV \r
1088 Timeout - timeout threshold\r
1089 \r
1090Returns:\r
1091\r
1092 EFI_SUCCESS Success\r
1093 EFI_TIMEOUT Timeout\r
1094 \r
1095--*/\r
1096;\r
1097\r
1098EFI_STATUS\r
1099WaitForPeriodicScheduleEnable (\r
1100 IN USB2_HC_DEV *HcDev,\r
1101 IN UINTN Timeout\r
1102 )\r
1103/*++\r
1104\r
1105Routine Description:\r
1106\r
1107 Wait for Ehc periodic schedule enable or timeout\r
1108 \r
1109Arguments:\r
1110\r
1111 HcDev - USB2_HC_DEV \r
1112 Timeout - timeout threshold\r
1113 \r
1114Returns:\r
1115\r
1116 EFI_SUCCESS Success\r
1117 EFI_TIMEOUT Timeout\r
1118 \r
1119--*/\r
1120;\r
1121\r
1122EFI_STATUS\r
1123WaitForPeriodicScheduleDisable (\r
1124 IN USB2_HC_DEV *HcDev,\r
1125 IN UINTN Timeout\r
1126 )\r
1127/*++\r
1128\r
1129Routine Description:\r
1130\r
1131 Wait for periodic schedule disable or timeout\r
1132 \r
1133Arguments:\r
1134\r
1135 HcDev - USB2_HC_DEV \r
1136 Timeout - timeout threshold\r
1137 \r
1138Returns:\r
1139\r
1140 EFI_SUCCESS Success\r
1141 EFI_TIMEOUT Timeout\r
1142 \r
1143--*/\r
1144;\r
1145\r
1146EFI_STATUS\r
1147GetCapabilityLen (\r
1148 IN USB2_HC_DEV *HcDev\r
1149 )\r
1150/*++\r
1151\r
1152Routine Description:\r
1153\r
1154 Get the length of capability register\r
1155 \r
1156Arguments:\r
1157\r
1158 HcDev - USB2_HC_DEV \r
1159 \r
1160Returns:\r
1161\r
1162 EFI_SUCCESS Success\r
1163 EFI_DEVICE_ERROR Fail\r
1164 \r
1165--*/\r
1166;\r
1167\r
1168EFI_STATUS\r
1169SetFrameListBaseAddr (\r
1170 IN USB2_HC_DEV *HcDev,\r
1171 IN UINT32 FrameBuffer\r
1172 )\r
1173/*++\r
1174\r
1175Routine Description:\r
1176\r
1177 Set base address of frame list first entry\r
1178 \r
1179Arguments:\r
1180\r
1181 HcDev - USB2_HC_DEV \r
1182 FrameBuffer - base address of first entry of frame list\r
1183 \r
1184Returns:\r
1185\r
1186 EFI_SUCCESS Success\r
1187 EFI_DEVICE_ERROR Fail\r
1188 \r
1189--*/\r
1190;\r
1191\r
1192EFI_STATUS\r
1193SetAsyncListAddr (\r
1194 IN USB2_HC_DEV *HcDev,\r
1195 IN EHCI_QH_ENTITY *QhPtr\r
1196 )\r
1197/*++\r
1198\r
1199Routine Description:\r
1200\r
1201 Set address of first Async schedule Qh\r
1202 \r
1203Arguments:\r
1204\r
1205 HcDev - USB2_HC_DEV \r
1206 QhPtr - A pointer to first Qh in the Async schedule\r
1207 \r
1208Returns:\r
1209\r
1210 EFI_SUCCESS Success\r
1211 EFI_DEVICE_ERROR Fail\r
1212 \r
1213--*/\r
1214;\r
1215\r
1216EFI_STATUS\r
1217SetCtrlDataStructSeg (\r
1218 IN USB2_HC_DEV *HcDev\r
1219 )\r
1220/*++\r
1221\r
1222Routine Description:\r
1223\r
1224 Set address of first Async schedule Qh\r
1225 \r
1226Arguments:\r
1227\r
1228 HcDev - USB2_HC_DEV \r
1229 QhPtr - A pointer to first Qh in the Async schedule\r
1230 \r
1231Returns:\r
1232\r
1233 EFI_SUCCESS Success\r
1234 EFI_DEVICE_ERROR Fail\r
1235 \r
1236--*/\r
1237;\r
1238\r
1239EFI_STATUS\r
1240SetPortRoutingEhc (\r
1241 IN USB2_HC_DEV *HcDev\r
1242 )\r
1243/*++\r
1244\r
1245Routine Description:\r
1246\r
1247 Set Ehc port routing bit\r
1248 \r
1249Arguments:\r
1250\r
1251 HcDev - USB2_HC_DEV \r
1252 \r
1253Returns:\r
1254\r
1255 EFI_SUCCESS Success\r
1256 EFI_DEVICE_ERROR Fail\r
1257 \r
1258--*/\r
1259;\r
1260\r
1261EFI_STATUS\r
1262EnablePeriodicSchedule (\r
1263 IN USB2_HC_DEV *HcDev\r
1264 )\r
1265/*++\r
1266\r
1267Routine Description:\r
1268\r
1269 Enable periodic schedule\r
1270 \r
1271Arguments:\r
1272\r
1273 HcDev - USB2_HC_DEV \r
1274 \r
1275Returns:\r
1276\r
1277 EFI_SUCCESS Success\r
1278 EFI_DEVICE_ERROR Fail\r
1279 \r
1280--*/\r
1281;\r
1282\r
1283EFI_STATUS\r
1284DisablePeriodicSchedule (\r
1285 IN USB2_HC_DEV *HcDev\r
1286 )\r
1287/*++\r
1288\r
1289Routine Description:\r
1290\r
1291 Disable periodic schedule\r
1292 \r
1293Arguments:\r
1294\r
1295 HcDev - USB2_HC_DEV \r
1296 \r
1297Returns:\r
1298\r
1299 EFI_SUCCESS Success\r
1300 EFI_DEVICE_ERROR Fail\r
1301 \r
1302--*/\r
1303;\r
1304\r
1305EFI_STATUS\r
1306EnableAsynchronousSchedule (\r
1307 IN USB2_HC_DEV *HcDev\r
1308 )\r
1309/*++\r
1310\r
1311Routine Description:\r
1312\r
1313 Enable asynchrounous schedule\r
1314 \r
1315Arguments:\r
1316\r
1317 HcDev - USB2_HC_DEV \r
1318 \r
1319Returns:\r\r
1320\r
1321 EFI_SUCCESS Success\r
1322 EFI_DEVICE_ERROR Fail\r
1323 \r
1324--*/\r
1325;\r
1326\r
1327EFI_STATUS\r
1328DisableAsynchronousSchedule (\r
1329 IN USB2_HC_DEV *HcDev\r
1330 )\r
1331/*++\r
1332\r
1333Routine Description:\r
1334\r
1335 Disable asynchrounous schedule\r
1336 \r
1337Arguments:\r
1338\r
1339 HcDev - USB2_HC_DEV \r
1340 \r
1341Returns:\r
1342\r
1343 EFI_SUCCESS Success\r
1344 EFI_DEVICE_ERROR Fail\r
1345 \r
1346--*/\r
1347;\r
1348\r
1349EFI_STATUS\r
1350StartScheduleExecution (\r
1351 IN USB2_HC_DEV *HcDev\r
1352 )\r
1353/*++\r
1354\r
1355Routine Description:\r
1356\r
1357 Start Ehc schedule execution\r
1358 \r
1359Arguments:\r
1360\r
1361 HcDev - USB2_HC_DEV \r
1362 \r
1363Returns:\r
1364\r
1365 EFI_SUCCESS Success\r
1366 EFI_DEVICE_ERROR Fail\r
1367 \r
1368--*/\r
1369;\r
1370\r
1371EFI_STATUS\r
1372ResetEhc (\r
1373 IN USB2_HC_DEV *HcDev\r
1374 )\r
1375/*++\r
1376\r
1377Routine Description:\r
1378\r
1379 Reset Ehc\r
1380 \r
1381Arguments:\r
1382\r
1383 HcDev - USB2_HC_DEV \r
1384 \r
1385Returns:\r
1386\r
1387 EFI_SUCCESS Success\r
1388 EFI_DEVICE_ERROR Fail\r
1389 \r
1390--*/\r
1391;\r
1392\r
1393EFI_STATUS\r
1394ClearEhcAllStatus (\r
1395 IN USB2_HC_DEV *HcDev\r
1396 )\r
1397/*++\r
1398\r
1399Routine Description:\r
1400\r
1401 Clear Ehc all status bits\r
1402 \r
1403Arguments:\r
1404\r
1405 HcDev - USB2_HC_DEV \r
1406 \r
1407Returns:\r
1408\r
1409 EFI_SUCCESS Success\r
1410 EFI_DEVICE_ERROR Fail\r
1411 \r
1412--*/\r
1413;\r
1414\r
1415//\r
1416// EhciSched Functions\r
1417//\r
1418EFI_STATUS\r
1419InitialPeriodicFrameList (\r
1420 IN USB2_HC_DEV *HcDev,\r
1421 IN UINTN Length\r
1422 )\r
1423/*++\r
1424\r
1425Routine Description:\r
1426\r
1427 Initialize Periodic Schedule Frame List\r
1428\r
1429Arguments:\r
1430\r
1431 HcDev - USB2_HC_DEV\r
1432 Length - Frame List Length\r
1433 \r
1434Returns:\r
1435\r
1436 EFI_SUCCESS Success\r
1437 EFI_DEVICE_ERROR Fail\r
1438 \r
1439--*/\r
1440;\r
1441\r
1442VOID\r
1443DeinitialPeriodicFrameList (\r
1444 IN USB2_HC_DEV *HcDev\r
1445 )\r
1446/*++\r
1447\r
1448Routine Description:\r
1449\r
1450 Deinitialize Periodic Schedule Frame List\r
1451\r
1452Arguments:\r
1453\r
1454 HcDev - USB2_HC_DEV\r
1455\r
1456Returns:\r
1457\r
1458 VOID\r
1459 \r
1460--*/\r
1461;\r
1462\r
1463EFI_STATUS\r
1464CreatePollingTimer (\r
1465 IN USB2_HC_DEV *HcDev,\r
1466 IN EFI_EVENT_NOTIFY NotifyFunction\r
1467 )\r
1468/*++\r
1469\r
1470Routine Description:\r
1471\r
1472 Create Async Request Polling Timer\r
1473\r
1474Arguments:\r
1475\r
1476 HcDev - USB2_HC_DEV\r
1477 NotifyFunction - Timer Notify Function\r
1478 \r
1479Returns:\r
1480\r
1481 EFI_SUCCESS Success\r
1482 EFI_DEVICE_ERROR Fail\r
1483 \r
1484--*/\r
1485;\r
1486\r
1487EFI_STATUS\r
1488DestoryPollingTimer (\r
1489 IN USB2_HC_DEV *HcDev\r
1490 )\r
1491/*++\r
1492\r
1493Routine Description:\r
1494\r
1495 Destory Async Request Polling Timer\r
1496\r
1497Arguments:\r
1498\r
1499 HcDev - USB2_HC_DEV\r
1500 \r
1501Returns:\r
1502\r
1503 EFI_SUCCESS Success\r
1504 EFI_DEVICE_ERROR Fail\r
1505 \r
1506--*/\r
1507;\r
1508\r
1509EFI_STATUS\r
1510StartPollingTimer (\r
1511 IN USB2_HC_DEV *HcDev\r
1512 )\r
1513/*++\r
1514\r
1515Routine Description:\r
1516\r
1517 Start Async Request Polling Timer\r
1518\r
1519Arguments:\r
1520\r
1521 HcDev - USB2_HC_DEV\r
1522 \r
1523Returns:\r
1524\r
1525 EFI_SUCCESS Success\r
1526 EFI_DEVICE_ERROR Fail\r
1527 \r
1528--*/\r
1529;\r
1530\r
1531EFI_STATUS\r
1532StopPollingTimer (\r
1533 IN USB2_HC_DEV *HcDev\r
1534 )\r
1535/*++\r
1536\r
1537Routine Description:\r
1538\r
1539 Stop Async Request Polling Timer\r
1540\r
1541Arguments:\r
1542\r
1543 HcDev - USB2_HC_DEV\r
1544 \r
1545Returns:\r
1546\r
1547 EFI_SUCCESS Success\r
1548 EFI_DEVICE_ERROR Fail\r
1549 \r
1550--*/\r
1551;\r
1552\r
1553EFI_STATUS\r
1554CreateQh (\r
1555 IN USB2_HC_DEV *HcDev,\r
1556 IN UINT8 DeviceAddr,\r
1557 IN UINT8 Endpoint,\r
1558 IN UINT8 DeviceSpeed,\r
1559 IN UINTN MaxPacketLen,\r
1560 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1561 )\r
1562/*++\r
1563\r
1564Routine Description:\r
1565\r
1566 Create Qh Structure and Pre-Initialize\r
1567\r
1568Arguments:\r
1569\r
1570 HcDev - USB2_HC_DEV \r
1571 DeviceAddr - Address of Device\r
1572 Endpoint - Endpoint Number\r
1573 DeviceSpeed - Device Speed\r
1574 MaxPacketLen - Max Length of one Packet\r
1575 QhPtrPtr - A pointer of pointer to Qh for return\r
1576 \r
1577Returns:\r
1578\r
1579 EFI_SUCCESS Success\r
1580 EFI_DEVICE_ERROR Fail\r
1581 \r
1582--*/\r
1583;\r
1584\r
1585EFI_STATUS\r
1586CreateControlQh (\r
1587 IN USB2_HC_DEV *HcDev,\r
1588 IN UINT8 DeviceAddr,\r
1589 IN UINT8 DeviceSpeed,\r
1590 IN UINTN MaxPacketLen,\r
1591 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1592 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1593 )\r
1594/*++\r
1595\r
1596Routine Description:\r
1597\r
1598 Create Qh for Control Transfer\r
1599\r
1600Arguments:\r
1601\r
1602 HcDev - USB2_HC_DEV \r
1603 DeviceAddr - Address of Device\r
1604 DeviceSpeed - Device Speed\r
1605 MaxPacketLen - Max Length of one Packet\r
1606 Translator - Translator Transaction for SplitX\r
1607 QhPtrPtr - A pointer of pointer to Qh for return\r
1608 \r
1609Returns:\r
1610\r
1611 EFI_SUCCESS Success\r
1612 EFI_DEVICE_ERROR Fail\r
1613 \r
1614--*/\r
1615;\r
1616\r
1617EFI_STATUS\r
1618CreateBulkQh (\r
1619 IN USB2_HC_DEV *HcDev,\r
1620 IN UINT8 DeviceAddr,\r
1621 IN UINT8 EndPointAddr,\r
1622 IN UINT8 DeviceSpeed,\r
1623 IN UINT8 DataToggle,\r
1624 IN UINTN MaxPacketLen,\r
1625 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1626 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1627 )\r
1628/*++\r
1629\r
1630Routine Description:\r
1631\r
1632 Create Qh for Bulk Transfer\r
1633\r
1634Arguments:\r
1635\r
1636 HcDev - USB2_HC_DEV \r
1637 DeviceAddr - Address of Device\r
1638 EndPointAddr - Address of Endpoint\r
1639 DeviceSpeed - Device Speed\r
1640 MaxPacketLen - Max Length of one Packet\r
1641 Translator - Translator Transaction for SplitX\r
1642 QhPtrPtr - A pointer of pointer to Qh for return\r
1643 \r
1644Returns:\r
1645\r
1646 EFI_SUCCESS Success\r
1647 EFI_DEVICE_ERROR Fail\r
1648 \r
1649--*/\r
1650;\r
1651\r
1652EFI_STATUS\r
1653CreateInterruptQh (\r
1654 IN USB2_HC_DEV *HcDev,\r
1655 IN UINT8 DeviceAddr,\r
1656 IN UINT8 EndPointAddr,\r
1657 IN UINT8 DeviceSpeed,\r
1658 IN UINT8 DataToggle,\r
1659 IN UINTN MaxPacketLen,\r
1660 IN UINTN Interval,\r
1661 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1662 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1663 )\r
1664/*++\r
1665\r
1666Routine Description:\r
1667\r
1668 Create Qh for Control Transfer\r
1669\r
1670Arguments:\r
1671\r
1672 HcDev - USB2_HC_DEV \r
1673 DeviceAddr - Address of Device\r
1674 EndPointAddr - Address of Endpoint\r
1675 DeviceSpeed - Device Speed\r
1676 MaxPacketLen - Max Length of one Packet\r
1677 Interval - value of interval\r
1678 Translator - Translator Transaction for SplitX\r
1679 QhPtrPtr - A pointer of pointer to Qh for return\r
1680 \r
1681Returns:\r
1682\r
1683 EFI_SUCCESS Success\r
1684 EFI_DEVICE_ERROR Fail\r
1685 \r
1686--*/\r
1687;\r
1688\r
1689VOID\r
1690DestoryQh (\r
1691 IN USB2_HC_DEV *HcDev,\r
1692 IN EHCI_QH_ENTITY *QhPtr\r
1693 )\r
1694/*++\r
1695\r
1696Routine Description:\r
1697\r
1698 Destory Qh Structure \r
1699 \r
1700Arguments:\r
1701\r
1702 HcDev - USB2_HC_DEV \r
1703 QhPtr - A pointer to Qh\r
1704 \r
1705Returns:\r
1706\r
1707 VOID\r
1708 \r
1709--*/\r
1710;\r
1711\r
1712EFI_STATUS\r
1713CreateQtd (\r
1714 IN USB2_HC_DEV *HcDev,\r
1715 IN UINT8 *DataPtr,\r
1716 IN UINTN DataLen,\r
1717 IN UINT8 PktId,\r
1718 IN UINT8 Toggle,\r
1719 IN UINT8 QtdStatus,\r
1720 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1721 )\r
1722/*++\r
1723\r
1724Routine Description:\r
1725\r
1726 Create Qtd Structure and Pre-Initialize it\r
1727\r
1728Arguments:\r
1729\r
1730 HcDev - USB2_HC_DEV \r
1731 DataPtr - A pointer to user data buffer to transfer\r
1732 DataLen - Length of user data to transfer\r
1733 PktId - Packet Identification of this Qtd\r
1734 Toggle - Data Toggle of this Qtd\r
1735 QtdStatus - Default value of status of this Qtd\r
1736 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1737 \r
1738Returns:\r
1739\r
1740 EFI_SUCCESS Success\r
1741 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1742 \r
1743--*/\r
1744;\r
1745\r
1746EFI_STATUS\r
1747CreateSetupQtd (\r
1748 IN USB2_HC_DEV *HcDev,\r
1749 IN UINT8 *DevReqPtr,\r
1750 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1751 )\r
1752/*++\r
1753\r
1754Routine Description:\r
1755\r
1756 Create Qtd Structure for Setup \r
1757\r
1758Arguments:\r
1759\r
1760 HcDev - USB2_HC_DEV \r
1761 DevReqPtr - A pointer to Device Request Data\r
1762 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1763 \r
1764Returns:\r
1765\r
1766 EFI_SUCCESS Success\r
1767 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1768 \r
1769--*/\r
1770;\r
1771\r
1772EFI_STATUS\r
1773CreateDataQtd (\r
1774 IN USB2_HC_DEV *HcDev,\r
1775 IN UINT8 *DataPtr,\r
1776 IN UINTN DataLen,\r
1777 IN UINT8 PktId,\r
1778 IN UINT8 Toggle,\r
1779 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1780 )\r
1781/*++\r
1782\r
1783Routine Description:\r
1784\r
1785 Create Qtd Structure for data \r
1786\r
1787Arguments:\r
1788\r
1789 HcDev - USB2_HC_DEV \r
1790 DataPtr - A pointer to user data buffer to transfer\r
1791 DataLen - Length of user data to transfer\r
1792 PktId - Packet Identification of this Qtd\r
1793 Toggle - Data Toggle of this Qtd\r
1794 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1795 \r
1796Returns:\r
1797\r
1798 EFI_SUCCESS Success\r
1799 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1800 \r
1801--*/\r
1802;\r
1803\r
1804EFI_STATUS\r
1805CreateStatusQtd (\r
1806 IN USB2_HC_DEV *HcDev,\r
1807 IN UINT8 PktId,\r
1808 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1809 )\r
1810/*++\r
1811\r
1812Routine Description:\r
1813\r
1814 Create Qtd Structure for status \r
1815\r
1816Arguments:\r
1817\r
1818 HcDev - USB2_HC_DEV \r
1819 PktId - Packet Identification of this Qtd\r
1820 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1821 \r
1822Returns:\r
1823\r
1824 EFI_SUCCESS Success\r
1825 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1826 \r
1827--*/\r
1828;\r
1829\r
1830EFI_STATUS\r
1831CreateAltQtd (\r
1832 IN USB2_HC_DEV *HcDev,\r
1833 IN UINT8 PktId,\r
1834 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1835 )\r
1836/*++\r
1837\r
1838Routine Description:\r
1839\r
1840 Create Qtd Structure for Alternative \r
1841\r
1842Arguments:\r
1843\r
1844 HcDev - USB2_HC_DEV \r
1845 PktId - Packet Identification of this Qtd\r
1846 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1847 \r
1848Returns:\r
1849\r
1850 EFI_SUCCESS Success\r
1851 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1852 \r
1853--*/\r
1854;\r
1855\r
1856EFI_STATUS\r
1857CreateControlQtds (\r
1858 IN USB2_HC_DEV *HcDev,\r
1859 IN UINT8 DataPktId,\r
1860 IN UINT8 *RequestCursor,\r
1861 IN UINT8 *DataCursor,\r
1862 IN UINTN DataLen,\r
1863 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1864 OUT EHCI_QTD_ENTITY **ControlQtdsHead\r
1865 )\r
1866/*++\r
1867\r
1868Routine Description:\r
1869\r
1870 Create Qtds list for Control Transfer \r
1871\r
1872Arguments:\r
1873\r
1874 HcDev - USB2_HC_DEV \r
1875 DataPktId - Packet Identification of Data Qtds\r
1876 RequestCursor - A pointer to request structure buffer to transfer\r
1877 DataCursor - A pointer to user data buffer to transfer\r
1878 DataLen - Length of user data to transfer\r
1879 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1880 \r
1881Returns:\r
1882\r
1883 EFI_SUCCESS Success\r
1884 EFI_DEVICE_ERROR Fail\r
1885 \r
1886--*/\r
1887;\r
1888\r
1889EFI_STATUS\r
1890CreateBulkOrInterruptQtds (\r
1891 IN USB2_HC_DEV *HcDev,\r
1892 IN UINT8 PktId,\r
1893 IN UINT8 *DataCursor,\r
1894 IN UINTN DataLen,\r
1895 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1896 OUT EHCI_QTD_ENTITY **QtdsHead\r
1897 )\r
1898/*++\r
1899\r
1900Routine Description:\r
1901\r
1902 Create Qtds list for Bulk or Interrupt Transfer \r
1903\r
1904Arguments:\r
1905\r
1906 HcDev - USB2_HC_DEV \r
1907 PktId - Packet Identification of Qtds\r
1908 DataCursor - A pointer to user data buffer to transfer\r
1909 DataLen - Length of user data to transfer\r
1910 DataToggle - Data Toggle to start\r
1911 Translator - Translator Transaction for SplitX\r
1912 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1913 \r
1914Returns:\r
1915\r
1916 EFI_SUCCESS Success\r
1917 EFI_DEVICE_ERROR Fail\r
1918 \r
1919--*/\r
1920;\r
1921\r
1922VOID\r
1923DestoryQtds (\r
1924 IN USB2_HC_DEV *HcDev,\r
1925 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
1926 )\r
1927/*++\r
1928\r
1929Routine Description:\r
1930\r
1931 Destory all Qtds in the list\r
1932\r
1933Arguments:\r
1934\r
1935 HcDev - USB2_HC_DEV \r
1936 FirstQtdPtr - A pointer to first Qtd in the list \r
1937 \r
1938Returns:\r
1939\r
1940 VOID\r
1941\r
1942--*/\r
1943;\r
1944\r
1945VOID\r
1946LinkQtdToQtd (\r
1947 IN EHCI_QTD_ENTITY *PreQtdPtr,\r
1948 IN EHCI_QTD_ENTITY *QtdPtr\r
1949 )\r
1950/*++\r
1951\r
1952Routine Description:\r
1953\r
1954 Link Qtds together\r
1955 \r
1956Arguments:\r
1957\r
1958 PreQtdPtr - A pointer to pre Qtd\r
1959 QtdPtr - A pointer to next Qtd\r
1960 \r
1961Returns:\r
1962\r
1963 VOID\r
1964\r
1965--*/\r
1966;\r
1967\r
1968VOID\r
1969LinkQtdsToAltQtd (\r
1970 IN EHCI_QTD_ENTITY *FirstQtdPtr,\r
1971 IN EHCI_QTD_ENTITY *AltQtdPtr\r
1972 )\r
1973/*++\r
1974\r
1975Routine Description:\r
1976\r
1977 Link AlterQtds together\r
1978 \r
1979Arguments:\r
1980\r
1981 FirstQtdPtr - A pointer to first Qtd in the list\r
1982 AltQtdPtr - A pointer to alternative Qtd\r
1983 \r
1984Returns:\r
1985 VOID\r
1986\r
1987--*/\r
1988;\r
1989\r
1990VOID\r
1991LinkQtdToQh (\r
1992 IN EHCI_QH_ENTITY *QhPtr,\r
1993 IN EHCI_QTD_ENTITY *QtdEntryPtr\r
1994 )\r
1995/*++\r
1996\r
1997Routine Description:\r
1998\r
1999 Link Qtds list to Qh\r
2000 \r
2001Arguments:\r
2002\r
2003 QhPtr - A pointer to Qh\r
2004 QtdPtr - A pointer to first Qtd in the list\r
2005 \r
2006Returns:\r
2007\r
2008 VOID\r
2009\r
2010--*/\r
2011;\r
2012\r
2013EFI_STATUS\r
2014LinkQhToAsyncList (\r
2015 IN USB2_HC_DEV *HcDev,\r
2016 IN EHCI_QH_ENTITY *QhPtr\r
2017 )\r
2018/*++\r
2019\r
2020Routine Description:\r
2021\r
2022 Link Qh to Async Schedule List\r
2023 \r
2024Arguments:\r
2025\r
2026 HcDev - USB2_HC_DEV \r
2027 QhPtr - A pointer to Qh\r
2028 \r
2029Returns:\r
2030\r
2031 EFI_SUCCESS Success\r
2032 EFI_DEVICE_ERROR Fail\r
2033 \r
2034--*/\r
2035;\r
2036\r
2037EFI_STATUS\r
2038UnlinkQhFromAsyncList (\r
2039 IN USB2_HC_DEV *HcDev,\r
2040 IN EHCI_QH_ENTITY *QhPtr\r
2041 )\r
2042/*++\r
2043\r
2044Routine Description:\r
2045\r
2046 Unlink Qh from Async Schedule List\r
2047 \r
2048Arguments:\r
2049\r
2050 HcDev - USB2_HC_DEV \r
2051 QhPtr - A pointer to Qh\r
2052 \r
2053Returns:\r
2054\r
2055 EFI_SUCCESS Success\r
2056 EFI_DEVICE_ERROR Fail\r
2057 \r
2058--*/\r
2059;\r
2060\r
2061VOID\r
2062LinkQhToPeriodicList (\r
2063 IN USB2_HC_DEV *HcDev,\r
2064 IN EHCI_QH_ENTITY *QhPtr\r
2065 )\r
2066/*++\r
2067\r
2068Routine Description:\r
2069\r
2070 Link Qh to Periodic Schedule List\r
2071 \r
2072Arguments:\r
2073\r
2074 HcDev - USB2_HC_DEV \r
2075 QhPtr - A pointer to Qh\r
2076 \r
2077Returns:\r
2078\r
2079 VOID\r
2080\r
2081--*/\r
2082;\r
2083\r
2084VOID\r
2085UnlinkQhFromPeriodicList (\r
2086 IN USB2_HC_DEV *HcDev,\r
2087 IN EHCI_QH_ENTITY *QhPtr,\r
2088 IN UINTN Interval\r
2089 )\r
2090/*++\r
2091\r
2092Routine Description:\r
2093\r
2094 Unlink Qh from Periodic Schedule List\r
2095 \r
2096Arguments:\r
2097\r
2098 HcDev - USB2_HC_DEV \r
2099 QhPtr - A pointer to Qh\r
2100 Interval - Interval of this periodic transfer\r
2101 \r
2102Returns:\r
2103\r
2104 VOID\r
2105 \r
2106--*/\r
2107;\r
2108\r
2109VOID\r
2110LinkToAsyncReqeust (\r
2111 IN USB2_HC_DEV *HcDev,\r
2112 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2113 )\r
2114/*++\r
2115\r
2116Routine Description:\r
2117\r
2118 Llink AsyncRequest Entry to Async Request List\r
2119 \r
2120Arguments:\r
2121\r
2122 HcDev - USB2_HC_DEV \r
2123 AsyncRequestPtr - A pointer to Async Request Entry\r
2124 \r
2125Returns:\r
2126\r
2127 VOID\r
2128 \r
2129--*/\r
2130;\r
2131\r
2132VOID\r
2133UnlinkFromAsyncReqeust (\r
2134 IN USB2_HC_DEV *HcDev,\r
2135 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2136 )\r
2137/*++\r
2138\r
2139Routine Description:\r
2140\r
2141 Unlink AsyncRequest Entry from Async Request List\r
2142 \r
2143Arguments:\r
2144\r
2145 HcDev - USB2_HC_DEV \r
2146 AsyncRequestPtr - A pointer to Async Request Entry\r
2147 \r
2148Returns:\r
2149\r
2150 VOID\r
2151 \r
2152--*/\r
2153;\r
2154\r
2155UINTN\r
2156GetNumberOfQtd (\r
2157 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2158 )\r
2159/*++\r
2160\r
2161Routine Description:\r
2162\r
2163 Number of Qtds in the list\r
2164 \r
2165Arguments:\r
2166\r
2167 FirstQtdPtr - A pointer to first Qtd in the list\r
2168 \r
2169Returns:\r
2170\r
2171 Number of Qtds in the list\r
2172\r
2173--*/\r
2174;\r
2175\r
2176UINTN\r
2177GetNumberOfTransaction (\r
2178 IN UINTN SizeOfData,\r
2179 IN UINTN SizeOfTransaction\r
2180 )\r
2181/*++\r
2182\r
2183Routine Description:\r
2184\r
2185 Number of Transactions in one Qtd\r
2186 \r
2187Arguments:\r
2188\r
2189 SizeOfData - Size of one Qtd\r
2190 SizeOfTransaction - Size of one Transaction\r
2191 \r
2192Returns:\r
2193\r
2194 Number of Transactions in this Qtd\r
2195\r
2196--*/\r
2197;\r
2198\r
2199UINTN\r
2200GetCapacityOfQtd (\r
2201 IN UINT8 *BufferCursor\r
2202 )\r
2203/*++\r
2204\r
2205Routine Description:\r
2206\r
2207 Get Capacity of Qtd\r
2208 \r
2209Arguments:\r
2210\r
2211 BufferCursor - BufferCursor of the Qtd\r
2212 \r
2213Returns:\r
2214\r
2215 Capacity of Qtd\r
2216\r
2217--*/\r
2218;\r
2219\r
2220UINTN\r
2221GetApproxiOfInterval (\r
2222 IN UINTN Interval\r
2223 )\r
2224/*++\r
2225\r
2226Routine Description:\r
2227\r
2228 Get the approximate value in the 2 index sequence\r
2229 \r
2230Arguments:\r
2231\r
2232 Interval - the value of interval\r
2233 \r
2234Returns:\r
2235\r
2236 approximate value of interval in the 2 index sequence\r
2237 \r
2238--*/\r
2239;\r
2240\r
2241EHCI_QTD_HW *\r
2242GetQtdNextPointer (\r
2243 IN EHCI_QTD_HW *HwQtdPtr\r
2244 )\r
2245/*++\r
2246\r
2247Routine Description:\r
2248\r
2249 Get Qtd next pointer field\r
2250 \r
2251Arguments:\r
2252\r
2253 HwQtdPtr - A pointer to hardware Qtd structure\r
2254 \r
2255Returns:\r
2256\r
2257 A pointer to next hardware Qtd structure\r
2258 \r
2259--*/\r
2260;\r
2261\r
2262BOOLEAN\r
2263IsQtdStatusActive (\r
2264 IN EHCI_QTD_HW *HwQtdPtr\r
2265 )\r
2266/*++\r
2267\r
2268Routine Description:\r
2269\r
2270 Whether Qtd status is active or not\r
2271 \r
2272Arguments:\r
2273\r
2274 HwQtdPtr - A pointer to hardware Qtd structure\r
2275 \r
2276Returns:\r
2277\r
2278 TRUE Active\r
2279 FALSE Inactive\r
2280 \r
2281--*/\r
2282;\r
2283\r
2284BOOLEAN\r
2285IsQtdStatusHalted (\r
2286 IN EHCI_QTD_HW *HwQtdPtr\r
2287 )\r
2288/*++\r
2289\r
2290Routine Description:\r
2291\r
2292 Whether Qtd status is halted or not\r
2293 \r
2294Arguments:\r
2295\r
2296 HwQtdPtr - A pointer to hardware Qtd structure\r
2297 \r
2298Returns:\r\r
2299\r
2300 TRUE Halted\r
2301 FALSE Not halted\r
2302 \r
2303--*/\r
2304;\r
2305\r
2306BOOLEAN\r
2307IsQtdStatusBufferError (\r
2308 IN EHCI_QTD_HW *HwQtdPtr\r
2309 )\r
2310/*++\r
2311\r
2312Routine Description:\r
2313\r
2314 Whether Qtd status is buffer error or not\r
2315 \r
2316Arguments:\r
2317\r
2318 HwQtdPtr - A pointer to hardware Qtd structure\r
2319 \r
2320Returns:\r
2321\r
2322 TRUE Buffer error\r
2323 FALSE No buffer error\r
2324 \r
2325--*/\r
2326;\r
2327\r
2328BOOLEAN\r
2329IsQtdStatusBabbleError (\r
2330 IN EHCI_QTD_HW *HwQtdPtr\r
2331 )\r
2332/*++\r
2333\r
2334Routine Description:\r
2335\r
2336 Whether Qtd status is babble error or not\r
2337 \r
2338Arguments:\r
2339\r
2340 HwQtdPtr - A pointer to hardware Qtd structure\r
2341 \r
2342Returns:\r
2343\r
2344 TRUE Babble error\r
2345 FALSE No babble error\r
2346 \r
2347--*/\r
2348;\r
2349\r
2350BOOLEAN\r
2351IsQtdStatusTransactionError (\r
2352 IN EHCI_QTD_HW *HwQtdPtr\r
2353 )\r
2354/*++\r
2355\r
2356Routine Description:\r
2357\r
2358 Whether Qtd status is transaction error or not\r
2359 \r
2360Arguments:\r
2361\r
2362 HwQtdPtr - A pointer to hardware Qtd structure\r
2363 \r
2364Returns:\r
2365\r
2366 TRUE Transaction error\r
2367 FALSE No transaction error\r
2368 \r
2369--*/\r
2370;\r
2371\r
2372BOOLEAN\r
2373IsDataInTransfer (\r
2374 IN UINT8 EndPointAddress\r
2375 )\r
2376/*++\r
2377\r
2378Routine Description:\r
2379\r
2380 Whether is a DataIn direction transfer\r
2381 \r
2382Arguments:\r
2383\r
2384 EndPointAddress - address of the endpoint \r
2385 \r
2386Returns:\r
2387\r
2388 TRUE DataIn\r
2389 FALSE DataOut\r
2390 \r
2391--*/\r
2392;\r
2393\r
2394EFI_STATUS\r
2395MapDataBuffer (\r
2396 IN USB2_HC_DEV *HcDev,\r
2397 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
2398 IN OUT VOID *Data,\r
2399 IN OUT UINTN *DataLength,\r
2400 OUT UINT8 *PktId,\r
2401 OUT UINT8 **DataCursor,\r
2402 OUT VOID **DataMap\r
2403 )\r
2404/*++\r
2405\r
2406Routine Description:\r
2407\r
2408 Map address of user data buffer\r
2409 \r
2410Arguments:\r
2411\r
2412 HcDev - USB2_HC_DEV \r
2413 TransferDirection - direction of transfer\r
2414 Data - A pointer to user data buffer \r
2415 DataLength - length of user data\r
2416 PktId - Packte Identificaion\r
2417 DataCursor - mapped address to return\r
2418 DataMap - identificaion of this mapping to return\r
2419 \r
2420Returns:\r
2421\r
2422 EFI_SUCCESS Success\r
2423 EFI_DEVICE_ERROR Fail\r
2424 \r
2425--*/\r
2426;\r
2427\r
2428EFI_STATUS\r
2429MapRequestBuffer (\r
2430 IN USB2_HC_DEV *HcDev,\r
2431 IN OUT VOID *Request,\r
2432 OUT UINT8 **RequestCursor,\r
2433 OUT VOID **RequestMap\r
2434 )\r
2435/*++\r
2436\r
2437Routine Description:\r
2438\r
2439 Map address of request structure buffer\r
2440 \r
2441Arguments:\r
2442\r
2443 HcDev - USB2_HC_DEV \r
2444 Request - A pointer to request structure\r
2445 RequestCursor - Mapped address of request structure to return\r
2446 RequestMap - Identificaion of this mapping to return\r
2447 \r
2448Returns:\r
2449\r
2450 EFI_SUCCESS Success\r
2451 EFI_DEVICE_ERROR Fail\r
2452 \r
2453--*/\r
2454;\r
2455\r
2456VOID\r
2457SetQtdBufferPointer (\r
2458 IN EHCI_QTD_HW *QtdHwPtr,\r
2459 IN VOID *DataPtr,\r
2460 IN UINTN DataLen\r
2461 )\r
2462/*++\r
2463\r
2464Routine Description:\r
2465\r
2466 Set data buffer pointers in Qtd\r
2467\r
2468Arguments:\r
2469\r
2470 QtdHwPtr - A pointer to Qtd hardware structure \r
2471 DataPtr - A pointer to user data buffer\r
2472 DataLen - Length of the user data buffer\r
2473 \r
2474Returns:\r
2475\r
2476 VOID\r
2477\r
2478--*/\r
2479;\r
2480\r
2481EHCI_QTD_HW *\r
2482GetQtdAlternateNextPointer (\r
2483 IN EHCI_QTD_HW *HwQtdPtr\r
2484 )\r
2485/*++\r
2486\r
2487Routine Description:\r
2488\r
2489 Get Qtd alternate next pointer field\r
2490 \r
2491Arguments:\r
2492\r
2493 HwQtdPtr - A pointer to hardware Qtd structure\r
2494 \r
2495Returns:\r
2496\r
2497 A pointer to hardware alternate Qtd\r
2498 \r
2499--*/\r
2500;\r
2501\r
2502VOID\r
2503ZeroOutQhOverlay (\r
2504 IN EHCI_QH_ENTITY *QhPtr\r
2505 )\r
2506/*++\r
2507\r
2508Routine Description:\r
2509\r
2510 Zero out the fields in Qh structure\r
2511 \r
2512Arguments:\r
2513\r
2514 QhPtr - A pointer to Qh structure\r
2515 \r
2516Returns:\r
2517\r
2518 VOID\r
2519 \r
2520--*/\r
2521;\r
2522\r
2523VOID\r
2524UpdateAsyncRequestTransfer (\r
2525 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,\r
2526 IN UINT32 TransferResult,\r
2527 IN UINTN ErrTDPos\r
2528 )\r
2529/*++\r
2530\r
2531Routine Description:\r
2532\r
2533 Update asynchronous request transfer\r
2534 \r
2535Arguments:\r
2536\r
2537 AsyncRequestPtr - A pointer to async request \r
2538 TransferResult - transfer result \r
2539 ErrQtdPos - postion of error Qtd\r
2540 \r
2541Returns:\r
2542\r
2543 VOID\r
2544 \r
2545--*/\r
2546;\r
2547\r
2548\r
2549EFI_STATUS\r
2550DeleteAsyncRequestTransfer (\r
2551 IN USB2_HC_DEV *HcDev,\r
2552 IN UINT8 DeviceAddress,\r
2553 IN UINT8 EndPointAddress,\r
2554 OUT UINT8 *DataToggle\r
2555 )\r
2556/*++\r
2557\r
2558Routine Description:\r
2559\r
2560 Delete all asynchronous request transfer\r
2561 \r
2562Arguments:\r
2563\r
2564 HcDev - USB2_HC_DEV \r
2565 DeviceAddress - address of usb device\r
2566 EndPointAddress - address of endpoint\r
2567 DataToggle - stored data toggle\r
2568 \r
2569Returns:\r
2570\r
2571 EFI_SUCCESS Success\r
2572 EFI_DEVICE_ERROR Fail\r
2573\r
2574--*/\r
2575;\r
2576\r
2577VOID\r
2578CleanUpAllAsyncRequestTransfer (\r
2579 IN USB2_HC_DEV *HcDev\r
2580 )\r
2581/*++\r
2582\r
2583Routine Description:\r
2584\r
2585 Clean up all asynchronous request transfer\r
2586 \r
2587Arguments:\r
2588\r
2589 HcDev - USB2_HC_DEV \r
2590 \r
2591Returns:\r
2592 VOID\r
2593 \r
2594--*/\r
2595;\r
2596\r
2597EFI_STATUS\r
2598ExecuteTransfer (\r
2599 IN USB2_HC_DEV *HcDev,\r
2600 IN BOOLEAN IsControl,\r
2601 IN EHCI_QH_ENTITY *QhPtr,\r
2602 IN OUT UINTN *ActualLen,\r
2603 OUT UINT8 *DataToggle,\r
2604 IN UINTN TimeOut,\r
2605 OUT UINT32 *TransferResult\r
2606 )\r
2607/*++\r
2608\r
2609Routine Description:\r
2610\r
2611 Execute Bulk or SyncInterrupt Transfer\r
2612\r
2613Arguments:\r
2614\r
2615 HcDev - USB2_HC_DEV\r
2616 IsControl - Is control transfer or not\r
2617 QhPtr - A pointer to Qh\r
2618 ActualLen - Actual transfered Len \r
2619 DataToggle - Data Toggle\r
2620 TimeOut - TimeOut threshold\r
2621 TransferResult - Transfer result\r
2622 \r
2623Returns:\r
2624\r
2625 EFI_SUCCESS Sucess\r
2626 EFI_DEVICE_ERROR Error\r
2627 \r
2628--*/\r
2629;\r
2630\r
2631BOOLEAN\r
2632CheckQtdsTransferResult (\r
2633 IN BOOLEAN IsControl,\r
2634 IN EHCI_QH_ENTITY *QhPtr,\r
2635 OUT UINT32 *Result,\r
2636 OUT UINTN *ErrQtdPos,\r
2637 OUT UINTN *ActualLen\r
2638 )\r
2639/*++\r
2640\r
2641Routine Description:\r
2642\r
2643 Check transfer result of Qtds\r
2644\r
2645Arguments:\r
2646\r
2647 IsControl - Is control transfer or not\r
2648 QhPtr - A pointer to Qh\r
2649 Result - Transfer result\r
2650 ErrQtdPos - Error TD Position\r
2651 ActualLen - Actual Transfer Size\r
2652\r
2653Returns:\r
2654\r
2655 TRUE Qtds finished\r
2656 FALSE Not finish\r
2657 \r
2658--*/\r
2659;\r
2660\r
2661EFI_STATUS\r
2662AsyncRequestMoniter (\r
2663 IN EFI_EVENT Event,\r
2664 IN VOID *Context\r
2665 )\r
2666/*++\r
2667\r
2668Routine Description:\r
2669 \r
2670 Interrupt transfer periodic check handler\r
2671 \r
2672Arguments:\r
2673\r
2674 Event - Interrupt event\r
2675 Context - Pointer to USB2_HC_DEV\r
2676 \r
2677Returns:\r
2678 \r
2679 EFI_SUCCESS Success\r
2680 EFI_DEVICE_ERROR Fail\r
2681 \r
2682--*/\r
2683;\r
2684\r
74c56167 2685VOID\r
2686ClearLegacySupport (\r
2687 IN USB2_HC_DEV *HcDev\r
2688 );\r
2689\r
2690VOID\r
2691HostReset (\r
2692 IN USB2_HC_DEV *HcDev\r
2693 );\r
2694\r
2695VOID \r
2696DumpEHCIPortsStatus (\r
2697 IN USB2_HC_DEV *HcDev\r
2698 );\r
562d2849 2699#endif\r
EFI Development Kit II mirror for PVE