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1. Add NULL QH to set as QH header;
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
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562d2849 1/*++\r
2\r
4d1fe68e 3Copyright (c) 2006, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
562d2849 11\r
12Module Name:\r
13\r
14 Ehci.h\r
4d1fe68e 15\r
16Abstract:\r
17\r
562d2849 18\r
19Revision History\r
20--*/\r
21\r
22#ifndef _EHCI_H\r
23#define _EHCI_H\r
24\r
25//\r
26// Universal Host Controller Interface data structures and defines\r
27//\r
28#include <IndustryStandard/pci22.h>\r
29\r
71a62114 30\r
713ace4c 31extern UINTN gEHCDebugLevel;\r
32extern UINTN gEHCErrorLevel;\r
71a62114 33\r
562d2849 34\r
35#define STALL_1_MACRO_SECOND 1\r
36#define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND\r
37#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r
38\r
4d1fe68e 39#define MEM_UNIT_SIZE 128\r
40\r
41\r
562d2849 42#define SETUP_PACKET_PID_CODE 0x02\r
43#define INPUT_PACKET_PID_CODE 0x01\r
44#define OUTPUT_PACKET_PID_CODE 0x0\r
45\r
46#define ITD_SELECT_TYPE 0x0\r
47#define QH_SELECT_TYPE 0x01\r
48#define SITD_SELECT_TYPE 0x02\r
49#define FSTN_SELECT_TYPE 0x03\r
50\r
51#define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND\r
52#define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND\r
53#define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND\r
54#define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND\r
55#define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND\r
56#define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND\r
57\r
58#define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */\r
59\r
4d1fe68e 60#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16\r
562d2849 61\r
62#define EHCI_MIN_PACKET_SIZE 8\r
63#define EHCI_MAX_PACKET_SIZE 1024\r
64#define EHCI_MAX_FRAME_LIST_LENGTH 1024\r
65#define EHCI_BLOCK_SIZE_WITH_TT 64\r
66#define EHCI_BLOCK_SIZE 512\r
67#define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)\r
68\r
69#define NAK_COUNT_RELOAD 3\r
4d1fe68e 70#define QTD_ERROR_COUNTER 3\r
562d2849 71#define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1\r
72\r
73#define QTD_STATUS_ACTIVE 0x80\r
74#define QTD_STATUS_HALTED 0x40\r
75#define QTD_STATUS_BUFFER_ERR 0x20\r
76#define QTD_STATUS_BABBLE_ERR 0x10\r
77#define QTD_STATUS_TRANSACTION_ERR 0x08\r
78#define QTD_STATUS_DO_STOP_SPLIT 0x02\r
79#define QTD_STATUS_DO_START_SPLIT 0\r
80#define QTD_STATUS_DO_PING 0x01\r
81#define QTD_STATUS_DO_OUT 0\r
82\r
83#define DATA0 0\r
84#define DATA1 1\r
85\r
86#define MICRO_FRAME_0_CHANNEL 0x01\r
87#define MICRO_FRAME_1_CHANNEL 0x02\r
88#define MICRO_FRAME_2_CHANNEL 0x04\r
89#define MICRO_FRAME_3_CHANNEL 0x08\r
90#define MICRO_FRAME_4_CHANNEL 0x10\r
91#define MICRO_FRAME_5_CHANNEL 0x20\r
92#define MICRO_FRAME_6_CHANNEL 0x40\r
93#define MICRO_FRAME_7_CHANNEL 0x80\r
94\r
95#define CONTROL_TRANSFER 0x01\r
96#define BULK_TRANSFER 0x02\r
97#define SYNC_INTERRUPT_TRANSFER 0x04\r
98#define ASYNC_INTERRUPT_TRANSFER 0x08\r
99#define SYNC_ISOCHRONOUS_TRANSFER 0x10\r
100#define ASYNC_ISOCHRONOUS_TRANSFER 0x20\r
101\r
102\r
103//\r
104// Enhanced Host Controller Registers definitions\r
105//\r
562d2849 106extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
107extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
108\r
109#define USBCMD 0x0 /* Command Register Offset 00-03h */\r
110#define USBCMD_RS 0x01 /* Run / Stop */\r
111#define USBCMD_HCRESET 0x02 /* Host controller reset */\r
112#define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */\r
113#define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */\r
114#define USBCMD_PSE 0x10 /* Periodic schedule enable */\r
115#define USBCMD_ASE 0x20 /* Asynchronous schedule enable */\r
116#define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */\r
117\r
118#define USBSTS 0x04 /* Statue Register Offset 04-07h */\r
119#define USBSTS_HSE 0x10 /* Host system error */\r
120#define USBSTS_IAA 0x20 /* Interrupt on async advance */\r
121#define USBSTS_HCH 0x1000 /* Host controller halted */\r
122#define USBSTS_PSS 0x4000 /* Periodic schedule status */\r
123#define USBSTS_ASS 0x8000 /* Asynchronous schedule status */\r
124\r
125#define USBINTR 0x08 /* Command Register Offset 08-0bh */\r
126\r
127#define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */\r
128\r
129#define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */\r
130\r
131#define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */\r
132\r
133#define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */\r
134\r
135#define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */\r
136#define CONFIGFLAG_CF 0x01 /* Configure Flag */\r
137\r
138#define PORTSC 0x44 /* Port Status/Control Offset 44-47h */\r
139#define PORTSC_CCS 0x01 /* Current Connect Status*/\r
140#define PORTSC_CSC 0x02 /* Connect Status Change */\r
141#define PORTSC_PED 0x04 /* Port Enable / Disable */\r
142#define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */\r
143#define PORTSC_OCA 0x10 /* Over current Active */\r
144#define PORTSC_OCC 0x20 /* Over current Change */\r
145#define PORTSC_FPR 0x40 /* Force Port Resume */\r
146#define PORTSC_SUSP 0x80 /* Port Suspend State */\r
147#define PORTSC_PR 0x100 /* Port Reset */\r
148#define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */\r
149#define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */\r
150#define PORTSC_PP 0x1000 /* Port Power */\r
151#define PORTSC_PO 0x2000 /* Port Owner */\r
152\r
153#define CAPLENGTH 0 /* Capability Register Length 00h */\r
154\r
155#define HCIVERSION 0x02 /* Interface Version Number 02-03h */\r
156\r
157#define HCSPARAMS 0x04 /* Structural Parameters 04-07h */\r
158#define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */\r
159\r
160#define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */\r
161#define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */\r
162#define HCCP_PFLF 0x02 /* Programmable Frame List Flag */\r
163#define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */\r
164\r
165#define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */\r
166\r
167#define CLASSC 0x09 /* Class Code 09-0bh */\r
168\r
169#define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */\r
170\r
171#define SBRN 0x60 /* Serial Bus Release Number 60h */\r
172\r
173#define FLADJ 0x61 /* Frame Length Adjustment Register 61h */\r
174\r
175#define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */\r
176\r
177//\r
178// PCI Configuration Registers\r
179//\r
180#define EHCI_PCI_CLASSC 0x09\r
181#define EHCI_PCI_MEMORY_BASE 0x10\r
182\r
183//\r
184// Memory Offset Registers\r
185//\r
186#define EHCI_MEMORY_CAPLENGTH 0x0\r
187#define EHCI_MEMORY_CONFIGFLAG 0x40\r
188\r
189//\r
190// USB Base Class Code,Sub-Class Code and Programming Interface\r
191//\r
192#define PCI_CLASSC_PI_EHCI 0x20\r
193\r
194#define SETUP_PACKET_ID 0x2D\r
195#define INPUT_PACKET_ID 0x69\r
196#define OUTPUT_PACKET_ID 0xE1\r
197#define ERROR_PACKET_ID 0x55\r
198\r
71a62114 199#define bit(a) (1 << (a))\r
200\r
201#define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))\r
202#define GET_32B_TO_63B(Addr) ((UINTN)RShiftU64((UINTN) Addr, 32) & (0xffffffff))\r
562d2849 203\r
204\r
205//\r
206// Ehci Data and Ctrl Structures\r
207//\r
208#pragma pack(1)\r
209\r
210typedef struct {\r
211 UINT8 PI;\r
212 UINT8 SubClassCode;\r
213 UINT8 BaseCode;\r
214} USB_CLASSC;\r
215\r
4d1fe68e 216//\r
217//32 Bytes Aligned\r
218//\r
562d2849 219typedef struct {\r
220 UINT32 NextQtdTerminate : 1;\r
221 UINT32 Rsvd1 : 4;\r
222 UINT32 NextQtdPointer : 27;\r
223\r
224 UINT32 AltNextQtdTerminate : 1;\r
225 UINT32 Rsvd2 : 4;\r
226 UINT32 AltNextQtdPointer : 27;\r
227\r
228 UINT32 Status : 8;\r
229 UINT32 PidCode : 2;\r
230 UINT32 ErrorCount : 2;\r
231 UINT32 CurrentPage : 3;\r
232 UINT32 InterruptOnComplete : 1;\r
233 UINT32 TotalBytes : 15;\r
234 UINT32 DataToggle : 1;\r
235\r
236 UINT32 CurrentOffset : 12;\r
237 UINT32 BufferPointer0 : 20;\r
238\r
239 UINT32 Rsvd3 : 12;\r
240 UINT32 BufferPointer1 : 20;\r
241\r
242 UINT32 Rsvd4 : 12;\r
243 UINT32 BufferPointer2 : 20;\r
244\r
245 UINT32 Rsvd5 : 12;\r
246 UINT32 BufferPointer3 : 20;\r
247\r
248 UINT32 Rsvd6 : 12;\r
249 UINT32 BufferPointer4 : 20;\r
250\r
4d1fe68e 251 UINT32 PAD[5];\r
562d2849 252} EHCI_QTD_HW;\r
253\r
4d1fe68e 254//\r
255//32 Bytes Aligned\r
256//\r
562d2849 257typedef struct {\r
258 UINT32 QhTerminate : 1;\r
259 UINT32 SelectType : 2;\r
260 UINT32 Rsvd1 : 2;\r
261 UINT32 QhHorizontalPointer : 27;\r
262\r
263 UINT32 DeviceAddr : 7;\r
264 UINT32 Inactive : 1;\r
265 UINT32 EndpointNum : 4;\r
266 UINT32 EndpointSpeed : 2;\r
267 UINT32 DataToggleControl : 1;\r
268 UINT32 HeadReclamationFlag : 1;\r
269 UINT32 MaxPacketLen : 11;\r
270 UINT32 ControlEndpointFlag : 1;\r
271 UINT32 NakCountReload : 4;\r
272\r
273 UINT32 InerruptScheduleMask : 8;\r
274 UINT32 SplitComletionMask : 8;\r
275 UINT32 HubAddr : 7;\r
276 UINT32 PortNum : 7;\r
277 UINT32 Multiplier : 2;\r
278\r
279 UINT32 Rsvd2 : 5;\r
280 UINT32 CurrentQtdPointer : 27;\r
281\r
282 UINT32 NextQtdTerminate : 1;\r
283 UINT32 Rsvd3 : 4;\r
284 UINT32 NextQtdPointer : 27;\r
285\r
286 UINT32 AltNextQtdTerminate : 1;\r
287 UINT32 NakCount : 4;\r
288 UINT32 AltNextQtdPointer : 27;\r
289\r
290 UINT32 Status : 8;\r
291 UINT32 PidCode : 2;\r
292 UINT32 ErrorCount : 2;\r
293 UINT32 CurrentPage : 3;\r
294 UINT32 InterruptOnComplete : 1;\r
295 UINT32 TotalBytes : 15;\r
296 UINT32 DataToggle : 1;\r
297\r
298 UINT32 CurrentOffset : 12;\r
299 UINT32 BufferPointer0 : 20;\r
300\r
301 UINT32 CompleteSplitMask : 8;\r
302 UINT32 Rsvd4 : 4;\r
303 UINT32 BufferPointer1 : 20;\r
304\r
305 UINT32 FrameTag : 5;\r
306 UINT32 SplitBytes : 7;\r
307 UINT32 BufferPointer2 : 20;\r
308\r
309 UINT32 Rsvd5 : 12;\r
310 UINT32 BufferPointer3 : 20;\r
311\r
312 UINT32 Rsvd6 : 12;\r
313 UINT32 BufferPointer4 : 20;\r
314\r
4d1fe68e 315 UINT32 Pad[5];\r
562d2849 316} EHCI_QH_HW;\r
317\r
318typedef struct {\r
319 UINT32 LinkTerminate : 1;\r
320 UINT32 SelectType : 2;\r
321 UINT32 Rsvd : 2;\r
322 UINT32 LinkPointer : 27;\r
323} FRAME_LIST_ENTRY;\r
324\r
325#pragma pack()\r
326\r
327typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;\r
328typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;\r
329typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;\r
4d1fe68e 330//\r
331//Aligan On 32 Bytes\r
332//\r
ffac4bcb 333struct _EHCI_QTD_ENTITY {\r
562d2849 334 EHCI_QTD_HW Qtd;\r
335 UINT32 TotalBytes;\r
336 UINT32 StaticTotalBytes;\r
337 UINT32 StaticCurrentOffset;\r
338 EHCI_QTD_ENTITY *Prev;\r
339 EHCI_QTD_ENTITY *Next;\r
340 EHCI_QTD_ENTITY *AltNext;\r
341 EHCI_QH_ENTITY *SelfQh;\r
ffac4bcb 342};\r
4d1fe68e 343//\r
344//Aligan On 32 Bytes\r
345//\r
ffac4bcb 346struct _EHCI_QH_ENTITY {\r
562d2849 347 EHCI_QH_HW Qh;\r
348 EHCI_QH_ENTITY *Next;\r
349 EHCI_QH_ENTITY *Prev;\r
350 EHCI_QTD_ENTITY *FirstQtdPtr;\r
351 EHCI_QTD_ENTITY *LastQtdPtr;\r
352 EHCI_QTD_ENTITY *AltQtdPtr;\r
353 UINTN Interval;\r
354 UINT8 TransferType;\r
ffac4bcb 355};\r
562d2849 356\r
357#define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)\r
358#define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)\r
359\r
360\r
361//\r
362// Ehci Managment Structures\r
363//\r
364#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
365\r
366#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
367\r
ffac4bcb 368struct _EHCI_ASYNC_REQUEST {\r
562d2849 369 UINT8 TransferType;\r
370 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;\r
371 VOID *Context;\r
372 EHCI_ASYNC_REQUEST *Prev;\r
373 EHCI_ASYNC_REQUEST *Next;\r
374 EHCI_QH_ENTITY *QhPtr;\r
ffac4bcb 375};\r
562d2849 376\r
377typedef struct _MEMORY_MANAGE_HEADER {\r
378 UINT8 *BitArrayPtr;\r
379 UINTN BitArraySizeInBytes;\r
380 UINT8 *MemoryBlockPtr;\r
381 UINTN MemoryBlockSizeInBytes;\r
382 VOID *Mapping;\r
383 struct _MEMORY_MANAGE_HEADER *Next;\r
384} MEMORY_MANAGE_HEADER;\r
385\r
386typedef struct _USB2_HC_DEV {\r
387 UINTN Signature;\r
388 EFI_PCI_IO_PROTOCOL *PciIo;\r
389 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
390 UINTN PeriodicFrameListLength;\r
391 VOID *PeriodicFrameListBuffer;\r
392 VOID *PeriodicFrameListMap;\r
393 VOID *AsyncList;\r
394 EHCI_ASYNC_REQUEST *AsyncRequestList;\r
395 EFI_EVENT AsyncRequestEvent;\r
396 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
397 MEMORY_MANAGE_HEADER *MemoryHeader;\r
4d1fe68e 398 UINT8 Is64BitCapable;\r
562d2849 399 UINT32 High32BitAddr;\r
4d1fe68e 400 EHCI_QH_ENTITY *NULLQH;\r
37279806 401 UINT32 UsbCapabilityLen;\r
402 UINT16 DeviceSpeed[16];\r
562d2849 403} USB2_HC_DEV;\r
404\r
405\r
406//\r
407// Internal Functions Declaration\r
408//\r
409\r
410//\r
411// EhciMem Functions\r
412//\r
413EFI_STATUS\r
414CreateMemoryBlock (\r
415 IN USB2_HC_DEV *HcDev,\r
416 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
417 IN UINTN MemoryBlockSizeInPages\r
418 )\r
419/*++\r
420\r
421Routine Description:\r
422\r
423 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,\r
424 and use PciIo->Map to map the common buffer for Bus Master Read/Write.\r
425\r
426Arguments:\r
427\r
428 HcDev - USB2_HC_DEV\r
429 MemoryHeader - MEMORY_MANAGE_HEADER to output\r
430 MemoryBlockSizeInPages - MemoryBlockSizeInPages\r
4d1fe68e 431\r
562d2849 432Returns:\r
433\r
434 EFI_SUCCESS Success\r
435 EFI_OUT_OF_RESOURCES Fail for no resources\r
436 EFI_UNSUPPORTED Unsupported currently\r
4d1fe68e 437\r
562d2849 438--*/\r
439;\r
440\r
441EFI_STATUS\r
442FreeMemoryHeader (\r
443 IN USB2_HC_DEV *HcDev,\r
444 IN MEMORY_MANAGE_HEADER *MemoryHeader\r
445 )\r
446/*++\r
447\r
448Routine Description:\r
449\r
450 Free Memory Header\r
451\r
452Arguments:\r
453\r
454 HcDev - USB2_HC_DEV\r
455 MemoryHeader - MemoryHeader to be freed\r
456\r
457Returns:\r
458\r
459 EFI_SUCCESS Success\r
460 EFI_INVALID_PARAMETER Parameter is error\r
461\r
462--*/\r
463;\r
464\r
465VOID\r
466InsertMemoryHeaderToList (\r
467 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
468 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
469 )\r
470/*++\r
471\r
472Routine Description:\r
473\r
474 Insert Memory Header To List\r
475\r
476Arguments:\r
477\r
478 MemoryHeader - MEMORY_MANAGE_HEADER\r
479 NewMemoryHeader - MEMORY_MANAGE_HEADER\r
480\r
481Returns:\r
482\r
483 VOID\r
484\r
485--*/\r
486;\r
487\r
488EFI_STATUS\r
489AllocMemInMemoryBlock (\r
490 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
491 OUT VOID **Pool,\r
492 IN UINTN NumberOfMemoryUnit\r
493 )\r
494/*++\r
495\r
496Routine Description:\r
497\r
498 Alloc Memory In MemoryBlock\r
499\r
500Arguments:\r
501\r
502 MemoryHeader - MEMORY_MANAGE_HEADER\r
503 Pool - Place to store pointer to memory\r
504 NumberOfMemoryUnit - Number Of Memory Unit\r
505\r
506Returns:\r
507\r
508 EFI_SUCCESS Success\r
4d1fe68e 509 EFI_NOT_FOUND Can't find the free memory\r
562d2849 510\r
511--*/\r
512;\r
513\r
514BOOLEAN\r
515IsMemoryBlockEmptied (\r
516 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
517 )\r
518/*++\r
519\r
520Routine Description:\r
521\r
522 Is Memory Block Emptied\r
523\r
524Arguments:\r
525\r
526 MemoryHeaderPtr - MEMORY_MANAGE_HEADER\r
527\r
528Returns:\r
529\r
530 TRUE Empty\r
4d1fe68e 531 FALSE Not Empty\r
562d2849 532\r
533--*/\r
534;\r
535\r
536VOID\r
537DelinkMemoryBlock (\r
538 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
539 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader\r
540 )\r
541/*++\r
542\r
543Routine Description:\r
544\r
545 Delink Memory Block\r
546\r
547Arguments:\r
548\r
549 FirstMemoryHeader - MEMORY_MANAGE_HEADER\r
550 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER\r
551\r
552Returns:\r
553\r
554 VOID\r
555\r
556--*/\r
557;\r
558\r
559EFI_STATUS\r
560InitialMemoryManagement (\r
561 IN USB2_HC_DEV *HcDev\r
562 )\r
563/*++\r
564\r
565Routine Description:\r
566\r
567 Initialize Memory Management\r
568\r
569Arguments:\r
570\r
571 HcDev - USB2_HC_DEV\r
572\r
573Returns:\r
574\r
575 EFI_SUCCESS Success\r
576 EFI_DEVICE_ERROR Fail\r
577\r
578--*/\r
579;\r
580\r
581EFI_STATUS\r
582DeinitialMemoryManagement (\r
583 IN USB2_HC_DEV *HcDev\r
584 )\r
585/*++\r
586\r
587Routine Description:\r
588\r
589 Deinitialize Memory Management\r
590\r
591Arguments:\r
592\r
593 HcDev - USB2_HC_DEV\r
594\r
595Returns:\r
596\r
597 EFI_SUCCESS Success\r
598 EFI_DEVICE_ERROR Fail\r
4d1fe68e 599\r
562d2849 600--*/\r
601;\r
602\r
603EFI_STATUS\r
604EhciAllocatePool (\r
605 IN USB2_HC_DEV *HcDev,\r
606 OUT UINT8 **Pool,\r
607 IN UINTN AllocSize\r
608 )\r
609/*++\r
610\r
611Routine Description:\r
612\r
613 Ehci Allocate Pool\r
614\r
615Arguments:\r
616\r
617 HcDev - USB2_HC_DEV\r
618 Pool - Place to store pointer to the memory buffer\r
619 AllocSize - Alloc Size\r
620\r
621Returns:\r
622\r
623 EFI_SUCCESS Success\r
624 EFI_DEVICE_ERROR Fail\r
4d1fe68e 625\r
562d2849 626--*/\r
627;\r
628\r
629VOID\r
630EhciFreePool (\r
631 IN USB2_HC_DEV *HcDev,\r
632 IN UINT8 *Pool,\r
633 IN UINTN AllocSize\r
634 )\r
635/*++\r
636\r
637Routine Description:\r
638\r
639 Uhci Free Pool\r
640\r
641Arguments:\r
642\r
643 HcDev - USB_HC_DEV\r
644 Pool - Pool to free\r
645 AllocSize - Pool size\r
646\r
647Returns:\r
648\r
649 VOID\r
650\r
651--*/\r
652;\r
653\r
654//\r
655// EhciReg Functions\r
656//\r
657EFI_STATUS\r
658ReadEhcCapabiltiyReg (\r
659 IN USB2_HC_DEV *HcDev,\r
660 IN UINT32 CapabiltiyRegAddr,\r
661 IN OUT UINT32 *Data\r
662 )\r
663/*++\r
664\r
665Routine Description:\r
666\r
667 Read Ehc Capabitlity register\r
4d1fe68e 668\r
562d2849 669Arguments:\r
670\r
4d1fe68e 671 HcDev - USB2_HC_DEV\r
562d2849 672 CapabiltiyRegAddr - Ehc Capability register address\r
673 Data - A pointer to data read from register\r
4d1fe68e 674\r
562d2849 675Returns:\r
676\r
677 EFI_SUCCESS Success\r
678 EFI_DEVICE_ERROR Fail\r
4d1fe68e 679\r
562d2849 680--*/\r
681;\r
682\r
683EFI_STATUS\r
684ReadEhcOperationalReg (\r
685 IN USB2_HC_DEV *HcDev,\r
686 IN UINT32 OperationalRegAddr,\r
687 IN OUT UINT32 *Data\r
688 )\r
689/*++\r
690\r
691Routine Description:\r
692\r
693 Read Ehc Operation register\r
4d1fe68e 694\r
562d2849 695Arguments:\r
696\r
4d1fe68e 697 HcDev - USB2_HC_DEV\r
562d2849 698 OperationalRegAddr - Ehc Operation register address\r
699 Data - A pointer to data read from register\r
4d1fe68e 700\r
562d2849 701Returns:\r
702\r
703 EFI_SUCCESS Success\r
704 EFI_DEVICE_ERROR Fail\r
4d1fe68e 705\r
562d2849 706--*/\r
707;\r
708\r
709EFI_STATUS\r
710WriteEhcOperationalReg (\r
711 IN USB2_HC_DEV *HcDev,\r
712 IN UINT32 OperationalRegAddr,\r
713 IN UINT32 Data\r
714 )\r
715/*++\r
716\r
717Routine Description:\r
718\r
719 Write Ehc Operation register\r
4d1fe68e 720\r
562d2849 721Arguments:\r
722\r
4d1fe68e 723 HcDev - USB2_HC_DEV\r
562d2849 724 OperationalRegAddr - Ehc Operation register address\r
725 Data - 32bit write to register\r
4d1fe68e 726\r
562d2849 727Returns:\r
728\r
729 EFI_SUCCESS Success\r
730 EFI_DEVICE_ERROR Fail\r
4d1fe68e 731\r
562d2849 732--*/\r
733;\r
734\r
735EFI_STATUS\r
736SetEhcDoorbell (\r
737 IN USB2_HC_DEV *HcDev\r
738 )\r
739/*++\r
740\r
741Routine Description:\r
742\r
743 Set Ehc door bell bit\r
4d1fe68e 744\r
562d2849 745Arguments:\r
746\r
4d1fe68e 747 HcDev - USB2_HC_DEV\r
748\r
562d2849 749Returns:\r
750\r
751 EFI_SUCCESS Success\r
752 EFI_DEVICE_ERROR Fail\r
4d1fe68e 753\r
562d2849 754--*/\r
755;\r
756\r
757EFI_STATUS\r
758SetFrameListLen (\r
759 IN USB2_HC_DEV *HcDev,\r
760 IN UINTN Length\r
761 )\r
762/*++\r
763\r
764Routine Description:\r
765\r
766 Set the length of Frame List\r
4d1fe68e 767\r
562d2849 768Arguments:\r
769\r
4d1fe68e 770 HcDev - USB2_HC_DEV\r
562d2849 771 Length - the required length of frame list\r
4d1fe68e 772\r
562d2849 773Returns:\r
774\r
775 EFI_SUCCESS Success\r
776 EFI_INVALID_PARAMETER Invalid parameter\r
777 EFI_DEVICE_ERROR Fail\r
4d1fe68e 778\r
562d2849 779--*/\r
780;\r
781\r
782BOOLEAN\r
783IsFrameListProgrammable (\r
784 IN USB2_HC_DEV *HcDev\r
785 )\r
786/*++\r
787\r
788Routine Description:\r
789\r
790 Whether frame list is programmable\r
4d1fe68e 791\r
562d2849 792Arguments:\r
793\r
4d1fe68e 794 HcDev - USB2_HC_DEV\r
795\r
562d2849 796Returns:\r
797\r
798 TRUE Programmable\r
799 FALSE Unprogrammable\r
4d1fe68e 800\r
562d2849 801--*/\r
802;\r
803\r
804BOOLEAN\r
805IsPeriodicScheduleEnabled (\r
806 IN USB2_HC_DEV *HcDev\r
807 )\r
808/*++\r
809\r
810Routine Description:\r
811\r
812 Whether periodic schedule is enabled\r
4d1fe68e 813\r
562d2849 814Arguments:\r
815\r
4d1fe68e 816 HcDev - USB2_HC_DEV\r
817\r
562d2849 818Returns:\r
819\r
820 TRUE Enabled\r
821 FALSE Disabled\r
4d1fe68e 822\r
562d2849 823--*/\r
824;\r
825\r
826BOOLEAN\r
827IsAsyncScheduleEnabled (\r
828 IN USB2_HC_DEV *HcDev\r
829 )\r
830/*++\r
831\r
832Routine Description:\r
833\r
834 Whether asynchronous schedule is enabled\r
4d1fe68e 835\r
562d2849 836Arguments:\r
837\r
4d1fe68e 838 HcDev - USB2_HC_DEV\r
839\r
562d2849 840Returns:\r
841\r
842 TRUE Enabled\r
843 FALSE Disabled\r
4d1fe68e 844\r
562d2849 845--*/\r
846;\r
847\r
848BOOLEAN\r
849IsEhcPortEnabled (\r
850 IN USB2_HC_DEV *HcDev,\r
851 IN UINT8 PortNum\r
852 )\r
853/*++\r
854\r
855Routine Description:\r
856\r
857 Whether port is enabled\r
4d1fe68e 858\r
562d2849 859Arguments:\r
860\r
4d1fe68e 861 HcDev - USB2_HC_DEV\r
862\r
562d2849 863Returns:\r
864\r
865 TRUE Enabled\r
866 FALSE Disabled\r
4d1fe68e 867\r
562d2849 868--*/\r
869;\r
870\r
871BOOLEAN\r
872IsEhcReseted (\r
873 IN USB2_HC_DEV *HcDev\r
874 )\r
875/*++\r
876\r
877Routine Description:\r
878\r
879 Whether Ehc is halted\r
4d1fe68e 880\r
562d2849 881Arguments:\r
882\r
4d1fe68e 883 HcDev - USB2_HC_DEV\r
884\r
562d2849 885Returns:\r
886\r
887 TRUE Reseted\r
888 FALSE Unreseted\r
4d1fe68e 889\r
562d2849 890--*/\r
891;\r
892\r
893BOOLEAN\r
894IsEhcHalted (\r
895 IN USB2_HC_DEV *HcDev\r
896 )\r
897/*++\r
898\r
899Routine Description:\r
900\r
901 Whether Ehc is halted\r
4d1fe68e 902\r
562d2849 903Arguments:\r
904\r
4d1fe68e 905 HcDev - USB2_HC_DEV\r
906\r
562d2849 907Returns:\r
908\r
909 TRUE Halted\r
910 FALSE Not halted\r
4d1fe68e 911\r
562d2849 912--*/\r
913;\r
914\r
915BOOLEAN\r
916IsEhcSysError (\r
917 IN USB2_HC_DEV *HcDev\r
918 )\r
919/*++\r
920\r
921Routine Description:\r
922\r
923 Whether Ehc is system error\r
4d1fe68e 924\r
562d2849 925Arguments:\r
926\r
4d1fe68e 927 HcDev - USB2_HC_DEV\r
928\r
562d2849 929Returns:\r
930\r
931 TRUE System error\r
932 FALSE No system error\r
4d1fe68e 933\r
562d2849 934--*/\r
935;\r
936\r
937BOOLEAN\r
938IsHighSpeedDevice (\r
939 IN EFI_USB2_HC_PROTOCOL *This,\r
4d1fe68e 940 IN UINT8 PortNum\r
562d2849 941 )\r
942/*++\r
943\r
944Routine Description:\r
945\r
946 Whether high speed device attached\r
4d1fe68e 947\r
562d2849 948Arguments:\r
949\r
4d1fe68e 950 HcDev - USB2_HC_DEV\r
951\r
562d2849 952Returns:\r
953\r
954 TRUE High speed\r
955 FALSE Full speed\r
4d1fe68e 956\r
562d2849 957--*/\r
958;\r
959\r
960EFI_STATUS\r
961WaitForEhcReset (\r
962 IN USB2_HC_DEV *HcDev,\r
963 IN UINTN Timeout\r
964 )\r
965/*++\r
966\r
967Routine Description:\r
968\r
969 wait for Ehc reset or timeout\r
4d1fe68e 970\r
562d2849 971Arguments:\r
972\r
4d1fe68e 973 HcDev - USB2_HC_DEV\r
562d2849 974 Timeout - timeout threshold\r
4d1fe68e 975\r
562d2849 976Returns:\r
977\r
978 EFI_SUCCESS Success\r
979 EFI_TIMEOUT Timeout\r
4d1fe68e 980\r
562d2849 981--*/\r
982;\r
983\r
984EFI_STATUS\r
985WaitForEhcHalt (\r
986 IN USB2_HC_DEV *HcDev,\r
987 IN UINTN Timeout\r
988 )\r
989/*++\r
990\r
991Routine Description:\r
992\r
993 wait for Ehc halt or timeout\r
4d1fe68e 994\r
562d2849 995Arguments:\r
996\r
4d1fe68e 997 HcDev - USB2_HC_DEV\r
562d2849 998 Timeout - timeout threshold\r
4d1fe68e 999\r
562d2849 1000Returns:\r
1001\r
1002 EFI_SUCCESS Success\r
1003 EFI_TIMEOUT Timeout\r
4d1fe68e 1004\r
562d2849 1005--*/\r
1006;\r
1007\r
1008EFI_STATUS\r
1009WaitForEhcNotHalt (\r
1010 IN USB2_HC_DEV *HcDev,\r
1011 IN UINTN Timeout\r
1012 )\r
1013/*++\r
1014\r
1015Routine Description:\r
1016\r
1017 wait for Ehc not halt or timeout\r
4d1fe68e 1018\r
562d2849 1019Arguments:\r
1020\r
4d1fe68e 1021 HcDev - USB2_HC_DEV\r
562d2849 1022 Timeout - timeout threshold\r
4d1fe68e 1023\r
562d2849 1024Returns:\r
1025\r
1026 EFI_SUCCESS Success\r
1027 EFI_TIMEOUT Timeout\r
4d1fe68e 1028\r
562d2849 1029--*/\r
1030;\r
1031\r
1032EFI_STATUS\r
1033WaitForEhcDoorbell (\r
1034 IN USB2_HC_DEV *HcDev,\r
1035 IN UINTN Timeout\r
1036 )\r
1037/*++\r
1038\r
1039Routine Description:\r
1040\r
1041 Wait for periodic schedule disable or timeout\r
1042\r
1043Arguments:\r
1044\r
4d1fe68e 1045 HcDev - USB2_HC_DEV\r
562d2849 1046 Timeout - timeout threshold\r
1047\r
1048Returns:\r
1049\r
1050 EFI_SUCCESS Success\r
1051 EFI_TIMEOUT Timeout\r
4d1fe68e 1052\r
562d2849 1053--*/\r
1054;\r
1055\r
1056EFI_STATUS\r
1057WaitForAsyncScheduleEnable (\r
1058 IN USB2_HC_DEV *HcDev,\r
1059 IN UINTN Timeout\r
1060 )\r
1061/*++\r
1062\r
1063Routine Description:\r
1064\r
1065 Wait for Ehc asynchronous schedule enable or timeout\r
4d1fe68e 1066\r
562d2849 1067Arguments:\r
1068\r
4d1fe68e 1069 HcDev - USB2_HC_DEV\r
562d2849 1070 Timeout - timeout threshold\r
4d1fe68e 1071\r
562d2849 1072Returns:\r
1073\r
1074 EFI_SUCCESS Success\r
1075 EFI_TIMEOUT Timeout\r
4d1fe68e 1076\r
562d2849 1077--*/\r
1078;\r
1079\r
1080EFI_STATUS\r
1081WaitForAsyncScheduleDisable (\r
1082 IN USB2_HC_DEV *HcDev,\r
1083 IN UINTN Timeout\r
1084 )\r
1085/*++\r
1086\r
1087Routine Description:\r
1088\r
1089 Wait for Ehc asynchronous schedule disable or timeout\r
4d1fe68e 1090\r
562d2849 1091Arguments:\r
1092\r
4d1fe68e 1093 HcDev - USB2_HC_DEV\r
562d2849 1094 Timeout - timeout threshold\r
4d1fe68e 1095\r
562d2849 1096Returns:\r
1097\r
1098 EFI_SUCCESS Success\r
1099 EFI_TIMEOUT Timeout\r
4d1fe68e 1100\r
562d2849 1101--*/\r
1102;\r
1103\r
1104EFI_STATUS\r
1105WaitForPeriodicScheduleEnable (\r
1106 IN USB2_HC_DEV *HcDev,\r
1107 IN UINTN Timeout\r
1108 )\r
1109/*++\r
1110\r
1111Routine Description:\r
1112\r
1113 Wait for Ehc periodic schedule enable or timeout\r
4d1fe68e 1114\r
562d2849 1115Arguments:\r
1116\r
4d1fe68e 1117 HcDev - USB2_HC_DEV\r
562d2849 1118 Timeout - timeout threshold\r
4d1fe68e 1119\r
562d2849 1120Returns:\r
1121\r
1122 EFI_SUCCESS Success\r
1123 EFI_TIMEOUT Timeout\r
4d1fe68e 1124\r
562d2849 1125--*/\r
1126;\r
1127\r
1128EFI_STATUS\r
1129WaitForPeriodicScheduleDisable (\r
1130 IN USB2_HC_DEV *HcDev,\r
1131 IN UINTN Timeout\r
1132 )\r
1133/*++\r
1134\r
1135Routine Description:\r
1136\r
1137 Wait for periodic schedule disable or timeout\r
4d1fe68e 1138\r
562d2849 1139Arguments:\r
1140\r
4d1fe68e 1141 HcDev - USB2_HC_DEV\r
562d2849 1142 Timeout - timeout threshold\r
4d1fe68e 1143\r
562d2849 1144Returns:\r
1145\r
1146 EFI_SUCCESS Success\r
1147 EFI_TIMEOUT Timeout\r
4d1fe68e 1148\r
562d2849 1149--*/\r
1150;\r
1151\r
1152EFI_STATUS\r
1153GetCapabilityLen (\r
1154 IN USB2_HC_DEV *HcDev\r
1155 )\r
1156/*++\r
1157\r
1158Routine Description:\r
1159\r
1160 Get the length of capability register\r
4d1fe68e 1161\r
562d2849 1162Arguments:\r
1163\r
4d1fe68e 1164 HcDev - USB2_HC_DEV\r
1165\r
562d2849 1166Returns:\r
1167\r
1168 EFI_SUCCESS Success\r
1169 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1170\r
562d2849 1171--*/\r
1172;\r
1173\r
1174EFI_STATUS\r
1175SetFrameListBaseAddr (\r
1176 IN USB2_HC_DEV *HcDev,\r
1177 IN UINT32 FrameBuffer\r
1178 )\r
1179/*++\r
1180\r
1181Routine Description:\r
1182\r
1183 Set base address of frame list first entry\r
4d1fe68e 1184\r
562d2849 1185Arguments:\r
1186\r
4d1fe68e 1187 HcDev - USB2_HC_DEV\r
562d2849 1188 FrameBuffer - base address of first entry of frame list\r
4d1fe68e 1189\r
562d2849 1190Returns:\r
1191\r
1192 EFI_SUCCESS Success\r
1193 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1194\r
562d2849 1195--*/\r
1196;\r
1197\r
1198EFI_STATUS\r
1199SetAsyncListAddr (\r
1200 IN USB2_HC_DEV *HcDev,\r
1201 IN EHCI_QH_ENTITY *QhPtr\r
1202 )\r
1203/*++\r
1204\r
1205Routine Description:\r
1206\r
1207 Set address of first Async schedule Qh\r
4d1fe68e 1208\r
562d2849 1209Arguments:\r
1210\r
4d1fe68e 1211 HcDev - USB2_HC_DEV\r
562d2849 1212 QhPtr - A pointer to first Qh in the Async schedule\r
4d1fe68e 1213\r
562d2849 1214Returns:\r
1215\r
1216 EFI_SUCCESS Success\r
1217 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1218\r
562d2849 1219--*/\r
1220;\r
1221\r
1222EFI_STATUS\r
1223SetCtrlDataStructSeg (\r
1224 IN USB2_HC_DEV *HcDev\r
1225 )\r
1226/*++\r
1227\r
1228Routine Description:\r
1229\r
1230 Set address of first Async schedule Qh\r
4d1fe68e 1231\r
562d2849 1232Arguments:\r
1233\r
4d1fe68e 1234 HcDev - USB2_HC_DEV\r
562d2849 1235 QhPtr - A pointer to first Qh in the Async schedule\r
4d1fe68e 1236\r
562d2849 1237Returns:\r
1238\r
1239 EFI_SUCCESS Success\r
1240 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1241\r
562d2849 1242--*/\r
1243;\r
1244\r
1245EFI_STATUS\r
1246SetPortRoutingEhc (\r
1247 IN USB2_HC_DEV *HcDev\r
1248 )\r
1249/*++\r
1250\r
1251Routine Description:\r
1252\r
1253 Set Ehc port routing bit\r
4d1fe68e 1254\r
562d2849 1255Arguments:\r
1256\r
4d1fe68e 1257 HcDev - USB2_HC_DEV\r
1258\r
562d2849 1259Returns:\r
1260\r
1261 EFI_SUCCESS Success\r
1262 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1263\r
562d2849 1264--*/\r
1265;\r
1266\r
1267EFI_STATUS\r
1268EnablePeriodicSchedule (\r
1269 IN USB2_HC_DEV *HcDev\r
1270 )\r
1271/*++\r
1272\r
1273Routine Description:\r
1274\r
1275 Enable periodic schedule\r
4d1fe68e 1276\r
562d2849 1277Arguments:\r
1278\r
4d1fe68e 1279 HcDev - USB2_HC_DEV\r
1280\r
562d2849 1281Returns:\r
1282\r
1283 EFI_SUCCESS Success\r
1284 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1285\r
562d2849 1286--*/\r
1287;\r
1288\r
1289EFI_STATUS\r
1290DisablePeriodicSchedule (\r
1291 IN USB2_HC_DEV *HcDev\r
1292 )\r
1293/*++\r
1294\r
1295Routine Description:\r
1296\r
1297 Disable periodic schedule\r
4d1fe68e 1298\r
562d2849 1299Arguments:\r
1300\r
4d1fe68e 1301 HcDev - USB2_HC_DEV\r
1302\r
562d2849 1303Returns:\r
1304\r
1305 EFI_SUCCESS Success\r
1306 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1307\r
562d2849 1308--*/\r
1309;\r
1310\r
1311EFI_STATUS\r
1312EnableAsynchronousSchedule (\r
1313 IN USB2_HC_DEV *HcDev\r
1314 )\r
1315/*++\r
1316\r
1317Routine Description:\r
1318\r
1319 Enable asynchrounous schedule\r
4d1fe68e 1320\r
562d2849 1321Arguments:\r
1322\r
4d1fe68e 1323 HcDev - USB2_HC_DEV\r
1324\r
562d2849 1325Returns:\r\r
1326\r
1327 EFI_SUCCESS Success\r
1328 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1329\r
562d2849 1330--*/\r
1331;\r
1332\r
1333EFI_STATUS\r
1334DisableAsynchronousSchedule (\r
1335 IN USB2_HC_DEV *HcDev\r
1336 )\r
1337/*++\r
1338\r
1339Routine Description:\r
1340\r
1341 Disable asynchrounous schedule\r
4d1fe68e 1342\r
562d2849 1343Arguments:\r
1344\r
4d1fe68e 1345 HcDev - USB2_HC_DEV\r
1346\r
562d2849 1347Returns:\r
1348\r
1349 EFI_SUCCESS Success\r
1350 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1351\r
562d2849 1352--*/\r
1353;\r
1354\r
1355EFI_STATUS\r
1356StartScheduleExecution (\r
1357 IN USB2_HC_DEV *HcDev\r
1358 )\r
1359/*++\r
1360\r
1361Routine Description:\r
1362\r
1363 Start Ehc schedule execution\r
4d1fe68e 1364\r
562d2849 1365Arguments:\r
1366\r
4d1fe68e 1367 HcDev - USB2_HC_DEV\r
1368\r
562d2849 1369Returns:\r
1370\r
1371 EFI_SUCCESS Success\r
1372 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1373\r
562d2849 1374--*/\r
1375;\r
1376\r
1377EFI_STATUS\r
1378ResetEhc (\r
1379 IN USB2_HC_DEV *HcDev\r
1380 )\r
1381/*++\r
1382\r
1383Routine Description:\r
1384\r
1385 Reset Ehc\r
4d1fe68e 1386\r
562d2849 1387Arguments:\r
1388\r
4d1fe68e 1389 HcDev - USB2_HC_DEV\r
1390\r
562d2849 1391Returns:\r
1392\r
1393 EFI_SUCCESS Success\r
1394 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1395\r
562d2849 1396--*/\r
1397;\r
1398\r
1399EFI_STATUS\r
1400ClearEhcAllStatus (\r
1401 IN USB2_HC_DEV *HcDev\r
1402 )\r
1403/*++\r
1404\r
1405Routine Description:\r
1406\r
1407 Clear Ehc all status bits\r
4d1fe68e 1408\r
562d2849 1409Arguments:\r
1410\r
4d1fe68e 1411 HcDev - USB2_HC_DEV\r
1412\r
562d2849 1413Returns:\r
1414\r
1415 EFI_SUCCESS Success\r
1416 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1417\r
562d2849 1418--*/\r
1419;\r
1420\r
1421//\r
1422// EhciSched Functions\r
1423//\r
1424EFI_STATUS\r
1425InitialPeriodicFrameList (\r
1426 IN USB2_HC_DEV *HcDev,\r
1427 IN UINTN Length\r
1428 )\r
1429/*++\r
1430\r
1431Routine Description:\r
1432\r
1433 Initialize Periodic Schedule Frame List\r
1434\r
1435Arguments:\r
1436\r
1437 HcDev - USB2_HC_DEV\r
1438 Length - Frame List Length\r
4d1fe68e 1439\r
562d2849 1440Returns:\r
1441\r
1442 EFI_SUCCESS Success\r
1443 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1444\r
562d2849 1445--*/\r
1446;\r
1447\r
1448VOID\r
1449DeinitialPeriodicFrameList (\r
1450 IN USB2_HC_DEV *HcDev\r
1451 )\r
1452/*++\r
1453\r
1454Routine Description:\r
1455\r
1456 Deinitialize Periodic Schedule Frame List\r
1457\r
1458Arguments:\r
1459\r
1460 HcDev - USB2_HC_DEV\r
1461\r
1462Returns:\r
1463\r
1464 VOID\r
4d1fe68e 1465\r
562d2849 1466--*/\r
1467;\r
1468\r
1469EFI_STATUS\r
1470CreatePollingTimer (\r
1471 IN USB2_HC_DEV *HcDev,\r
1472 IN EFI_EVENT_NOTIFY NotifyFunction\r
1473 )\r
1474/*++\r
1475\r
1476Routine Description:\r
1477\r
1478 Create Async Request Polling Timer\r
1479\r
1480Arguments:\r
1481\r
1482 HcDev - USB2_HC_DEV\r
1483 NotifyFunction - Timer Notify Function\r
4d1fe68e 1484\r
562d2849 1485Returns:\r
1486\r
1487 EFI_SUCCESS Success\r
1488 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1489\r
562d2849 1490--*/\r
1491;\r
1492\r
1493EFI_STATUS\r
1494DestoryPollingTimer (\r
1495 IN USB2_HC_DEV *HcDev\r
1496 )\r
1497/*++\r
1498\r
1499Routine Description:\r
1500\r
1501 Destory Async Request Polling Timer\r
1502\r
1503Arguments:\r
1504\r
1505 HcDev - USB2_HC_DEV\r
4d1fe68e 1506\r
562d2849 1507Returns:\r
1508\r
1509 EFI_SUCCESS Success\r
1510 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1511\r
562d2849 1512--*/\r
1513;\r
1514\r
1515EFI_STATUS\r
1516StartPollingTimer (\r
1517 IN USB2_HC_DEV *HcDev\r
1518 )\r
1519/*++\r
1520\r
1521Routine Description:\r
1522\r
1523 Start Async Request Polling Timer\r
1524\r
1525Arguments:\r
1526\r
1527 HcDev - USB2_HC_DEV\r
4d1fe68e 1528\r
562d2849 1529Returns:\r
1530\r
1531 EFI_SUCCESS Success\r
1532 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1533\r
562d2849 1534--*/\r
1535;\r
1536\r
1537EFI_STATUS\r
1538StopPollingTimer (\r
1539 IN USB2_HC_DEV *HcDev\r
1540 )\r
1541/*++\r
1542\r
1543Routine Description:\r
1544\r
1545 Stop Async Request Polling Timer\r
1546\r
1547Arguments:\r
1548\r
1549 HcDev - USB2_HC_DEV\r
4d1fe68e 1550\r
562d2849 1551Returns:\r
1552\r
1553 EFI_SUCCESS Success\r
1554 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1555\r
562d2849 1556--*/\r
1557;\r
1558\r
1559EFI_STATUS\r
1560CreateQh (\r
1561 IN USB2_HC_DEV *HcDev,\r
1562 IN UINT8 DeviceAddr,\r
1563 IN UINT8 Endpoint,\r
1564 IN UINT8 DeviceSpeed,\r
1565 IN UINTN MaxPacketLen,\r
1566 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1567 )\r
1568/*++\r
1569\r
1570Routine Description:\r
1571\r
1572 Create Qh Structure and Pre-Initialize\r
1573\r
1574Arguments:\r
1575\r
4d1fe68e 1576 HcDev - USB2_HC_DEV\r
562d2849 1577 DeviceAddr - Address of Device\r
1578 Endpoint - Endpoint Number\r
1579 DeviceSpeed - Device Speed\r
1580 MaxPacketLen - Max Length of one Packet\r
1581 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1582\r
562d2849 1583Returns:\r
1584\r
1585 EFI_SUCCESS Success\r
1586 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1587\r
562d2849 1588--*/\r
1589;\r
1590\r
1591EFI_STATUS\r
1592CreateControlQh (\r
1593 IN USB2_HC_DEV *HcDev,\r
1594 IN UINT8 DeviceAddr,\r
1595 IN UINT8 DeviceSpeed,\r
1596 IN UINTN MaxPacketLen,\r
1597 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1598 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1599 )\r
1600/*++\r
1601\r
1602Routine Description:\r
1603\r
1604 Create Qh for Control Transfer\r
1605\r
1606Arguments:\r
1607\r
4d1fe68e 1608 HcDev - USB2_HC_DEV\r
562d2849 1609 DeviceAddr - Address of Device\r
1610 DeviceSpeed - Device Speed\r
1611 MaxPacketLen - Max Length of one Packet\r
1612 Translator - Translator Transaction for SplitX\r
1613 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1614\r
562d2849 1615Returns:\r
1616\r
1617 EFI_SUCCESS Success\r
1618 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1619\r
562d2849 1620--*/\r
1621;\r
1622\r
1623EFI_STATUS\r
1624CreateBulkQh (\r
1625 IN USB2_HC_DEV *HcDev,\r
1626 IN UINT8 DeviceAddr,\r
1627 IN UINT8 EndPointAddr,\r
1628 IN UINT8 DeviceSpeed,\r
1629 IN UINT8 DataToggle,\r
1630 IN UINTN MaxPacketLen,\r
1631 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1632 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1633 )\r
1634/*++\r
1635\r
1636Routine Description:\r
1637\r
1638 Create Qh for Bulk Transfer\r
1639\r
1640Arguments:\r
1641\r
4d1fe68e 1642 HcDev - USB2_HC_DEV\r
562d2849 1643 DeviceAddr - Address of Device\r
1644 EndPointAddr - Address of Endpoint\r
1645 DeviceSpeed - Device Speed\r
1646 MaxPacketLen - Max Length of one Packet\r
1647 Translator - Translator Transaction for SplitX\r
1648 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1649\r
562d2849 1650Returns:\r
1651\r
1652 EFI_SUCCESS Success\r
1653 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1654\r
562d2849 1655--*/\r
1656;\r
1657\r
1658EFI_STATUS\r
1659CreateInterruptQh (\r
1660 IN USB2_HC_DEV *HcDev,\r
1661 IN UINT8 DeviceAddr,\r
1662 IN UINT8 EndPointAddr,\r
1663 IN UINT8 DeviceSpeed,\r
1664 IN UINT8 DataToggle,\r
1665 IN UINTN MaxPacketLen,\r
1666 IN UINTN Interval,\r
1667 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1668 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1669 )\r
1670/*++\r
1671\r
1672Routine Description:\r
1673\r
1674 Create Qh for Control Transfer\r
1675\r
1676Arguments:\r
1677\r
4d1fe68e 1678 HcDev - USB2_HC_DEV\r
562d2849 1679 DeviceAddr - Address of Device\r
1680 EndPointAddr - Address of Endpoint\r
1681 DeviceSpeed - Device Speed\r
1682 MaxPacketLen - Max Length of one Packet\r
1683 Interval - value of interval\r
1684 Translator - Translator Transaction for SplitX\r
1685 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1686\r
562d2849 1687Returns:\r
1688\r
1689 EFI_SUCCESS Success\r
1690 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1691\r
562d2849 1692--*/\r
1693;\r
1694\r
1695VOID\r
1696DestoryQh (\r
1697 IN USB2_HC_DEV *HcDev,\r
1698 IN EHCI_QH_ENTITY *QhPtr\r
1699 )\r
1700/*++\r
1701\r
1702Routine Description:\r
1703\r
4d1fe68e 1704 Destory Qh Structure\r
1705\r
562d2849 1706Arguments:\r
1707\r
4d1fe68e 1708 HcDev - USB2_HC_DEV\r
562d2849 1709 QhPtr - A pointer to Qh\r
4d1fe68e 1710\r
562d2849 1711Returns:\r
1712\r
1713 VOID\r
4d1fe68e 1714\r
562d2849 1715--*/\r
1716;\r
1717\r
1718EFI_STATUS\r
1719CreateQtd (\r
1720 IN USB2_HC_DEV *HcDev,\r
1721 IN UINT8 *DataPtr,\r
1722 IN UINTN DataLen,\r
1723 IN UINT8 PktId,\r
1724 IN UINT8 Toggle,\r
1725 IN UINT8 QtdStatus,\r
1726 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1727 )\r
1728/*++\r
1729\r
1730Routine Description:\r
1731\r
1732 Create Qtd Structure and Pre-Initialize it\r
1733\r
1734Arguments:\r
1735\r
4d1fe68e 1736 HcDev - USB2_HC_DEV\r
562d2849 1737 DataPtr - A pointer to user data buffer to transfer\r
1738 DataLen - Length of user data to transfer\r
1739 PktId - Packet Identification of this Qtd\r
1740 Toggle - Data Toggle of this Qtd\r
1741 QtdStatus - Default value of status of this Qtd\r
1742 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 1743\r
562d2849 1744Returns:\r
1745\r
1746 EFI_SUCCESS Success\r
1747 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 1748\r
562d2849 1749--*/\r
1750;\r
1751\r
1752EFI_STATUS\r
1753CreateSetupQtd (\r
1754 IN USB2_HC_DEV *HcDev,\r
1755 IN UINT8 *DevReqPtr,\r
1756 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1757 )\r
1758/*++\r
1759\r
1760Routine Description:\r
1761\r
4d1fe68e 1762 Create Qtd Structure for Setup\r
562d2849 1763\r
1764Arguments:\r
1765\r
4d1fe68e 1766 HcDev - USB2_HC_DEV\r
562d2849 1767 DevReqPtr - A pointer to Device Request Data\r
1768 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 1769\r
562d2849 1770Returns:\r
1771\r
1772 EFI_SUCCESS Success\r
1773 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 1774\r
562d2849 1775--*/\r
1776;\r
1777\r
1778EFI_STATUS\r
1779CreateDataQtd (\r
1780 IN USB2_HC_DEV *HcDev,\r
1781 IN UINT8 *DataPtr,\r
1782 IN UINTN DataLen,\r
1783 IN UINT8 PktId,\r
1784 IN UINT8 Toggle,\r
1785 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1786 )\r
1787/*++\r
1788\r
1789Routine Description:\r
1790\r
4d1fe68e 1791 Create Qtd Structure for data\r
562d2849 1792\r
1793Arguments:\r
1794\r
4d1fe68e 1795 HcDev - USB2_HC_DEV\r
562d2849 1796 DataPtr - A pointer to user data buffer to transfer\r
1797 DataLen - Length of user data to transfer\r
1798 PktId - Packet Identification of this Qtd\r
1799 Toggle - Data Toggle of this Qtd\r
1800 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 1801\r
562d2849 1802Returns:\r
1803\r
1804 EFI_SUCCESS Success\r
1805 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 1806\r
562d2849 1807--*/\r
1808;\r
1809\r
1810EFI_STATUS\r
1811CreateStatusQtd (\r
1812 IN USB2_HC_DEV *HcDev,\r
1813 IN UINT8 PktId,\r
1814 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1815 )\r
1816/*++\r
1817\r
1818Routine Description:\r
1819\r
4d1fe68e 1820 Create Qtd Structure for status\r
562d2849 1821\r
1822Arguments:\r
1823\r
4d1fe68e 1824 HcDev - USB2_HC_DEV\r
562d2849 1825 PktId - Packet Identification of this Qtd\r
1826 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 1827\r
562d2849 1828Returns:\r
1829\r
1830 EFI_SUCCESS Success\r
1831 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 1832\r
562d2849 1833--*/\r
1834;\r
1835\r
1836EFI_STATUS\r
1837CreateAltQtd (\r
1838 IN USB2_HC_DEV *HcDev,\r
1839 IN UINT8 PktId,\r
1840 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1841 )\r
1842/*++\r
1843\r
1844Routine Description:\r
1845\r
4d1fe68e 1846 Create Qtd Structure for Alternative\r
562d2849 1847\r
1848Arguments:\r
1849\r
4d1fe68e 1850 HcDev - USB2_HC_DEV\r
562d2849 1851 PktId - Packet Identification of this Qtd\r
1852 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 1853\r
562d2849 1854Returns:\r
1855\r
1856 EFI_SUCCESS Success\r
1857 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 1858\r
562d2849 1859--*/\r
1860;\r
1861\r
1862EFI_STATUS\r
1863CreateControlQtds (\r
1864 IN USB2_HC_DEV *HcDev,\r
1865 IN UINT8 DataPktId,\r
1866 IN UINT8 *RequestCursor,\r
1867 IN UINT8 *DataCursor,\r
1868 IN UINTN DataLen,\r
1869 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1870 OUT EHCI_QTD_ENTITY **ControlQtdsHead\r
1871 )\r
1872/*++\r
1873\r
1874Routine Description:\r
1875\r
4d1fe68e 1876 Create Qtds list for Control Transfer\r
562d2849 1877\r
1878Arguments:\r
1879\r
4d1fe68e 1880 HcDev - USB2_HC_DEV\r
562d2849 1881 DataPktId - Packet Identification of Data Qtds\r
1882 RequestCursor - A pointer to request structure buffer to transfer\r
1883 DataCursor - A pointer to user data buffer to transfer\r
1884 DataLen - Length of user data to transfer\r
1885 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
4d1fe68e 1886\r
562d2849 1887Returns:\r
1888\r
1889 EFI_SUCCESS Success\r
1890 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1891\r
562d2849 1892--*/\r
1893;\r
1894\r
1895EFI_STATUS\r
1896CreateBulkOrInterruptQtds (\r
1897 IN USB2_HC_DEV *HcDev,\r
1898 IN UINT8 PktId,\r
1899 IN UINT8 *DataCursor,\r
1900 IN UINTN DataLen,\r
1901 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1902 OUT EHCI_QTD_ENTITY **QtdsHead\r
1903 )\r
1904/*++\r
1905\r
1906Routine Description:\r
1907\r
4d1fe68e 1908 Create Qtds list for Bulk or Interrupt Transfer\r
562d2849 1909\r
1910Arguments:\r
1911\r
4d1fe68e 1912 HcDev - USB2_HC_DEV\r
562d2849 1913 PktId - Packet Identification of Qtds\r
1914 DataCursor - A pointer to user data buffer to transfer\r
1915 DataLen - Length of user data to transfer\r
1916 DataToggle - Data Toggle to start\r
1917 Translator - Translator Transaction for SplitX\r
1918 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
4d1fe68e 1919\r
562d2849 1920Returns:\r
1921\r
1922 EFI_SUCCESS Success\r
1923 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1924\r
562d2849 1925--*/\r
1926;\r
1927\r
1928VOID\r
1929DestoryQtds (\r
1930 IN USB2_HC_DEV *HcDev,\r
1931 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
1932 )\r
1933/*++\r
1934\r
1935Routine Description:\r
1936\r
1937 Destory all Qtds in the list\r
1938\r
1939Arguments:\r
1940\r
4d1fe68e 1941 HcDev - USB2_HC_DEV\r
1942 FirstQtdPtr - A pointer to first Qtd in the list\r
1943\r
562d2849 1944Returns:\r
1945\r
1946 VOID\r
1947\r
1948--*/\r
1949;\r
1950\r
1951VOID\r
1952LinkQtdToQtd (\r
1953 IN EHCI_QTD_ENTITY *PreQtdPtr,\r
1954 IN EHCI_QTD_ENTITY *QtdPtr\r
1955 )\r
1956/*++\r
1957\r
1958Routine Description:\r
1959\r
1960 Link Qtds together\r
4d1fe68e 1961\r
562d2849 1962Arguments:\r
1963\r
1964 PreQtdPtr - A pointer to pre Qtd\r
1965 QtdPtr - A pointer to next Qtd\r
4d1fe68e 1966\r
562d2849 1967Returns:\r
1968\r
1969 VOID\r
1970\r
1971--*/\r
1972;\r
1973\r
1974VOID\r
1975LinkQtdsToAltQtd (\r
1976 IN EHCI_QTD_ENTITY *FirstQtdPtr,\r
1977 IN EHCI_QTD_ENTITY *AltQtdPtr\r
1978 )\r
1979/*++\r
1980\r
1981Routine Description:\r
1982\r
1983 Link AlterQtds together\r
4d1fe68e 1984\r
562d2849 1985Arguments:\r
1986\r
1987 FirstQtdPtr - A pointer to first Qtd in the list\r
1988 AltQtdPtr - A pointer to alternative Qtd\r
4d1fe68e 1989\r
562d2849 1990Returns:\r
1991 VOID\r
1992\r
1993--*/\r
1994;\r
1995\r
1996VOID\r
1997LinkQtdToQh (\r
1998 IN EHCI_QH_ENTITY *QhPtr,\r
1999 IN EHCI_QTD_ENTITY *QtdEntryPtr\r
2000 )\r
2001/*++\r
2002\r
2003Routine Description:\r
2004\r
2005 Link Qtds list to Qh\r
4d1fe68e 2006\r
562d2849 2007Arguments:\r
2008\r
2009 QhPtr - A pointer to Qh\r
2010 QtdPtr - A pointer to first Qtd in the list\r
4d1fe68e 2011\r
562d2849 2012Returns:\r
2013\r
2014 VOID\r
2015\r
2016--*/\r
2017;\r
2018\r
2019EFI_STATUS\r
2020LinkQhToAsyncList (\r
2021 IN USB2_HC_DEV *HcDev,\r
2022 IN EHCI_QH_ENTITY *QhPtr\r
2023 )\r
2024/*++\r
2025\r
2026Routine Description:\r
2027\r
2028 Link Qh to Async Schedule List\r
4d1fe68e 2029\r
562d2849 2030Arguments:\r
2031\r
4d1fe68e 2032 HcDev - USB2_HC_DEV\r
562d2849 2033 QhPtr - A pointer to Qh\r
4d1fe68e 2034\r
562d2849 2035Returns:\r
2036\r
2037 EFI_SUCCESS Success\r
2038 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2039\r
562d2849 2040--*/\r
2041;\r
2042\r
2043EFI_STATUS\r
2044UnlinkQhFromAsyncList (\r
2045 IN USB2_HC_DEV *HcDev,\r
2046 IN EHCI_QH_ENTITY *QhPtr\r
2047 )\r
2048/*++\r
2049\r
2050Routine Description:\r
2051\r
2052 Unlink Qh from Async Schedule List\r
4d1fe68e 2053\r
562d2849 2054Arguments:\r
2055\r
4d1fe68e 2056 HcDev - USB2_HC_DEV\r
562d2849 2057 QhPtr - A pointer to Qh\r
4d1fe68e 2058\r
562d2849 2059Returns:\r
2060\r
2061 EFI_SUCCESS Success\r
2062 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2063\r
562d2849 2064--*/\r
2065;\r
2066\r
2067VOID\r
2068LinkQhToPeriodicList (\r
2069 IN USB2_HC_DEV *HcDev,\r
2070 IN EHCI_QH_ENTITY *QhPtr\r
2071 )\r
2072/*++\r
2073\r
2074Routine Description:\r
2075\r
2076 Link Qh to Periodic Schedule List\r
4d1fe68e 2077\r
562d2849 2078Arguments:\r
2079\r
4d1fe68e 2080 HcDev - USB2_HC_DEV\r
562d2849 2081 QhPtr - A pointer to Qh\r
4d1fe68e 2082\r
562d2849 2083Returns:\r
2084\r
2085 VOID\r
2086\r
2087--*/\r
2088;\r
2089\r
2090VOID\r
2091UnlinkQhFromPeriodicList (\r
2092 IN USB2_HC_DEV *HcDev,\r
2093 IN EHCI_QH_ENTITY *QhPtr,\r
2094 IN UINTN Interval\r
2095 )\r
2096/*++\r
2097\r
2098Routine Description:\r
2099\r
2100 Unlink Qh from Periodic Schedule List\r
4d1fe68e 2101\r
562d2849 2102Arguments:\r
2103\r
4d1fe68e 2104 HcDev - USB2_HC_DEV\r
562d2849 2105 QhPtr - A pointer to Qh\r
2106 Interval - Interval of this periodic transfer\r
4d1fe68e 2107\r
562d2849 2108Returns:\r
2109\r
2110 VOID\r
4d1fe68e 2111\r
562d2849 2112--*/\r
2113;\r
2114\r
2115VOID\r
2116LinkToAsyncReqeust (\r
2117 IN USB2_HC_DEV *HcDev,\r
2118 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2119 )\r
2120/*++\r
2121\r
2122Routine Description:\r
2123\r
2124 Llink AsyncRequest Entry to Async Request List\r
4d1fe68e 2125\r
562d2849 2126Arguments:\r
2127\r
4d1fe68e 2128 HcDev - USB2_HC_DEV\r
562d2849 2129 AsyncRequestPtr - A pointer to Async Request Entry\r
4d1fe68e 2130\r
562d2849 2131Returns:\r
2132\r
2133 VOID\r
4d1fe68e 2134\r
562d2849 2135--*/\r
2136;\r
2137\r
2138VOID\r
2139UnlinkFromAsyncReqeust (\r
2140 IN USB2_HC_DEV *HcDev,\r
2141 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2142 )\r
2143/*++\r
2144\r
2145Routine Description:\r
2146\r
2147 Unlink AsyncRequest Entry from Async Request List\r
4d1fe68e 2148\r
562d2849 2149Arguments:\r
2150\r
4d1fe68e 2151 HcDev - USB2_HC_DEV\r
562d2849 2152 AsyncRequestPtr - A pointer to Async Request Entry\r
4d1fe68e 2153\r
562d2849 2154Returns:\r
2155\r
2156 VOID\r
4d1fe68e 2157\r
562d2849 2158--*/\r
2159;\r
2160\r
2161UINTN\r
2162GetNumberOfQtd (\r
2163 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2164 )\r
2165/*++\r
2166\r
2167Routine Description:\r
2168\r
2169 Number of Qtds in the list\r
4d1fe68e 2170\r
562d2849 2171Arguments:\r
2172\r
2173 FirstQtdPtr - A pointer to first Qtd in the list\r
4d1fe68e 2174\r
562d2849 2175Returns:\r
2176\r
2177 Number of Qtds in the list\r
2178\r
2179--*/\r
2180;\r
2181\r
562d2849 2182\r
562d2849 2183\r
2184UINTN\r
2185GetCapacityOfQtd (\r
2186 IN UINT8 *BufferCursor\r
2187 )\r
2188/*++\r
2189\r
2190Routine Description:\r
2191\r
2192 Get Capacity of Qtd\r
4d1fe68e 2193\r
562d2849 2194Arguments:\r
2195\r
2196 BufferCursor - BufferCursor of the Qtd\r
4d1fe68e 2197\r
562d2849 2198Returns:\r
2199\r
2200 Capacity of Qtd\r
2201\r
2202--*/\r
2203;\r
2204\r
2205UINTN\r
2206GetApproxiOfInterval (\r
2207 IN UINTN Interval\r
2208 )\r
2209/*++\r
2210\r
2211Routine Description:\r
2212\r
2213 Get the approximate value in the 2 index sequence\r
4d1fe68e 2214\r
562d2849 2215Arguments:\r
2216\r
2217 Interval - the value of interval\r
4d1fe68e 2218\r
562d2849 2219Returns:\r
2220\r
2221 approximate value of interval in the 2 index sequence\r
4d1fe68e 2222\r
562d2849 2223--*/\r
2224;\r
2225\r
2226EHCI_QTD_HW *\r
2227GetQtdNextPointer (\r
2228 IN EHCI_QTD_HW *HwQtdPtr\r
2229 )\r
2230/*++\r
2231\r
2232Routine Description:\r
2233\r
2234 Get Qtd next pointer field\r
4d1fe68e 2235\r
562d2849 2236Arguments:\r
2237\r
2238 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2239\r
562d2849 2240Returns:\r
2241\r
2242 A pointer to next hardware Qtd structure\r
4d1fe68e 2243\r
562d2849 2244--*/\r
2245;\r
2246\r
2247BOOLEAN\r
2248IsQtdStatusActive (\r
2249 IN EHCI_QTD_HW *HwQtdPtr\r
2250 )\r
2251/*++\r
2252\r
2253Routine Description:\r
2254\r
2255 Whether Qtd status is active or not\r
4d1fe68e 2256\r
562d2849 2257Arguments:\r
2258\r
2259 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2260\r
562d2849 2261Returns:\r
2262\r
2263 TRUE Active\r
2264 FALSE Inactive\r
4d1fe68e 2265\r
562d2849 2266--*/\r
2267;\r
2268\r
2269BOOLEAN\r
2270IsQtdStatusHalted (\r
2271 IN EHCI_QTD_HW *HwQtdPtr\r
2272 )\r
2273/*++\r
2274\r
2275Routine Description:\r
2276\r
2277 Whether Qtd status is halted or not\r
4d1fe68e 2278\r
562d2849 2279Arguments:\r
2280\r
2281 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2282\r
562d2849 2283Returns:\r\r
2284\r
2285 TRUE Halted\r
2286 FALSE Not halted\r
4d1fe68e 2287\r
562d2849 2288--*/\r
2289;\r
2290\r
2291BOOLEAN\r
2292IsQtdStatusBufferError (\r
2293 IN EHCI_QTD_HW *HwQtdPtr\r
2294 )\r
2295/*++\r
2296\r
2297Routine Description:\r
2298\r
2299 Whether Qtd status is buffer error or not\r
4d1fe68e 2300\r
562d2849 2301Arguments:\r
2302\r
2303 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2304\r
562d2849 2305Returns:\r
2306\r
2307 TRUE Buffer error\r
2308 FALSE No buffer error\r
4d1fe68e 2309\r
562d2849 2310--*/\r
2311;\r
2312\r
2313BOOLEAN\r
2314IsQtdStatusBabbleError (\r
2315 IN EHCI_QTD_HW *HwQtdPtr\r
2316 )\r
2317/*++\r
2318\r
2319Routine Description:\r
2320\r
2321 Whether Qtd status is babble error or not\r
4d1fe68e 2322\r
562d2849 2323Arguments:\r
2324\r
2325 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2326\r
562d2849 2327Returns:\r
2328\r
2329 TRUE Babble error\r
2330 FALSE No babble error\r
4d1fe68e 2331\r
562d2849 2332--*/\r
2333;\r
2334\r
2335BOOLEAN\r
2336IsQtdStatusTransactionError (\r
2337 IN EHCI_QTD_HW *HwQtdPtr\r
2338 )\r
2339/*++\r
2340\r
2341Routine Description:\r
2342\r
2343 Whether Qtd status is transaction error or not\r
4d1fe68e 2344\r
562d2849 2345Arguments:\r
2346\r
2347 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2348\r
562d2849 2349Returns:\r
2350\r
2351 TRUE Transaction error\r
2352 FALSE No transaction error\r
4d1fe68e 2353\r
562d2849 2354--*/\r
2355;\r
2356\r
2357BOOLEAN\r
2358IsDataInTransfer (\r
2359 IN UINT8 EndPointAddress\r
2360 )\r
2361/*++\r
2362\r
2363Routine Description:\r
2364\r
2365 Whether is a DataIn direction transfer\r
4d1fe68e 2366\r
562d2849 2367Arguments:\r
2368\r
4d1fe68e 2369 EndPointAddress - address of the endpoint\r
2370\r
562d2849 2371Returns:\r
2372\r
2373 TRUE DataIn\r
2374 FALSE DataOut\r
4d1fe68e 2375\r
562d2849 2376--*/\r
2377;\r
2378\r
2379EFI_STATUS\r
2380MapDataBuffer (\r
2381 IN USB2_HC_DEV *HcDev,\r
2382 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
2383 IN OUT VOID *Data,\r
2384 IN OUT UINTN *DataLength,\r
2385 OUT UINT8 *PktId,\r
2386 OUT UINT8 **DataCursor,\r
2387 OUT VOID **DataMap\r
2388 )\r
2389/*++\r
2390\r
2391Routine Description:\r
2392\r
2393 Map address of user data buffer\r
4d1fe68e 2394\r
562d2849 2395Arguments:\r
2396\r
4d1fe68e 2397 HcDev - USB2_HC_DEV\r
562d2849 2398 TransferDirection - direction of transfer\r
4d1fe68e 2399 Data - A pointer to user data buffer\r
562d2849 2400 DataLength - length of user data\r
2401 PktId - Packte Identificaion\r
2402 DataCursor - mapped address to return\r
2403 DataMap - identificaion of this mapping to return\r
4d1fe68e 2404\r
562d2849 2405Returns:\r
2406\r
2407 EFI_SUCCESS Success\r
2408 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2409\r
562d2849 2410--*/\r
2411;\r
2412\r
2413EFI_STATUS\r
2414MapRequestBuffer (\r
2415 IN USB2_HC_DEV *HcDev,\r
2416 IN OUT VOID *Request,\r
2417 OUT UINT8 **RequestCursor,\r
2418 OUT VOID **RequestMap\r
2419 )\r
2420/*++\r
2421\r
2422Routine Description:\r
2423\r
2424 Map address of request structure buffer\r
4d1fe68e 2425\r
562d2849 2426Arguments:\r
2427\r
4d1fe68e 2428 HcDev - USB2_HC_DEV\r
562d2849 2429 Request - A pointer to request structure\r
2430 RequestCursor - Mapped address of request structure to return\r
2431 RequestMap - Identificaion of this mapping to return\r
4d1fe68e 2432\r
562d2849 2433Returns:\r
2434\r
2435 EFI_SUCCESS Success\r
2436 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2437\r
562d2849 2438--*/\r
2439;\r
2440\r
2441VOID\r
2442SetQtdBufferPointer (\r
2443 IN EHCI_QTD_HW *QtdHwPtr,\r
2444 IN VOID *DataPtr,\r
2445 IN UINTN DataLen\r
2446 )\r
2447/*++\r
2448\r
2449Routine Description:\r
2450\r
2451 Set data buffer pointers in Qtd\r
2452\r
2453Arguments:\r
2454\r
4d1fe68e 2455 QtdHwPtr - A pointer to Qtd hardware structure\r
562d2849 2456 DataPtr - A pointer to user data buffer\r
2457 DataLen - Length of the user data buffer\r
4d1fe68e 2458\r
562d2849 2459Returns:\r
2460\r
2461 VOID\r
2462\r
2463--*/\r
2464;\r
2465\r
2466EHCI_QTD_HW *\r
2467GetQtdAlternateNextPointer (\r
2468 IN EHCI_QTD_HW *HwQtdPtr\r
2469 )\r
2470/*++\r
2471\r
2472Routine Description:\r
2473\r
2474 Get Qtd alternate next pointer field\r
4d1fe68e 2475\r
562d2849 2476Arguments:\r
2477\r
2478 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2479\r
562d2849 2480Returns:\r
2481\r
2482 A pointer to hardware alternate Qtd\r
4d1fe68e 2483\r
562d2849 2484--*/\r
2485;\r
2486\r
2487VOID\r
2488ZeroOutQhOverlay (\r
2489 IN EHCI_QH_ENTITY *QhPtr\r
2490 )\r
2491/*++\r
2492\r
2493Routine Description:\r
2494\r
2495 Zero out the fields in Qh structure\r
4d1fe68e 2496\r
562d2849 2497Arguments:\r
2498\r
2499 QhPtr - A pointer to Qh structure\r
4d1fe68e 2500\r
562d2849 2501Returns:\r
2502\r
2503 VOID\r
4d1fe68e 2504\r
562d2849 2505--*/\r
2506;\r
2507\r
2508VOID\r
2509UpdateAsyncRequestTransfer (\r
2510 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,\r
2511 IN UINT32 TransferResult,\r
2512 IN UINTN ErrTDPos\r
2513 )\r
2514/*++\r
2515\r
2516Routine Description:\r
2517\r
2518 Update asynchronous request transfer\r
4d1fe68e 2519\r
562d2849 2520Arguments:\r
2521\r
4d1fe68e 2522 AsyncRequestPtr - A pointer to async request\r
2523 TransferResult - transfer result\r
562d2849 2524 ErrQtdPos - postion of error Qtd\r
4d1fe68e 2525\r
562d2849 2526Returns:\r
2527\r
2528 VOID\r
4d1fe68e 2529\r
562d2849 2530--*/\r
2531;\r
2532\r
2533\r
2534EFI_STATUS\r
2535DeleteAsyncRequestTransfer (\r
2536 IN USB2_HC_DEV *HcDev,\r
2537 IN UINT8 DeviceAddress,\r
2538 IN UINT8 EndPointAddress,\r
2539 OUT UINT8 *DataToggle\r
2540 )\r
2541/*++\r
2542\r
2543Routine Description:\r
2544\r
2545 Delete all asynchronous request transfer\r
4d1fe68e 2546\r
562d2849 2547Arguments:\r
2548\r
4d1fe68e 2549 HcDev - USB2_HC_DEV\r
562d2849 2550 DeviceAddress - address of usb device\r
2551 EndPointAddress - address of endpoint\r
2552 DataToggle - stored data toggle\r
4d1fe68e 2553\r
562d2849 2554Returns:\r
2555\r
2556 EFI_SUCCESS Success\r
2557 EFI_DEVICE_ERROR Fail\r
2558\r
2559--*/\r
2560;\r
2561\r
2562VOID\r
2563CleanUpAllAsyncRequestTransfer (\r
2564 IN USB2_HC_DEV *HcDev\r
2565 )\r
2566/*++\r
2567\r
2568Routine Description:\r
2569\r
2570 Clean up all asynchronous request transfer\r
4d1fe68e 2571\r
562d2849 2572Arguments:\r
2573\r
4d1fe68e 2574 HcDev - USB2_HC_DEV\r
2575\r
562d2849 2576Returns:\r
2577 VOID\r
4d1fe68e 2578\r
562d2849 2579--*/\r
2580;\r
2581\r
2582EFI_STATUS\r
2583ExecuteTransfer (\r
2584 IN USB2_HC_DEV *HcDev,\r
2585 IN BOOLEAN IsControl,\r
2586 IN EHCI_QH_ENTITY *QhPtr,\r
2587 IN OUT UINTN *ActualLen,\r
2588 OUT UINT8 *DataToggle,\r
2589 IN UINTN TimeOut,\r
2590 OUT UINT32 *TransferResult\r
2591 )\r
2592/*++\r
2593\r
2594Routine Description:\r
2595\r
2596 Execute Bulk or SyncInterrupt Transfer\r
2597\r
2598Arguments:\r
2599\r
2600 HcDev - USB2_HC_DEV\r
2601 IsControl - Is control transfer or not\r
2602 QhPtr - A pointer to Qh\r
4d1fe68e 2603 ActualLen - Actual transfered Len\r
562d2849 2604 DataToggle - Data Toggle\r
2605 TimeOut - TimeOut threshold\r
2606 TransferResult - Transfer result\r
4d1fe68e 2607\r
562d2849 2608Returns:\r
2609\r
2610 EFI_SUCCESS Sucess\r
2611 EFI_DEVICE_ERROR Error\r
4d1fe68e 2612\r
562d2849 2613--*/\r
2614;\r
2615\r
2616BOOLEAN\r
2617CheckQtdsTransferResult (\r
2618 IN BOOLEAN IsControl,\r
2619 IN EHCI_QH_ENTITY *QhPtr,\r
2620 OUT UINT32 *Result,\r
2621 OUT UINTN *ErrQtdPos,\r
2622 OUT UINTN *ActualLen\r
2623 )\r
2624/*++\r
2625\r
2626Routine Description:\r
2627\r
2628 Check transfer result of Qtds\r
2629\r
2630Arguments:\r
2631\r
2632 IsControl - Is control transfer or not\r
2633 QhPtr - A pointer to Qh\r
2634 Result - Transfer result\r
2635 ErrQtdPos - Error TD Position\r
2636 ActualLen - Actual Transfer Size\r
2637\r
2638Returns:\r
2639\r
2640 TRUE Qtds finished\r
2641 FALSE Not finish\r
4d1fe68e 2642\r
562d2849 2643--*/\r
2644;\r
2645\r
2646EFI_STATUS\r
2647AsyncRequestMoniter (\r
2648 IN EFI_EVENT Event,\r
2649 IN VOID *Context\r
2650 )\r
2651/*++\r
2652\r
2653Routine Description:\r
4d1fe68e 2654\r
562d2849 2655 Interrupt transfer periodic check handler\r
4d1fe68e 2656\r
562d2849 2657Arguments:\r
2658\r
2659 Event - Interrupt event\r
2660 Context - Pointer to USB2_HC_DEV\r
4d1fe68e 2661\r
562d2849 2662Returns:\r
4d1fe68e 2663\r
562d2849 2664 EFI_SUCCESS Success\r
2665 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2666\r
2667--*/\r
2668;\r
2669\r
2670\r
2671EFI_STATUS\r
2672CreateNULLQH (\r
2673 IN USB2_HC_DEV *HcDev\r
2674 )\r
2675/*++\r
2676\r
2677Routine Description:\r
2678\r
2679 Create the NULL QH to make it as the Async QH header\r
2680\r
2681Arguments:\r
2682\r
2683 HcDev - USB2_HC_DEV\r
2684\r
2685Returns:\r
2686\r
2687 EFI_SUCCESS Success\r
562d2849 2688--*/\r
2689;\r
2690\r
4d1fe68e 2691VOID\r
2692DestroyNULLQH (\r
2693 IN USB2_HC_DEV *HcDev\r
2694 );\r
2695\r
74c56167 2696VOID\r
2697ClearLegacySupport (\r
2698 IN USB2_HC_DEV *HcDev\r
2699 );\r
2700\r
2701VOID\r
2702HostReset (\r
2703 IN USB2_HC_DEV *HcDev\r
2704 );\r
2705\r
4d1fe68e 2706\r
2707VOID\r
74c56167 2708DumpEHCIPortsStatus (\r
2709 IN USB2_HC_DEV *HcDev\r
2710 );\r
4d1fe68e 2711\r
2712\r
562d2849 2713#endif\r
EFI Development Kit II mirror for PVE