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EHCI driver need enable routine and disable Legacy USB
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
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562d2849 1/*++\r
2\r
3Copyright (c) 2006, Intel Corporation \r
4All rights reserved. This program and the accompanying materials \r
5are licensed and made available under the terms and conditions of the BSD License \r
6which accompanies this distribution. The full text of the license may be found at \r
7http://opensource.org/licenses/bsd-license.php \r
8 \r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
11\r
12Module Name:\r
13\r
14 Ehci.h\r
15 \r
16Abstract: \r
17 \r
18\r
19Revision History\r
20--*/\r
21\r
22#ifndef _EHCI_H\r
23#define _EHCI_H\r
24\r
25//\r
26// Universal Host Controller Interface data structures and defines\r
27//\r
28#include <IndustryStandard/pci22.h>\r
29\r
71a62114 30\r
713ace4c 31extern UINTN gEHCDebugLevel;\r
32extern UINTN gEHCErrorLevel;\r
71a62114 33\r
562d2849 34\r
35#define STALL_1_MACRO_SECOND 1\r
36#define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND\r
37#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r
38\r
39#define SETUP_PACKET_PID_CODE 0x02\r
40#define INPUT_PACKET_PID_CODE 0x01\r
41#define OUTPUT_PACKET_PID_CODE 0x0\r
42\r
43#define ITD_SELECT_TYPE 0x0\r
44#define QH_SELECT_TYPE 0x01\r
45#define SITD_SELECT_TYPE 0x02\r
46#define FSTN_SELECT_TYPE 0x03\r
47\r
48#define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND\r
49#define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND\r
50#define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND\r
51#define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND\r
52#define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND\r
53#define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND\r
54\r
55#define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */\r
56\r
57#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1\r
58\r
59#define EHCI_MIN_PACKET_SIZE 8\r
60#define EHCI_MAX_PACKET_SIZE 1024\r
61#define EHCI_MAX_FRAME_LIST_LENGTH 1024\r
62#define EHCI_BLOCK_SIZE_WITH_TT 64\r
63#define EHCI_BLOCK_SIZE 512\r
64#define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)\r
65\r
66#define NAK_COUNT_RELOAD 3\r
67#define QTD_ERROR_COUNTER 1\r
68#define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1\r
69\r
70#define QTD_STATUS_ACTIVE 0x80\r
71#define QTD_STATUS_HALTED 0x40\r
72#define QTD_STATUS_BUFFER_ERR 0x20\r
73#define QTD_STATUS_BABBLE_ERR 0x10\r
74#define QTD_STATUS_TRANSACTION_ERR 0x08\r
75#define QTD_STATUS_DO_STOP_SPLIT 0x02\r
76#define QTD_STATUS_DO_START_SPLIT 0\r
77#define QTD_STATUS_DO_PING 0x01\r
78#define QTD_STATUS_DO_OUT 0\r
79\r
80#define DATA0 0\r
81#define DATA1 1\r
82\r
83#define MICRO_FRAME_0_CHANNEL 0x01\r
84#define MICRO_FRAME_1_CHANNEL 0x02\r
85#define MICRO_FRAME_2_CHANNEL 0x04\r
86#define MICRO_FRAME_3_CHANNEL 0x08\r
87#define MICRO_FRAME_4_CHANNEL 0x10\r
88#define MICRO_FRAME_5_CHANNEL 0x20\r
89#define MICRO_FRAME_6_CHANNEL 0x40\r
90#define MICRO_FRAME_7_CHANNEL 0x80\r
91\r
92#define CONTROL_TRANSFER 0x01\r
93#define BULK_TRANSFER 0x02\r
94#define SYNC_INTERRUPT_TRANSFER 0x04\r
95#define ASYNC_INTERRUPT_TRANSFER 0x08\r
96#define SYNC_ISOCHRONOUS_TRANSFER 0x10\r
97#define ASYNC_ISOCHRONOUS_TRANSFER 0x20\r
98\r
99\r
100//\r
101// Enhanced Host Controller Registers definitions\r
102//\r
103extern UINT32 mUsbCapabilityLen;\r
104extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
105extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
106\r
107#define USBCMD 0x0 /* Command Register Offset 00-03h */\r
108#define USBCMD_RS 0x01 /* Run / Stop */\r
109#define USBCMD_HCRESET 0x02 /* Host controller reset */\r
110#define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */\r
111#define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */\r
112#define USBCMD_PSE 0x10 /* Periodic schedule enable */\r
113#define USBCMD_ASE 0x20 /* Asynchronous schedule enable */\r
114#define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */\r
115\r
116#define USBSTS 0x04 /* Statue Register Offset 04-07h */\r
117#define USBSTS_HSE 0x10 /* Host system error */\r
118#define USBSTS_IAA 0x20 /* Interrupt on async advance */\r
119#define USBSTS_HCH 0x1000 /* Host controller halted */\r
120#define USBSTS_PSS 0x4000 /* Periodic schedule status */\r
121#define USBSTS_ASS 0x8000 /* Asynchronous schedule status */\r
122\r
123#define USBINTR 0x08 /* Command Register Offset 08-0bh */\r
124\r
125#define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */\r
126\r
127#define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */\r
128\r
129#define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */\r
130\r
131#define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */\r
132\r
133#define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */\r
134#define CONFIGFLAG_CF 0x01 /* Configure Flag */\r
135\r
136#define PORTSC 0x44 /* Port Status/Control Offset 44-47h */\r
137#define PORTSC_CCS 0x01 /* Current Connect Status*/\r
138#define PORTSC_CSC 0x02 /* Connect Status Change */\r
139#define PORTSC_PED 0x04 /* Port Enable / Disable */\r
140#define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */\r
141#define PORTSC_OCA 0x10 /* Over current Active */\r
142#define PORTSC_OCC 0x20 /* Over current Change */\r
143#define PORTSC_FPR 0x40 /* Force Port Resume */\r
144#define PORTSC_SUSP 0x80 /* Port Suspend State */\r
145#define PORTSC_PR 0x100 /* Port Reset */\r
146#define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */\r
147#define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */\r
148#define PORTSC_PP 0x1000 /* Port Power */\r
149#define PORTSC_PO 0x2000 /* Port Owner */\r
150\r
151#define CAPLENGTH 0 /* Capability Register Length 00h */\r
152\r
153#define HCIVERSION 0x02 /* Interface Version Number 02-03h */\r
154\r
155#define HCSPARAMS 0x04 /* Structural Parameters 04-07h */\r
156#define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */\r
157\r
158#define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */\r
159#define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */\r
160#define HCCP_PFLF 0x02 /* Programmable Frame List Flag */\r
161#define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */\r
162\r
163#define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */\r
164\r
165#define CLASSC 0x09 /* Class Code 09-0bh */\r
166\r
167#define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */\r
168\r
169#define SBRN 0x60 /* Serial Bus Release Number 60h */\r
170\r
171#define FLADJ 0x61 /* Frame Length Adjustment Register 61h */\r
172\r
173#define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */\r
174\r
175//\r
176// PCI Configuration Registers\r
177//\r
178#define EHCI_PCI_CLASSC 0x09\r
179#define EHCI_PCI_MEMORY_BASE 0x10\r
180\r
181//\r
182// Memory Offset Registers\r
183//\r
184#define EHCI_MEMORY_CAPLENGTH 0x0\r
185#define EHCI_MEMORY_CONFIGFLAG 0x40\r
186\r
187//\r
188// USB Base Class Code,Sub-Class Code and Programming Interface\r
189//\r
190#define PCI_CLASSC_PI_EHCI 0x20\r
191\r
192#define SETUP_PACKET_ID 0x2D\r
193#define INPUT_PACKET_ID 0x69\r
194#define OUTPUT_PACKET_ID 0xE1\r
195#define ERROR_PACKET_ID 0x55\r
196\r
71a62114 197#define bit(a) (1 << (a))\r
198\r
199#define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))\r
200#define GET_32B_TO_63B(Addr) ((UINTN)RShiftU64((UINTN) Addr, 32) & (0xffffffff))\r
562d2849 201\r
202\r
203//\r
204// Ehci Data and Ctrl Structures\r
205//\r
206#pragma pack(1)\r
207\r
208typedef struct {\r
209 UINT8 PI;\r
210 UINT8 SubClassCode;\r
211 UINT8 BaseCode;\r
212} USB_CLASSC;\r
213\r
214typedef struct {\r
215 UINT32 NextQtdTerminate : 1;\r
216 UINT32 Rsvd1 : 4;\r
217 UINT32 NextQtdPointer : 27;\r
218\r
219 UINT32 AltNextQtdTerminate : 1;\r
220 UINT32 Rsvd2 : 4;\r
221 UINT32 AltNextQtdPointer : 27;\r
222\r
223 UINT32 Status : 8;\r
224 UINT32 PidCode : 2;\r
225 UINT32 ErrorCount : 2;\r
226 UINT32 CurrentPage : 3;\r
227 UINT32 InterruptOnComplete : 1;\r
228 UINT32 TotalBytes : 15;\r
229 UINT32 DataToggle : 1;\r
230\r
231 UINT32 CurrentOffset : 12;\r
232 UINT32 BufferPointer0 : 20;\r
233\r
234 UINT32 Rsvd3 : 12;\r
235 UINT32 BufferPointer1 : 20;\r
236\r
237 UINT32 Rsvd4 : 12;\r
238 UINT32 BufferPointer2 : 20;\r
239\r
240 UINT32 Rsvd5 : 12;\r
241 UINT32 BufferPointer3 : 20;\r
242\r
243 UINT32 Rsvd6 : 12;\r
244 UINT32 BufferPointer4 : 20;\r
245\r
246 UINT32 ExtBufferPointer0;\r
247 UINT32 ExtBufferPointer1;\r
248 UINT32 ExtBufferPointer2;\r
249 UINT32 ExtBufferPointer3;\r
250 UINT32 ExtBufferPointer4;\r
251} EHCI_QTD_HW;\r
252\r
253typedef struct {\r
254 UINT32 QhTerminate : 1;\r
255 UINT32 SelectType : 2;\r
256 UINT32 Rsvd1 : 2;\r
257 UINT32 QhHorizontalPointer : 27;\r
258\r
259 UINT32 DeviceAddr : 7;\r
260 UINT32 Inactive : 1;\r
261 UINT32 EndpointNum : 4;\r
262 UINT32 EndpointSpeed : 2;\r
263 UINT32 DataToggleControl : 1;\r
264 UINT32 HeadReclamationFlag : 1;\r
265 UINT32 MaxPacketLen : 11;\r
266 UINT32 ControlEndpointFlag : 1;\r
267 UINT32 NakCountReload : 4;\r
268\r
269 UINT32 InerruptScheduleMask : 8;\r
270 UINT32 SplitComletionMask : 8;\r
271 UINT32 HubAddr : 7;\r
272 UINT32 PortNum : 7;\r
273 UINT32 Multiplier : 2;\r
274\r
275 UINT32 Rsvd2 : 5;\r
276 UINT32 CurrentQtdPointer : 27;\r
277\r
278 UINT32 NextQtdTerminate : 1;\r
279 UINT32 Rsvd3 : 4;\r
280 UINT32 NextQtdPointer : 27;\r
281\r
282 UINT32 AltNextQtdTerminate : 1;\r
283 UINT32 NakCount : 4;\r
284 UINT32 AltNextQtdPointer : 27;\r
285\r
286 UINT32 Status : 8;\r
287 UINT32 PidCode : 2;\r
288 UINT32 ErrorCount : 2;\r
289 UINT32 CurrentPage : 3;\r
290 UINT32 InterruptOnComplete : 1;\r
291 UINT32 TotalBytes : 15;\r
292 UINT32 DataToggle : 1;\r
293\r
294 UINT32 CurrentOffset : 12;\r
295 UINT32 BufferPointer0 : 20;\r
296\r
297 UINT32 CompleteSplitMask : 8;\r
298 UINT32 Rsvd4 : 4;\r
299 UINT32 BufferPointer1 : 20;\r
300\r
301 UINT32 FrameTag : 5;\r
302 UINT32 SplitBytes : 7;\r
303 UINT32 BufferPointer2 : 20;\r
304\r
305 UINT32 Rsvd5 : 12;\r
306 UINT32 BufferPointer3 : 20;\r
307\r
308 UINT32 Rsvd6 : 12;\r
309 UINT32 BufferPointer4 : 20;\r
310\r
311 UINT32 ExtBufferPointer0;\r
312 UINT32 ExtBufferPointer1;\r
313 UINT32 ExtBufferPointer2;\r
314 UINT32 ExtBufferPointer3;\r
315 UINT32 ExtBufferPointer4;\r
316} EHCI_QH_HW;\r
317\r
318typedef struct {\r
319 UINT32 LinkTerminate : 1;\r
320 UINT32 SelectType : 2;\r
321 UINT32 Rsvd : 2;\r
322 UINT32 LinkPointer : 27;\r
323} FRAME_LIST_ENTRY;\r
324\r
325#pragma pack()\r
326\r
327typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;\r
328typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;\r
329typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;\r
330\r
ffac4bcb 331struct _EHCI_QTD_ENTITY {\r
562d2849 332 EHCI_QTD_HW Qtd;\r
333 UINT32 TotalBytes;\r
334 UINT32 StaticTotalBytes;\r
335 UINT32 StaticCurrentOffset;\r
336 EHCI_QTD_ENTITY *Prev;\r
337 EHCI_QTD_ENTITY *Next;\r
338 EHCI_QTD_ENTITY *AltNext;\r
339 EHCI_QH_ENTITY *SelfQh;\r
ffac4bcb 340};\r
562d2849 341\r
ffac4bcb 342struct _EHCI_QH_ENTITY {\r
562d2849 343 EHCI_QH_HW Qh;\r
344 EHCI_QH_ENTITY *Next;\r
345 EHCI_QH_ENTITY *Prev;\r
346 EHCI_QTD_ENTITY *FirstQtdPtr;\r
347 EHCI_QTD_ENTITY *LastQtdPtr;\r
348 EHCI_QTD_ENTITY *AltQtdPtr;\r
349 UINTN Interval;\r
350 UINT8 TransferType;\r
ffac4bcb 351};\r
562d2849 352\r
353#define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)\r
354#define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)\r
355\r
356\r
357//\r
358// Ehci Managment Structures\r
359//\r
360#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
361\r
362#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
363\r
ffac4bcb 364struct _EHCI_ASYNC_REQUEST {\r
562d2849 365 UINT8 TransferType;\r
366 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;\r
367 VOID *Context;\r
368 EHCI_ASYNC_REQUEST *Prev;\r
369 EHCI_ASYNC_REQUEST *Next;\r
370 EHCI_QH_ENTITY *QhPtr;\r
ffac4bcb 371};\r
562d2849 372\r
373typedef struct _MEMORY_MANAGE_HEADER {\r
374 UINT8 *BitArrayPtr;\r
375 UINTN BitArraySizeInBytes;\r
376 UINT8 *MemoryBlockPtr;\r
377 UINTN MemoryBlockSizeInBytes;\r
378 VOID *Mapping;\r
379 struct _MEMORY_MANAGE_HEADER *Next;\r
380} MEMORY_MANAGE_HEADER;\r
381\r
382typedef struct _USB2_HC_DEV {\r
383 UINTN Signature;\r
384 EFI_PCI_IO_PROTOCOL *PciIo;\r
385 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
386 UINTN PeriodicFrameListLength;\r
387 VOID *PeriodicFrameListBuffer;\r
388 VOID *PeriodicFrameListMap;\r
389 VOID *AsyncList;\r
390 EHCI_ASYNC_REQUEST *AsyncRequestList;\r
391 EFI_EVENT AsyncRequestEvent;\r
392 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
393 MEMORY_MANAGE_HEADER *MemoryHeader;\r
394 UINT8 Is64BitCapable;\r
395 UINT32 High32BitAddr;\r
396} USB2_HC_DEV;\r
397\r
398\r
399//\r
400// Internal Functions Declaration\r
401//\r
402\r
403//\r
404// EhciMem Functions\r
405//\r
406EFI_STATUS\r
407CreateMemoryBlock (\r
408 IN USB2_HC_DEV *HcDev,\r
409 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
410 IN UINTN MemoryBlockSizeInPages\r
411 )\r
412/*++\r
413\r
414Routine Description:\r
415\r
416 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,\r
417 and use PciIo->Map to map the common buffer for Bus Master Read/Write.\r
418\r
419Arguments:\r
420\r
421 HcDev - USB2_HC_DEV\r
422 MemoryHeader - MEMORY_MANAGE_HEADER to output\r
423 MemoryBlockSizeInPages - MemoryBlockSizeInPages\r
424 \r
425Returns:\r
426\r
427 EFI_SUCCESS Success\r
428 EFI_OUT_OF_RESOURCES Fail for no resources\r
429 EFI_UNSUPPORTED Unsupported currently\r
430 \r
431--*/\r
432;\r
433\r
434EFI_STATUS\r
435FreeMemoryHeader (\r
436 IN USB2_HC_DEV *HcDev,\r
437 IN MEMORY_MANAGE_HEADER *MemoryHeader\r
438 )\r
439/*++\r
440\r
441Routine Description:\r
442\r
443 Free Memory Header\r
444\r
445Arguments:\r
446\r
447 HcDev - USB2_HC_DEV\r
448 MemoryHeader - MemoryHeader to be freed\r
449\r
450Returns:\r
451\r
452 EFI_SUCCESS Success\r
453 EFI_INVALID_PARAMETER Parameter is error\r
454\r
455--*/\r
456;\r
457\r
458VOID\r
459InsertMemoryHeaderToList (\r
460 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
461 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
462 )\r
463/*++\r
464\r
465Routine Description:\r
466\r
467 Insert Memory Header To List\r
468\r
469Arguments:\r
470\r
471 MemoryHeader - MEMORY_MANAGE_HEADER\r
472 NewMemoryHeader - MEMORY_MANAGE_HEADER\r
473\r
474Returns:\r
475\r
476 VOID\r
477\r
478--*/\r
479;\r
480\r
481EFI_STATUS\r
482AllocMemInMemoryBlock (\r
483 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
484 OUT VOID **Pool,\r
485 IN UINTN NumberOfMemoryUnit\r
486 )\r
487/*++\r
488\r
489Routine Description:\r
490\r
491 Alloc Memory In MemoryBlock\r
492\r
493Arguments:\r
494\r
495 MemoryHeader - MEMORY_MANAGE_HEADER\r
496 Pool - Place to store pointer to memory\r
497 NumberOfMemoryUnit - Number Of Memory Unit\r
498\r
499Returns:\r
500\r
501 EFI_SUCCESS Success\r
502 EFI_NOT_FOUND Can't find the free memory \r
503\r
504--*/\r
505;\r
506\r
507BOOLEAN\r
508IsMemoryBlockEmptied (\r
509 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
510 )\r
511/*++\r
512\r
513Routine Description:\r
514\r
515 Is Memory Block Emptied\r
516\r
517Arguments:\r
518\r
519 MemoryHeaderPtr - MEMORY_MANAGE_HEADER\r
520\r
521Returns:\r
522\r
523 TRUE Empty\r
524 FALSE Not Empty \r
525\r
526--*/\r
527;\r
528\r
529VOID\r
530DelinkMemoryBlock (\r
531 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
532 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader\r
533 )\r
534/*++\r
535\r
536Routine Description:\r
537\r
538 Delink Memory Block\r
539\r
540Arguments:\r
541\r
542 FirstMemoryHeader - MEMORY_MANAGE_HEADER\r
543 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER\r
544\r
545Returns:\r
546\r
547 VOID\r
548\r
549--*/\r
550;\r
551\r
552EFI_STATUS\r
553InitialMemoryManagement (\r
554 IN USB2_HC_DEV *HcDev\r
555 )\r
556/*++\r
557\r
558Routine Description:\r
559\r
560 Initialize Memory Management\r
561\r
562Arguments:\r
563\r
564 HcDev - USB2_HC_DEV\r
565\r
566Returns:\r
567\r
568 EFI_SUCCESS Success\r
569 EFI_DEVICE_ERROR Fail\r
570\r
571--*/\r
572;\r
573\r
574EFI_STATUS\r
575DeinitialMemoryManagement (\r
576 IN USB2_HC_DEV *HcDev\r
577 )\r
578/*++\r
579\r
580Routine Description:\r
581\r
582 Deinitialize Memory Management\r
583\r
584Arguments:\r
585\r
586 HcDev - USB2_HC_DEV\r
587\r
588Returns:\r
589\r
590 EFI_SUCCESS Success\r
591 EFI_DEVICE_ERROR Fail\r
592 \r
593--*/\r
594;\r
595\r
596EFI_STATUS\r
597EhciAllocatePool (\r
598 IN USB2_HC_DEV *HcDev,\r
599 OUT UINT8 **Pool,\r
600 IN UINTN AllocSize\r
601 )\r
602/*++\r
603\r
604Routine Description:\r
605\r
606 Ehci Allocate Pool\r
607\r
608Arguments:\r
609\r
610 HcDev - USB2_HC_DEV\r
611 Pool - Place to store pointer to the memory buffer\r
612 AllocSize - Alloc Size\r
613\r
614Returns:\r
615\r
616 EFI_SUCCESS Success\r
617 EFI_DEVICE_ERROR Fail\r
618 \r
619--*/\r
620;\r
621\r
622VOID\r
623EhciFreePool (\r
624 IN USB2_HC_DEV *HcDev,\r
625 IN UINT8 *Pool,\r
626 IN UINTN AllocSize\r
627 )\r
628/*++\r
629\r
630Routine Description:\r
631\r
632 Uhci Free Pool\r
633\r
634Arguments:\r
635\r
636 HcDev - USB_HC_DEV\r
637 Pool - Pool to free\r
638 AllocSize - Pool size\r
639\r
640Returns:\r
641\r
642 VOID\r
643\r
644--*/\r
645;\r
646\r
647//\r
648// EhciReg Functions\r
649//\r
650EFI_STATUS\r
651ReadEhcCapabiltiyReg (\r
652 IN USB2_HC_DEV *HcDev,\r
653 IN UINT32 CapabiltiyRegAddr,\r
654 IN OUT UINT32 *Data\r
655 )\r
656/*++\r
657\r
658Routine Description:\r
659\r
660 Read Ehc Capabitlity register\r
661 \r
662Arguments:\r
663\r
664 HcDev - USB2_HC_DEV \r
665 CapabiltiyRegAddr - Ehc Capability register address\r
666 Data - A pointer to data read from register\r
667 \r
668Returns:\r
669\r
670 EFI_SUCCESS Success\r
671 EFI_DEVICE_ERROR Fail\r
672 \r
673--*/\r
674;\r
675\r
676EFI_STATUS\r
677ReadEhcOperationalReg (\r
678 IN USB2_HC_DEV *HcDev,\r
679 IN UINT32 OperationalRegAddr,\r
680 IN OUT UINT32 *Data\r
681 )\r
682/*++\r
683\r
684Routine Description:\r
685\r
686 Read Ehc Operation register\r
687 \r
688Arguments:\r
689\r
690 HcDev - USB2_HC_DEV \r
691 OperationalRegAddr - Ehc Operation register address\r
692 Data - A pointer to data read from register\r
693 \r
694Returns:\r
695\r
696 EFI_SUCCESS Success\r
697 EFI_DEVICE_ERROR Fail\r
698 \r
699--*/\r
700;\r
701\r
702EFI_STATUS\r
703WriteEhcOperationalReg (\r
704 IN USB2_HC_DEV *HcDev,\r
705 IN UINT32 OperationalRegAddr,\r
706 IN UINT32 Data\r
707 )\r
708/*++\r
709\r
710Routine Description:\r
711\r
712 Write Ehc Operation register\r
713 \r
714Arguments:\r
715\r
716 HcDev - USB2_HC_DEV \r
717 OperationalRegAddr - Ehc Operation register address\r
718 Data - 32bit write to register\r
719 \r
720Returns:\r
721\r
722 EFI_SUCCESS Success\r
723 EFI_DEVICE_ERROR Fail\r
724 \r
725--*/\r
726;\r
727\r
728EFI_STATUS\r
729SetEhcDoorbell (\r
730 IN USB2_HC_DEV *HcDev\r
731 )\r
732/*++\r
733\r
734Routine Description:\r
735\r
736 Set Ehc door bell bit\r
737 \r
738Arguments:\r
739\r
740 HcDev - USB2_HC_DEV \r
741 \r
742Returns:\r
743\r
744 EFI_SUCCESS Success\r
745 EFI_DEVICE_ERROR Fail\r
746 \r
747--*/\r
748;\r
749\r
750EFI_STATUS\r
751SetFrameListLen (\r
752 IN USB2_HC_DEV *HcDev,\r
753 IN UINTN Length\r
754 )\r
755/*++\r
756\r
757Routine Description:\r
758\r
759 Set the length of Frame List\r
760 \r
761Arguments:\r
762\r
763 HcDev - USB2_HC_DEV \r
764 Length - the required length of frame list\r
765 \r
766Returns:\r
767\r
768 EFI_SUCCESS Success\r
769 EFI_INVALID_PARAMETER Invalid parameter\r
770 EFI_DEVICE_ERROR Fail\r
771 \r
772--*/\r
773;\r
774\r
775BOOLEAN\r
776IsFrameListProgrammable (\r
777 IN USB2_HC_DEV *HcDev\r
778 )\r
779/*++\r
780\r
781Routine Description:\r
782\r
783 Whether frame list is programmable\r
784 \r
785Arguments:\r
786\r
787 HcDev - USB2_HC_DEV \r
788 \r
789Returns:\r
790\r
791 TRUE Programmable\r
792 FALSE Unprogrammable\r
793 \r
794--*/\r
795;\r
796\r
797BOOLEAN\r
798IsPeriodicScheduleEnabled (\r
799 IN USB2_HC_DEV *HcDev\r
800 )\r
801/*++\r
802\r
803Routine Description:\r
804\r
805 Whether periodic schedule is enabled\r
806 \r
807Arguments:\r
808\r
809 HcDev - USB2_HC_DEV \r
810 \r
811Returns:\r
812\r
813 TRUE Enabled\r
814 FALSE Disabled\r
815 \r
816--*/\r
817;\r
818\r
819BOOLEAN\r
820IsAsyncScheduleEnabled (\r
821 IN USB2_HC_DEV *HcDev\r
822 )\r
823/*++\r
824\r
825Routine Description:\r
826\r
827 Whether asynchronous schedule is enabled\r
828 \r
829Arguments:\r
830\r
831 HcDev - USB2_HC_DEV \r
832 \r
833Returns:\r
834\r
835 TRUE Enabled\r
836 FALSE Disabled\r
837 \r
838--*/\r
839;\r
840\r
841BOOLEAN\r
842IsEhcPortEnabled (\r
843 IN USB2_HC_DEV *HcDev,\r
844 IN UINT8 PortNum\r
845 )\r
846/*++\r
847\r
848Routine Description:\r
849\r
850 Whether port is enabled\r
851 \r
852Arguments:\r
853\r
854 HcDev - USB2_HC_DEV \r
855 \r
856Returns:\r
857\r
858 TRUE Enabled\r
859 FALSE Disabled\r
860 \r
861--*/\r
862;\r
863\r
864BOOLEAN\r
865IsEhcReseted (\r
866 IN USB2_HC_DEV *HcDev\r
867 )\r
868/*++\r
869\r
870Routine Description:\r
871\r
872 Whether Ehc is halted\r
873 \r
874Arguments:\r
875\r
876 HcDev - USB2_HC_DEV \r
877 \r
878Returns:\r
879\r
880 TRUE Reseted\r
881 FALSE Unreseted\r
882 \r
883--*/\r
884;\r
885\r
886BOOLEAN\r
887IsEhcHalted (\r
888 IN USB2_HC_DEV *HcDev\r
889 )\r
890/*++\r
891\r
892Routine Description:\r
893\r
894 Whether Ehc is halted\r
895 \r
896Arguments:\r
897\r
898 HcDev - USB2_HC_DEV \r
899 \r
900Returns:\r
901\r
902 TRUE Halted\r
903 FALSE Not halted\r
904 \r
905--*/\r
906;\r
907\r
908BOOLEAN\r
909IsEhcSysError (\r
910 IN USB2_HC_DEV *HcDev\r
911 )\r
912/*++\r
913\r
914Routine Description:\r
915\r
916 Whether Ehc is system error\r
917 \r
918Arguments:\r
919\r
920 HcDev - USB2_HC_DEV \r
921 \r
922Returns:\r
923\r
924 TRUE System error\r
925 FALSE No system error\r
926 \r
927--*/\r
928;\r
929\r
930BOOLEAN\r
931IsHighSpeedDevice (\r
932 IN EFI_USB2_HC_PROTOCOL *This,\r
933 IN UINT8 PortNum \r
934 )\r
935/*++\r
936\r
937Routine Description:\r
938\r
939 Whether high speed device attached\r
940 \r
941Arguments:\r
942\r
943 HcDev - USB2_HC_DEV \r
944 \r
945Returns:\r
946\r
947 TRUE High speed\r
948 FALSE Full speed\r
949 \r
950--*/\r
951;\r
952\r
953EFI_STATUS\r
954WaitForEhcReset (\r
955 IN USB2_HC_DEV *HcDev,\r
956 IN UINTN Timeout\r
957 )\r
958/*++\r
959\r
960Routine Description:\r
961\r
962 wait for Ehc reset or timeout\r
963 \r
964Arguments:\r
965\r
966 HcDev - USB2_HC_DEV \r
967 Timeout - timeout threshold\r
968 \r
969Returns:\r
970\r
971 EFI_SUCCESS Success\r
972 EFI_TIMEOUT Timeout\r
973 \r
974--*/\r
975;\r
976\r
977EFI_STATUS\r
978WaitForEhcHalt (\r
979 IN USB2_HC_DEV *HcDev,\r
980 IN UINTN Timeout\r
981 )\r
982/*++\r
983\r
984Routine Description:\r
985\r
986 wait for Ehc halt or timeout\r
987 \r
988Arguments:\r
989\r
990 HcDev - USB2_HC_DEV \r
991 Timeout - timeout threshold\r
992 \r
993Returns:\r
994\r
995 EFI_SUCCESS Success\r
996 EFI_TIMEOUT Timeout\r
997 \r
998--*/\r
999;\r
1000\r
1001EFI_STATUS\r
1002WaitForEhcNotHalt (\r
1003 IN USB2_HC_DEV *HcDev,\r
1004 IN UINTN Timeout\r
1005 )\r
1006/*++\r
1007\r
1008Routine Description:\r
1009\r
1010 wait for Ehc not halt or timeout\r
1011 \r
1012Arguments:\r
1013\r
1014 HcDev - USB2_HC_DEV \r
1015 Timeout - timeout threshold\r
1016 \r
1017Returns:\r
1018\r
1019 EFI_SUCCESS Success\r
1020 EFI_TIMEOUT Timeout\r
1021 \r
1022--*/\r
1023;\r
1024\r
1025EFI_STATUS\r
1026WaitForEhcDoorbell (\r
1027 IN USB2_HC_DEV *HcDev,\r
1028 IN UINTN Timeout\r
1029 )\r
1030/*++\r
1031\r
1032Routine Description:\r
1033\r
1034 Wait for periodic schedule disable or timeout\r
1035\r
1036Arguments:\r
1037\r
1038 HcDev - USB2_HC_DEV \r
1039 Timeout - timeout threshold\r
1040\r
1041Returns:\r
1042\r
1043 EFI_SUCCESS Success\r
1044 EFI_TIMEOUT Timeout\r
1045 \r
1046--*/\r
1047;\r
1048\r
1049EFI_STATUS\r
1050WaitForAsyncScheduleEnable (\r
1051 IN USB2_HC_DEV *HcDev,\r
1052 IN UINTN Timeout\r
1053 )\r
1054/*++\r
1055\r
1056Routine Description:\r
1057\r
1058 Wait for Ehc asynchronous schedule enable or timeout\r
1059 \r
1060Arguments:\r
1061\r
1062 HcDev - USB2_HC_DEV \r
1063 Timeout - timeout threshold\r
1064 \r
1065Returns:\r
1066\r
1067 EFI_SUCCESS Success\r
1068 EFI_TIMEOUT Timeout\r
1069 \r
1070--*/\r
1071;\r
1072\r
1073EFI_STATUS\r
1074WaitForAsyncScheduleDisable (\r
1075 IN USB2_HC_DEV *HcDev,\r
1076 IN UINTN Timeout\r
1077 )\r
1078/*++\r
1079\r
1080Routine Description:\r
1081\r
1082 Wait for Ehc asynchronous schedule disable or timeout\r
1083 \r
1084Arguments:\r
1085\r
1086 HcDev - USB2_HC_DEV \r
1087 Timeout - timeout threshold\r
1088 \r
1089Returns:\r
1090\r
1091 EFI_SUCCESS Success\r
1092 EFI_TIMEOUT Timeout\r
1093 \r
1094--*/\r
1095;\r
1096\r
1097EFI_STATUS\r
1098WaitForPeriodicScheduleEnable (\r
1099 IN USB2_HC_DEV *HcDev,\r
1100 IN UINTN Timeout\r
1101 )\r
1102/*++\r
1103\r
1104Routine Description:\r
1105\r
1106 Wait for Ehc periodic schedule enable or timeout\r
1107 \r
1108Arguments:\r
1109\r
1110 HcDev - USB2_HC_DEV \r
1111 Timeout - timeout threshold\r
1112 \r
1113Returns:\r
1114\r
1115 EFI_SUCCESS Success\r
1116 EFI_TIMEOUT Timeout\r
1117 \r
1118--*/\r
1119;\r
1120\r
1121EFI_STATUS\r
1122WaitForPeriodicScheduleDisable (\r
1123 IN USB2_HC_DEV *HcDev,\r
1124 IN UINTN Timeout\r
1125 )\r
1126/*++\r
1127\r
1128Routine Description:\r
1129\r
1130 Wait for periodic schedule disable or timeout\r
1131 \r
1132Arguments:\r
1133\r
1134 HcDev - USB2_HC_DEV \r
1135 Timeout - timeout threshold\r
1136 \r
1137Returns:\r
1138\r
1139 EFI_SUCCESS Success\r
1140 EFI_TIMEOUT Timeout\r
1141 \r
1142--*/\r
1143;\r
1144\r
1145EFI_STATUS\r
1146GetCapabilityLen (\r
1147 IN USB2_HC_DEV *HcDev\r
1148 )\r
1149/*++\r
1150\r
1151Routine Description:\r
1152\r
1153 Get the length of capability register\r
1154 \r
1155Arguments:\r
1156\r
1157 HcDev - USB2_HC_DEV \r
1158 \r
1159Returns:\r
1160\r
1161 EFI_SUCCESS Success\r
1162 EFI_DEVICE_ERROR Fail\r
1163 \r
1164--*/\r
1165;\r
1166\r
1167EFI_STATUS\r
1168SetFrameListBaseAddr (\r
1169 IN USB2_HC_DEV *HcDev,\r
1170 IN UINT32 FrameBuffer\r
1171 )\r
1172/*++\r
1173\r
1174Routine Description:\r
1175\r
1176 Set base address of frame list first entry\r
1177 \r
1178Arguments:\r
1179\r
1180 HcDev - USB2_HC_DEV \r
1181 FrameBuffer - base address of first entry of frame list\r
1182 \r
1183Returns:\r
1184\r
1185 EFI_SUCCESS Success\r
1186 EFI_DEVICE_ERROR Fail\r
1187 \r
1188--*/\r
1189;\r
1190\r
1191EFI_STATUS\r
1192SetAsyncListAddr (\r
1193 IN USB2_HC_DEV *HcDev,\r
1194 IN EHCI_QH_ENTITY *QhPtr\r
1195 )\r
1196/*++\r
1197\r
1198Routine Description:\r
1199\r
1200 Set address of first Async schedule Qh\r
1201 \r
1202Arguments:\r
1203\r
1204 HcDev - USB2_HC_DEV \r
1205 QhPtr - A pointer to first Qh in the Async schedule\r
1206 \r
1207Returns:\r
1208\r
1209 EFI_SUCCESS Success\r
1210 EFI_DEVICE_ERROR Fail\r
1211 \r
1212--*/\r
1213;\r
1214\r
1215EFI_STATUS\r
1216SetCtrlDataStructSeg (\r
1217 IN USB2_HC_DEV *HcDev\r
1218 )\r
1219/*++\r
1220\r
1221Routine Description:\r
1222\r
1223 Set address of first Async schedule Qh\r
1224 \r
1225Arguments:\r
1226\r
1227 HcDev - USB2_HC_DEV \r
1228 QhPtr - A pointer to first Qh in the Async schedule\r
1229 \r
1230Returns:\r
1231\r
1232 EFI_SUCCESS Success\r
1233 EFI_DEVICE_ERROR Fail\r
1234 \r
1235--*/\r
1236;\r
1237\r
1238EFI_STATUS\r
1239SetPortRoutingEhc (\r
1240 IN USB2_HC_DEV *HcDev\r
1241 )\r
1242/*++\r
1243\r
1244Routine Description:\r
1245\r
1246 Set Ehc port routing bit\r
1247 \r
1248Arguments:\r
1249\r
1250 HcDev - USB2_HC_DEV \r
1251 \r
1252Returns:\r
1253\r
1254 EFI_SUCCESS Success\r
1255 EFI_DEVICE_ERROR Fail\r
1256 \r
1257--*/\r
1258;\r
1259\r
1260EFI_STATUS\r
1261EnablePeriodicSchedule (\r
1262 IN USB2_HC_DEV *HcDev\r
1263 )\r
1264/*++\r
1265\r
1266Routine Description:\r
1267\r
1268 Enable periodic schedule\r
1269 \r
1270Arguments:\r
1271\r
1272 HcDev - USB2_HC_DEV \r
1273 \r
1274Returns:\r
1275\r
1276 EFI_SUCCESS Success\r
1277 EFI_DEVICE_ERROR Fail\r
1278 \r
1279--*/\r
1280;\r
1281\r
1282EFI_STATUS\r
1283DisablePeriodicSchedule (\r
1284 IN USB2_HC_DEV *HcDev\r
1285 )\r
1286/*++\r
1287\r
1288Routine Description:\r
1289\r
1290 Disable periodic schedule\r
1291 \r
1292Arguments:\r
1293\r
1294 HcDev - USB2_HC_DEV \r
1295 \r
1296Returns:\r
1297\r
1298 EFI_SUCCESS Success\r
1299 EFI_DEVICE_ERROR Fail\r
1300 \r
1301--*/\r
1302;\r
1303\r
1304EFI_STATUS\r
1305EnableAsynchronousSchedule (\r
1306 IN USB2_HC_DEV *HcDev\r
1307 )\r
1308/*++\r
1309\r
1310Routine Description:\r
1311\r
1312 Enable asynchrounous schedule\r
1313 \r
1314Arguments:\r
1315\r
1316 HcDev - USB2_HC_DEV \r
1317 \r
1318Returns:\r\r
1319\r
1320 EFI_SUCCESS Success\r
1321 EFI_DEVICE_ERROR Fail\r
1322 \r
1323--*/\r
1324;\r
1325\r
1326EFI_STATUS\r
1327DisableAsynchronousSchedule (\r
1328 IN USB2_HC_DEV *HcDev\r
1329 )\r
1330/*++\r
1331\r
1332Routine Description:\r
1333\r
1334 Disable asynchrounous schedule\r
1335 \r
1336Arguments:\r
1337\r
1338 HcDev - USB2_HC_DEV \r
1339 \r
1340Returns:\r
1341\r
1342 EFI_SUCCESS Success\r
1343 EFI_DEVICE_ERROR Fail\r
1344 \r
1345--*/\r
1346;\r
1347\r
1348EFI_STATUS\r
1349StartScheduleExecution (\r
1350 IN USB2_HC_DEV *HcDev\r
1351 )\r
1352/*++\r
1353\r
1354Routine Description:\r
1355\r
1356 Start Ehc schedule execution\r
1357 \r
1358Arguments:\r
1359\r
1360 HcDev - USB2_HC_DEV \r
1361 \r
1362Returns:\r
1363\r
1364 EFI_SUCCESS Success\r
1365 EFI_DEVICE_ERROR Fail\r
1366 \r
1367--*/\r
1368;\r
1369\r
1370EFI_STATUS\r
1371ResetEhc (\r
1372 IN USB2_HC_DEV *HcDev\r
1373 )\r
1374/*++\r
1375\r
1376Routine Description:\r
1377\r
1378 Reset Ehc\r
1379 \r
1380Arguments:\r
1381\r
1382 HcDev - USB2_HC_DEV \r
1383 \r
1384Returns:\r
1385\r
1386 EFI_SUCCESS Success\r
1387 EFI_DEVICE_ERROR Fail\r
1388 \r
1389--*/\r
1390;\r
1391\r
1392EFI_STATUS\r
1393ClearEhcAllStatus (\r
1394 IN USB2_HC_DEV *HcDev\r
1395 )\r
1396/*++\r
1397\r
1398Routine Description:\r
1399\r
1400 Clear Ehc all status bits\r
1401 \r
1402Arguments:\r
1403\r
1404 HcDev - USB2_HC_DEV \r
1405 \r
1406Returns:\r
1407\r
1408 EFI_SUCCESS Success\r
1409 EFI_DEVICE_ERROR Fail\r
1410 \r
1411--*/\r
1412;\r
1413\r
1414//\r
1415// EhciSched Functions\r
1416//\r
1417EFI_STATUS\r
1418InitialPeriodicFrameList (\r
1419 IN USB2_HC_DEV *HcDev,\r
1420 IN UINTN Length\r
1421 )\r
1422/*++\r
1423\r
1424Routine Description:\r
1425\r
1426 Initialize Periodic Schedule Frame List\r
1427\r
1428Arguments:\r
1429\r
1430 HcDev - USB2_HC_DEV\r
1431 Length - Frame List Length\r
1432 \r
1433Returns:\r
1434\r
1435 EFI_SUCCESS Success\r
1436 EFI_DEVICE_ERROR Fail\r
1437 \r
1438--*/\r
1439;\r
1440\r
1441VOID\r
1442DeinitialPeriodicFrameList (\r
1443 IN USB2_HC_DEV *HcDev\r
1444 )\r
1445/*++\r
1446\r
1447Routine Description:\r
1448\r
1449 Deinitialize Periodic Schedule Frame List\r
1450\r
1451Arguments:\r
1452\r
1453 HcDev - USB2_HC_DEV\r
1454\r
1455Returns:\r
1456\r
1457 VOID\r
1458 \r
1459--*/\r
1460;\r
1461\r
1462EFI_STATUS\r
1463CreatePollingTimer (\r
1464 IN USB2_HC_DEV *HcDev,\r
1465 IN EFI_EVENT_NOTIFY NotifyFunction\r
1466 )\r
1467/*++\r
1468\r
1469Routine Description:\r
1470\r
1471 Create Async Request Polling Timer\r
1472\r
1473Arguments:\r
1474\r
1475 HcDev - USB2_HC_DEV\r
1476 NotifyFunction - Timer Notify Function\r
1477 \r
1478Returns:\r
1479\r
1480 EFI_SUCCESS Success\r
1481 EFI_DEVICE_ERROR Fail\r
1482 \r
1483--*/\r
1484;\r
1485\r
1486EFI_STATUS\r
1487DestoryPollingTimer (\r
1488 IN USB2_HC_DEV *HcDev\r
1489 )\r
1490/*++\r
1491\r
1492Routine Description:\r
1493\r
1494 Destory Async Request Polling Timer\r
1495\r
1496Arguments:\r
1497\r
1498 HcDev - USB2_HC_DEV\r
1499 \r
1500Returns:\r
1501\r
1502 EFI_SUCCESS Success\r
1503 EFI_DEVICE_ERROR Fail\r
1504 \r
1505--*/\r
1506;\r
1507\r
1508EFI_STATUS\r
1509StartPollingTimer (\r
1510 IN USB2_HC_DEV *HcDev\r
1511 )\r
1512/*++\r
1513\r
1514Routine Description:\r
1515\r
1516 Start Async Request Polling Timer\r
1517\r
1518Arguments:\r
1519\r
1520 HcDev - USB2_HC_DEV\r
1521 \r
1522Returns:\r
1523\r
1524 EFI_SUCCESS Success\r
1525 EFI_DEVICE_ERROR Fail\r
1526 \r
1527--*/\r
1528;\r
1529\r
1530EFI_STATUS\r
1531StopPollingTimer (\r
1532 IN USB2_HC_DEV *HcDev\r
1533 )\r
1534/*++\r
1535\r
1536Routine Description:\r
1537\r
1538 Stop Async Request Polling Timer\r
1539\r
1540Arguments:\r
1541\r
1542 HcDev - USB2_HC_DEV\r
1543 \r
1544Returns:\r
1545\r
1546 EFI_SUCCESS Success\r
1547 EFI_DEVICE_ERROR Fail\r
1548 \r
1549--*/\r
1550;\r
1551\r
1552EFI_STATUS\r
1553CreateQh (\r
1554 IN USB2_HC_DEV *HcDev,\r
1555 IN UINT8 DeviceAddr,\r
1556 IN UINT8 Endpoint,\r
1557 IN UINT8 DeviceSpeed,\r
1558 IN UINTN MaxPacketLen,\r
1559 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1560 )\r
1561/*++\r
1562\r
1563Routine Description:\r
1564\r
1565 Create Qh Structure and Pre-Initialize\r
1566\r
1567Arguments:\r
1568\r
1569 HcDev - USB2_HC_DEV \r
1570 DeviceAddr - Address of Device\r
1571 Endpoint - Endpoint Number\r
1572 DeviceSpeed - Device Speed\r
1573 MaxPacketLen - Max Length of one Packet\r
1574 QhPtrPtr - A pointer of pointer to Qh for return\r
1575 \r
1576Returns:\r
1577\r
1578 EFI_SUCCESS Success\r
1579 EFI_DEVICE_ERROR Fail\r
1580 \r
1581--*/\r
1582;\r
1583\r
1584EFI_STATUS\r
1585CreateControlQh (\r
1586 IN USB2_HC_DEV *HcDev,\r
1587 IN UINT8 DeviceAddr,\r
1588 IN UINT8 DeviceSpeed,\r
1589 IN UINTN MaxPacketLen,\r
1590 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1591 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1592 )\r
1593/*++\r
1594\r
1595Routine Description:\r
1596\r
1597 Create Qh for Control Transfer\r
1598\r
1599Arguments:\r
1600\r
1601 HcDev - USB2_HC_DEV \r
1602 DeviceAddr - Address of Device\r
1603 DeviceSpeed - Device Speed\r
1604 MaxPacketLen - Max Length of one Packet\r
1605 Translator - Translator Transaction for SplitX\r
1606 QhPtrPtr - A pointer of pointer to Qh for return\r
1607 \r
1608Returns:\r
1609\r
1610 EFI_SUCCESS Success\r
1611 EFI_DEVICE_ERROR Fail\r
1612 \r
1613--*/\r
1614;\r
1615\r
1616EFI_STATUS\r
1617CreateBulkQh (\r
1618 IN USB2_HC_DEV *HcDev,\r
1619 IN UINT8 DeviceAddr,\r
1620 IN UINT8 EndPointAddr,\r
1621 IN UINT8 DeviceSpeed,\r
1622 IN UINT8 DataToggle,\r
1623 IN UINTN MaxPacketLen,\r
1624 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1625 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1626 )\r
1627/*++\r
1628\r
1629Routine Description:\r
1630\r
1631 Create Qh for Bulk Transfer\r
1632\r
1633Arguments:\r
1634\r
1635 HcDev - USB2_HC_DEV \r
1636 DeviceAddr - Address of Device\r
1637 EndPointAddr - Address of Endpoint\r
1638 DeviceSpeed - Device Speed\r
1639 MaxPacketLen - Max Length of one Packet\r
1640 Translator - Translator Transaction for SplitX\r
1641 QhPtrPtr - A pointer of pointer to Qh for return\r
1642 \r
1643Returns:\r
1644\r
1645 EFI_SUCCESS Success\r
1646 EFI_DEVICE_ERROR Fail\r
1647 \r
1648--*/\r
1649;\r
1650\r
1651EFI_STATUS\r
1652CreateInterruptQh (\r
1653 IN USB2_HC_DEV *HcDev,\r
1654 IN UINT8 DeviceAddr,\r
1655 IN UINT8 EndPointAddr,\r
1656 IN UINT8 DeviceSpeed,\r
1657 IN UINT8 DataToggle,\r
1658 IN UINTN MaxPacketLen,\r
1659 IN UINTN Interval,\r
1660 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1661 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1662 )\r
1663/*++\r
1664\r
1665Routine Description:\r
1666\r
1667 Create Qh for Control Transfer\r
1668\r
1669Arguments:\r
1670\r
1671 HcDev - USB2_HC_DEV \r
1672 DeviceAddr - Address of Device\r
1673 EndPointAddr - Address of Endpoint\r
1674 DeviceSpeed - Device Speed\r
1675 MaxPacketLen - Max Length of one Packet\r
1676 Interval - value of interval\r
1677 Translator - Translator Transaction for SplitX\r
1678 QhPtrPtr - A pointer of pointer to Qh for return\r
1679 \r
1680Returns:\r
1681\r
1682 EFI_SUCCESS Success\r
1683 EFI_DEVICE_ERROR Fail\r
1684 \r
1685--*/\r
1686;\r
1687\r
1688VOID\r
1689DestoryQh (\r
1690 IN USB2_HC_DEV *HcDev,\r
1691 IN EHCI_QH_ENTITY *QhPtr\r
1692 )\r
1693/*++\r
1694\r
1695Routine Description:\r
1696\r
1697 Destory Qh Structure \r
1698 \r
1699Arguments:\r
1700\r
1701 HcDev - USB2_HC_DEV \r
1702 QhPtr - A pointer to Qh\r
1703 \r
1704Returns:\r
1705\r
1706 VOID\r
1707 \r
1708--*/\r
1709;\r
1710\r
1711EFI_STATUS\r
1712CreateQtd (\r
1713 IN USB2_HC_DEV *HcDev,\r
1714 IN UINT8 *DataPtr,\r
1715 IN UINTN DataLen,\r
1716 IN UINT8 PktId,\r
1717 IN UINT8 Toggle,\r
1718 IN UINT8 QtdStatus,\r
1719 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1720 )\r
1721/*++\r
1722\r
1723Routine Description:\r
1724\r
1725 Create Qtd Structure and Pre-Initialize it\r
1726\r
1727Arguments:\r
1728\r
1729 HcDev - USB2_HC_DEV \r
1730 DataPtr - A pointer to user data buffer to transfer\r
1731 DataLen - Length of user data to transfer\r
1732 PktId - Packet Identification of this Qtd\r
1733 Toggle - Data Toggle of this Qtd\r
1734 QtdStatus - Default value of status of this Qtd\r
1735 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1736 \r
1737Returns:\r
1738\r
1739 EFI_SUCCESS Success\r
1740 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1741 \r
1742--*/\r
1743;\r
1744\r
1745EFI_STATUS\r
1746CreateSetupQtd (\r
1747 IN USB2_HC_DEV *HcDev,\r
1748 IN UINT8 *DevReqPtr,\r
1749 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1750 )\r
1751/*++\r
1752\r
1753Routine Description:\r
1754\r
1755 Create Qtd Structure for Setup \r
1756\r
1757Arguments:\r
1758\r
1759 HcDev - USB2_HC_DEV \r
1760 DevReqPtr - A pointer to Device Request Data\r
1761 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1762 \r
1763Returns:\r
1764\r
1765 EFI_SUCCESS Success\r
1766 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1767 \r
1768--*/\r
1769;\r
1770\r
1771EFI_STATUS\r
1772CreateDataQtd (\r
1773 IN USB2_HC_DEV *HcDev,\r
1774 IN UINT8 *DataPtr,\r
1775 IN UINTN DataLen,\r
1776 IN UINT8 PktId,\r
1777 IN UINT8 Toggle,\r
1778 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1779 )\r
1780/*++\r
1781\r
1782Routine Description:\r
1783\r
1784 Create Qtd Structure for data \r
1785\r
1786Arguments:\r
1787\r
1788 HcDev - USB2_HC_DEV \r
1789 DataPtr - A pointer to user data buffer to transfer\r
1790 DataLen - Length of user data to transfer\r
1791 PktId - Packet Identification of this Qtd\r
1792 Toggle - Data Toggle of this Qtd\r
1793 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1794 \r
1795Returns:\r
1796\r
1797 EFI_SUCCESS Success\r
1798 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1799 \r
1800--*/\r
1801;\r
1802\r
1803EFI_STATUS\r
1804CreateStatusQtd (\r
1805 IN USB2_HC_DEV *HcDev,\r
1806 IN UINT8 PktId,\r
1807 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1808 )\r
1809/*++\r
1810\r
1811Routine Description:\r
1812\r
1813 Create Qtd Structure for status \r
1814\r
1815Arguments:\r
1816\r
1817 HcDev - USB2_HC_DEV \r
1818 PktId - Packet Identification of this Qtd\r
1819 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1820 \r
1821Returns:\r
1822\r
1823 EFI_SUCCESS Success\r
1824 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1825 \r
1826--*/\r
1827;\r
1828\r
1829EFI_STATUS\r
1830CreateAltQtd (\r
1831 IN USB2_HC_DEV *HcDev,\r
1832 IN UINT8 PktId,\r
1833 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1834 )\r
1835/*++\r
1836\r
1837Routine Description:\r
1838\r
1839 Create Qtd Structure for Alternative \r
1840\r
1841Arguments:\r
1842\r
1843 HcDev - USB2_HC_DEV \r
1844 PktId - Packet Identification of this Qtd\r
1845 QtdPtrPtr - A pointer of pointer to Qtd for return\r
1846 \r
1847Returns:\r
1848\r
1849 EFI_SUCCESS Success\r
1850 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
1851 \r
1852--*/\r
1853;\r
1854\r
1855EFI_STATUS\r
1856CreateControlQtds (\r
1857 IN USB2_HC_DEV *HcDev,\r
1858 IN UINT8 DataPktId,\r
1859 IN UINT8 *RequestCursor,\r
1860 IN UINT8 *DataCursor,\r
1861 IN UINTN DataLen,\r
1862 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1863 OUT EHCI_QTD_ENTITY **ControlQtdsHead\r
1864 )\r
1865/*++\r
1866\r
1867Routine Description:\r
1868\r
1869 Create Qtds list for Control Transfer \r
1870\r
1871Arguments:\r
1872\r
1873 HcDev - USB2_HC_DEV \r
1874 DataPktId - Packet Identification of Data Qtds\r
1875 RequestCursor - A pointer to request structure buffer to transfer\r
1876 DataCursor - A pointer to user data buffer to transfer\r
1877 DataLen - Length of user data to transfer\r
1878 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1879 \r
1880Returns:\r
1881\r
1882 EFI_SUCCESS Success\r
1883 EFI_DEVICE_ERROR Fail\r
1884 \r
1885--*/\r
1886;\r
1887\r
1888EFI_STATUS\r
1889CreateBulkOrInterruptQtds (\r
1890 IN USB2_HC_DEV *HcDev,\r
1891 IN UINT8 PktId,\r
1892 IN UINT8 *DataCursor,\r
1893 IN UINTN DataLen,\r
1894 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1895 OUT EHCI_QTD_ENTITY **QtdsHead\r
1896 )\r
1897/*++\r
1898\r
1899Routine Description:\r
1900\r
1901 Create Qtds list for Bulk or Interrupt Transfer \r
1902\r
1903Arguments:\r
1904\r
1905 HcDev - USB2_HC_DEV \r
1906 PktId - Packet Identification of Qtds\r
1907 DataCursor - A pointer to user data buffer to transfer\r
1908 DataLen - Length of user data to transfer\r
1909 DataToggle - Data Toggle to start\r
1910 Translator - Translator Transaction for SplitX\r
1911 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
1912 \r
1913Returns:\r
1914\r
1915 EFI_SUCCESS Success\r
1916 EFI_DEVICE_ERROR Fail\r
1917 \r
1918--*/\r
1919;\r
1920\r
1921VOID\r
1922DestoryQtds (\r
1923 IN USB2_HC_DEV *HcDev,\r
1924 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
1925 )\r
1926/*++\r
1927\r
1928Routine Description:\r
1929\r
1930 Destory all Qtds in the list\r
1931\r
1932Arguments:\r
1933\r
1934 HcDev - USB2_HC_DEV \r
1935 FirstQtdPtr - A pointer to first Qtd in the list \r
1936 \r
1937Returns:\r
1938\r
1939 VOID\r
1940\r
1941--*/\r
1942;\r
1943\r
1944VOID\r
1945LinkQtdToQtd (\r
1946 IN EHCI_QTD_ENTITY *PreQtdPtr,\r
1947 IN EHCI_QTD_ENTITY *QtdPtr\r
1948 )\r
1949/*++\r
1950\r
1951Routine Description:\r
1952\r
1953 Link Qtds together\r
1954 \r
1955Arguments:\r
1956\r
1957 PreQtdPtr - A pointer to pre Qtd\r
1958 QtdPtr - A pointer to next Qtd\r
1959 \r
1960Returns:\r
1961\r
1962 VOID\r
1963\r
1964--*/\r
1965;\r
1966\r
1967VOID\r
1968LinkQtdsToAltQtd (\r
1969 IN EHCI_QTD_ENTITY *FirstQtdPtr,\r
1970 IN EHCI_QTD_ENTITY *AltQtdPtr\r
1971 )\r
1972/*++\r
1973\r
1974Routine Description:\r
1975\r
1976 Link AlterQtds together\r
1977 \r
1978Arguments:\r
1979\r
1980 FirstQtdPtr - A pointer to first Qtd in the list\r
1981 AltQtdPtr - A pointer to alternative Qtd\r
1982 \r
1983Returns:\r
1984 VOID\r
1985\r
1986--*/\r
1987;\r
1988\r
1989VOID\r
1990LinkQtdToQh (\r
1991 IN EHCI_QH_ENTITY *QhPtr,\r
1992 IN EHCI_QTD_ENTITY *QtdEntryPtr\r
1993 )\r
1994/*++\r
1995\r
1996Routine Description:\r
1997\r
1998 Link Qtds list to Qh\r
1999 \r
2000Arguments:\r
2001\r
2002 QhPtr - A pointer to Qh\r
2003 QtdPtr - A pointer to first Qtd in the list\r
2004 \r
2005Returns:\r
2006\r
2007 VOID\r
2008\r
2009--*/\r
2010;\r
2011\r
2012EFI_STATUS\r
2013LinkQhToAsyncList (\r
2014 IN USB2_HC_DEV *HcDev,\r
2015 IN EHCI_QH_ENTITY *QhPtr\r
2016 )\r
2017/*++\r
2018\r
2019Routine Description:\r
2020\r
2021 Link Qh to Async Schedule List\r
2022 \r
2023Arguments:\r
2024\r
2025 HcDev - USB2_HC_DEV \r
2026 QhPtr - A pointer to Qh\r
2027 \r
2028Returns:\r
2029\r
2030 EFI_SUCCESS Success\r
2031 EFI_DEVICE_ERROR Fail\r
2032 \r
2033--*/\r
2034;\r
2035\r
2036EFI_STATUS\r
2037UnlinkQhFromAsyncList (\r
2038 IN USB2_HC_DEV *HcDev,\r
2039 IN EHCI_QH_ENTITY *QhPtr\r
2040 )\r
2041/*++\r
2042\r
2043Routine Description:\r
2044\r
2045 Unlink Qh from Async Schedule List\r
2046 \r
2047Arguments:\r
2048\r
2049 HcDev - USB2_HC_DEV \r
2050 QhPtr - A pointer to Qh\r
2051 \r
2052Returns:\r
2053\r
2054 EFI_SUCCESS Success\r
2055 EFI_DEVICE_ERROR Fail\r
2056 \r
2057--*/\r
2058;\r
2059\r
2060VOID\r
2061LinkQhToPeriodicList (\r
2062 IN USB2_HC_DEV *HcDev,\r
2063 IN EHCI_QH_ENTITY *QhPtr\r
2064 )\r
2065/*++\r
2066\r
2067Routine Description:\r
2068\r
2069 Link Qh to Periodic Schedule List\r
2070 \r
2071Arguments:\r
2072\r
2073 HcDev - USB2_HC_DEV \r
2074 QhPtr - A pointer to Qh\r
2075 \r
2076Returns:\r
2077\r
2078 VOID\r
2079\r
2080--*/\r
2081;\r
2082\r
2083VOID\r
2084UnlinkQhFromPeriodicList (\r
2085 IN USB2_HC_DEV *HcDev,\r
2086 IN EHCI_QH_ENTITY *QhPtr,\r
2087 IN UINTN Interval\r
2088 )\r
2089/*++\r
2090\r
2091Routine Description:\r
2092\r
2093 Unlink Qh from Periodic Schedule List\r
2094 \r
2095Arguments:\r
2096\r
2097 HcDev - USB2_HC_DEV \r
2098 QhPtr - A pointer to Qh\r
2099 Interval - Interval of this periodic transfer\r
2100 \r
2101Returns:\r
2102\r
2103 VOID\r
2104 \r
2105--*/\r
2106;\r
2107\r
2108VOID\r
2109LinkToAsyncReqeust (\r
2110 IN USB2_HC_DEV *HcDev,\r
2111 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2112 )\r
2113/*++\r
2114\r
2115Routine Description:\r
2116\r
2117 Llink AsyncRequest Entry to Async Request List\r
2118 \r
2119Arguments:\r
2120\r
2121 HcDev - USB2_HC_DEV \r
2122 AsyncRequestPtr - A pointer to Async Request Entry\r
2123 \r
2124Returns:\r
2125\r
2126 VOID\r
2127 \r
2128--*/\r
2129;\r
2130\r
2131VOID\r
2132UnlinkFromAsyncReqeust (\r
2133 IN USB2_HC_DEV *HcDev,\r
2134 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2135 )\r
2136/*++\r
2137\r
2138Routine Description:\r
2139\r
2140 Unlink AsyncRequest Entry from Async Request List\r
2141 \r
2142Arguments:\r
2143\r
2144 HcDev - USB2_HC_DEV \r
2145 AsyncRequestPtr - A pointer to Async Request Entry\r
2146 \r
2147Returns:\r
2148\r
2149 VOID\r
2150 \r
2151--*/\r
2152;\r
2153\r
2154UINTN\r
2155GetNumberOfQtd (\r
2156 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2157 )\r
2158/*++\r
2159\r
2160Routine Description:\r
2161\r
2162 Number of Qtds in the list\r
2163 \r
2164Arguments:\r
2165\r
2166 FirstQtdPtr - A pointer to first Qtd in the list\r
2167 \r
2168Returns:\r
2169\r
2170 Number of Qtds in the list\r
2171\r
2172--*/\r
2173;\r
2174\r
2175UINTN\r
2176GetNumberOfTransaction (\r
2177 IN UINTN SizeOfData,\r
2178 IN UINTN SizeOfTransaction\r
2179 )\r
2180/*++\r
2181\r
2182Routine Description:\r
2183\r
2184 Number of Transactions in one Qtd\r
2185 \r
2186Arguments:\r
2187\r
2188 SizeOfData - Size of one Qtd\r
2189 SizeOfTransaction - Size of one Transaction\r
2190 \r
2191Returns:\r
2192\r
2193 Number of Transactions in this Qtd\r
2194\r
2195--*/\r
2196;\r
2197\r
2198UINTN\r
2199GetCapacityOfQtd (\r
2200 IN UINT8 *BufferCursor\r
2201 )\r
2202/*++\r
2203\r
2204Routine Description:\r
2205\r
2206 Get Capacity of Qtd\r
2207 \r
2208Arguments:\r
2209\r
2210 BufferCursor - BufferCursor of the Qtd\r
2211 \r
2212Returns:\r
2213\r
2214 Capacity of Qtd\r
2215\r
2216--*/\r
2217;\r
2218\r
2219UINTN\r
2220GetApproxiOfInterval (\r
2221 IN UINTN Interval\r
2222 )\r
2223/*++\r
2224\r
2225Routine Description:\r
2226\r
2227 Get the approximate value in the 2 index sequence\r
2228 \r
2229Arguments:\r
2230\r
2231 Interval - the value of interval\r
2232 \r
2233Returns:\r
2234\r
2235 approximate value of interval in the 2 index sequence\r
2236 \r
2237--*/\r
2238;\r
2239\r
2240EHCI_QTD_HW *\r
2241GetQtdNextPointer (\r
2242 IN EHCI_QTD_HW *HwQtdPtr\r
2243 )\r
2244/*++\r
2245\r
2246Routine Description:\r
2247\r
2248 Get Qtd next pointer field\r
2249 \r
2250Arguments:\r
2251\r
2252 HwQtdPtr - A pointer to hardware Qtd structure\r
2253 \r
2254Returns:\r
2255\r
2256 A pointer to next hardware Qtd structure\r
2257 \r
2258--*/\r
2259;\r
2260\r
2261BOOLEAN\r
2262IsQtdStatusActive (\r
2263 IN EHCI_QTD_HW *HwQtdPtr\r
2264 )\r
2265/*++\r
2266\r
2267Routine Description:\r
2268\r
2269 Whether Qtd status is active or not\r
2270 \r
2271Arguments:\r
2272\r
2273 HwQtdPtr - A pointer to hardware Qtd structure\r
2274 \r
2275Returns:\r
2276\r
2277 TRUE Active\r
2278 FALSE Inactive\r
2279 \r
2280--*/\r
2281;\r
2282\r
2283BOOLEAN\r
2284IsQtdStatusHalted (\r
2285 IN EHCI_QTD_HW *HwQtdPtr\r
2286 )\r
2287/*++\r
2288\r
2289Routine Description:\r
2290\r
2291 Whether Qtd status is halted or not\r
2292 \r
2293Arguments:\r
2294\r
2295 HwQtdPtr - A pointer to hardware Qtd structure\r
2296 \r
2297Returns:\r\r
2298\r
2299 TRUE Halted\r
2300 FALSE Not halted\r
2301 \r
2302--*/\r
2303;\r
2304\r
2305BOOLEAN\r
2306IsQtdStatusBufferError (\r
2307 IN EHCI_QTD_HW *HwQtdPtr\r
2308 )\r
2309/*++\r
2310\r
2311Routine Description:\r
2312\r
2313 Whether Qtd status is buffer error or not\r
2314 \r
2315Arguments:\r
2316\r
2317 HwQtdPtr - A pointer to hardware Qtd structure\r
2318 \r
2319Returns:\r
2320\r
2321 TRUE Buffer error\r
2322 FALSE No buffer error\r
2323 \r
2324--*/\r
2325;\r
2326\r
2327BOOLEAN\r
2328IsQtdStatusBabbleError (\r
2329 IN EHCI_QTD_HW *HwQtdPtr\r
2330 )\r
2331/*++\r
2332\r
2333Routine Description:\r
2334\r
2335 Whether Qtd status is babble error or not\r
2336 \r
2337Arguments:\r
2338\r
2339 HwQtdPtr - A pointer to hardware Qtd structure\r
2340 \r
2341Returns:\r
2342\r
2343 TRUE Babble error\r
2344 FALSE No babble error\r
2345 \r
2346--*/\r
2347;\r
2348\r
2349BOOLEAN\r
2350IsQtdStatusTransactionError (\r
2351 IN EHCI_QTD_HW *HwQtdPtr\r
2352 )\r
2353/*++\r
2354\r
2355Routine Description:\r
2356\r
2357 Whether Qtd status is transaction error or not\r
2358 \r
2359Arguments:\r
2360\r
2361 HwQtdPtr - A pointer to hardware Qtd structure\r
2362 \r
2363Returns:\r
2364\r
2365 TRUE Transaction error\r
2366 FALSE No transaction error\r
2367 \r
2368--*/\r
2369;\r
2370\r
2371BOOLEAN\r
2372IsDataInTransfer (\r
2373 IN UINT8 EndPointAddress\r
2374 )\r
2375/*++\r
2376\r
2377Routine Description:\r
2378\r
2379 Whether is a DataIn direction transfer\r
2380 \r
2381Arguments:\r
2382\r
2383 EndPointAddress - address of the endpoint \r
2384 \r
2385Returns:\r
2386\r
2387 TRUE DataIn\r
2388 FALSE DataOut\r
2389 \r
2390--*/\r
2391;\r
2392\r
2393EFI_STATUS\r
2394MapDataBuffer (\r
2395 IN USB2_HC_DEV *HcDev,\r
2396 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
2397 IN OUT VOID *Data,\r
2398 IN OUT UINTN *DataLength,\r
2399 OUT UINT8 *PktId,\r
2400 OUT UINT8 **DataCursor,\r
2401 OUT VOID **DataMap\r
2402 )\r
2403/*++\r
2404\r
2405Routine Description:\r
2406\r
2407 Map address of user data buffer\r
2408 \r
2409Arguments:\r
2410\r
2411 HcDev - USB2_HC_DEV \r
2412 TransferDirection - direction of transfer\r
2413 Data - A pointer to user data buffer \r
2414 DataLength - length of user data\r
2415 PktId - Packte Identificaion\r
2416 DataCursor - mapped address to return\r
2417 DataMap - identificaion of this mapping to return\r
2418 \r
2419Returns:\r
2420\r
2421 EFI_SUCCESS Success\r
2422 EFI_DEVICE_ERROR Fail\r
2423 \r
2424--*/\r
2425;\r
2426\r
2427EFI_STATUS\r
2428MapRequestBuffer (\r
2429 IN USB2_HC_DEV *HcDev,\r
2430 IN OUT VOID *Request,\r
2431 OUT UINT8 **RequestCursor,\r
2432 OUT VOID **RequestMap\r
2433 )\r
2434/*++\r
2435\r
2436Routine Description:\r
2437\r
2438 Map address of request structure buffer\r
2439 \r
2440Arguments:\r
2441\r
2442 HcDev - USB2_HC_DEV \r
2443 Request - A pointer to request structure\r
2444 RequestCursor - Mapped address of request structure to return\r
2445 RequestMap - Identificaion of this mapping to return\r
2446 \r
2447Returns:\r
2448\r
2449 EFI_SUCCESS Success\r
2450 EFI_DEVICE_ERROR Fail\r
2451 \r
2452--*/\r
2453;\r
2454\r
2455VOID\r
2456SetQtdBufferPointer (\r
2457 IN EHCI_QTD_HW *QtdHwPtr,\r
2458 IN VOID *DataPtr,\r
2459 IN UINTN DataLen\r
2460 )\r
2461/*++\r
2462\r
2463Routine Description:\r
2464\r
2465 Set data buffer pointers in Qtd\r
2466\r
2467Arguments:\r
2468\r
2469 QtdHwPtr - A pointer to Qtd hardware structure \r
2470 DataPtr - A pointer to user data buffer\r
2471 DataLen - Length of the user data buffer\r
2472 \r
2473Returns:\r
2474\r
2475 VOID\r
2476\r
2477--*/\r
2478;\r
2479\r
2480EHCI_QTD_HW *\r
2481GetQtdAlternateNextPointer (\r
2482 IN EHCI_QTD_HW *HwQtdPtr\r
2483 )\r
2484/*++\r
2485\r
2486Routine Description:\r
2487\r
2488 Get Qtd alternate next pointer field\r
2489 \r
2490Arguments:\r
2491\r
2492 HwQtdPtr - A pointer to hardware Qtd structure\r
2493 \r
2494Returns:\r
2495\r
2496 A pointer to hardware alternate Qtd\r
2497 \r
2498--*/\r
2499;\r
2500\r
2501VOID\r
2502ZeroOutQhOverlay (\r
2503 IN EHCI_QH_ENTITY *QhPtr\r
2504 )\r
2505/*++\r
2506\r
2507Routine Description:\r
2508\r
2509 Zero out the fields in Qh structure\r
2510 \r
2511Arguments:\r
2512\r
2513 QhPtr - A pointer to Qh structure\r
2514 \r
2515Returns:\r
2516\r
2517 VOID\r
2518 \r
2519--*/\r
2520;\r
2521\r
2522VOID\r
2523UpdateAsyncRequestTransfer (\r
2524 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,\r
2525 IN UINT32 TransferResult,\r
2526 IN UINTN ErrTDPos\r
2527 )\r
2528/*++\r
2529\r
2530Routine Description:\r
2531\r
2532 Update asynchronous request transfer\r
2533 \r
2534Arguments:\r
2535\r
2536 AsyncRequestPtr - A pointer to async request \r
2537 TransferResult - transfer result \r
2538 ErrQtdPos - postion of error Qtd\r
2539 \r
2540Returns:\r
2541\r
2542 VOID\r
2543 \r
2544--*/\r
2545;\r
2546\r
2547\r
2548EFI_STATUS\r
2549DeleteAsyncRequestTransfer (\r
2550 IN USB2_HC_DEV *HcDev,\r
2551 IN UINT8 DeviceAddress,\r
2552 IN UINT8 EndPointAddress,\r
2553 OUT UINT8 *DataToggle\r
2554 )\r
2555/*++\r
2556\r
2557Routine Description:\r
2558\r
2559 Delete all asynchronous request transfer\r
2560 \r
2561Arguments:\r
2562\r
2563 HcDev - USB2_HC_DEV \r
2564 DeviceAddress - address of usb device\r
2565 EndPointAddress - address of endpoint\r
2566 DataToggle - stored data toggle\r
2567 \r
2568Returns:\r
2569\r
2570 EFI_SUCCESS Success\r
2571 EFI_DEVICE_ERROR Fail\r
2572\r
2573--*/\r
2574;\r
2575\r
2576VOID\r
2577CleanUpAllAsyncRequestTransfer (\r
2578 IN USB2_HC_DEV *HcDev\r
2579 )\r
2580/*++\r
2581\r
2582Routine Description:\r
2583\r
2584 Clean up all asynchronous request transfer\r
2585 \r
2586Arguments:\r
2587\r
2588 HcDev - USB2_HC_DEV \r
2589 \r
2590Returns:\r
2591 VOID\r
2592 \r
2593--*/\r
2594;\r
2595\r
2596EFI_STATUS\r
2597ExecuteTransfer (\r
2598 IN USB2_HC_DEV *HcDev,\r
2599 IN BOOLEAN IsControl,\r
2600 IN EHCI_QH_ENTITY *QhPtr,\r
2601 IN OUT UINTN *ActualLen,\r
2602 OUT UINT8 *DataToggle,\r
2603 IN UINTN TimeOut,\r
2604 OUT UINT32 *TransferResult\r
2605 )\r
2606/*++\r
2607\r
2608Routine Description:\r
2609\r
2610 Execute Bulk or SyncInterrupt Transfer\r
2611\r
2612Arguments:\r
2613\r
2614 HcDev - USB2_HC_DEV\r
2615 IsControl - Is control transfer or not\r
2616 QhPtr - A pointer to Qh\r
2617 ActualLen - Actual transfered Len \r
2618 DataToggle - Data Toggle\r
2619 TimeOut - TimeOut threshold\r
2620 TransferResult - Transfer result\r
2621 \r
2622Returns:\r
2623\r
2624 EFI_SUCCESS Sucess\r
2625 EFI_DEVICE_ERROR Error\r
2626 \r
2627--*/\r
2628;\r
2629\r
2630BOOLEAN\r
2631CheckQtdsTransferResult (\r
2632 IN BOOLEAN IsControl,\r
2633 IN EHCI_QH_ENTITY *QhPtr,\r
2634 OUT UINT32 *Result,\r
2635 OUT UINTN *ErrQtdPos,\r
2636 OUT UINTN *ActualLen\r
2637 )\r
2638/*++\r
2639\r
2640Routine Description:\r
2641\r
2642 Check transfer result of Qtds\r
2643\r
2644Arguments:\r
2645\r
2646 IsControl - Is control transfer or not\r
2647 QhPtr - A pointer to Qh\r
2648 Result - Transfer result\r
2649 ErrQtdPos - Error TD Position\r
2650 ActualLen - Actual Transfer Size\r
2651\r
2652Returns:\r
2653\r
2654 TRUE Qtds finished\r
2655 FALSE Not finish\r
2656 \r
2657--*/\r
2658;\r
2659\r
2660EFI_STATUS\r
2661AsyncRequestMoniter (\r
2662 IN EFI_EVENT Event,\r
2663 IN VOID *Context\r
2664 )\r
2665/*++\r
2666\r
2667Routine Description:\r
2668 \r
2669 Interrupt transfer periodic check handler\r
2670 \r
2671Arguments:\r
2672\r
2673 Event - Interrupt event\r
2674 Context - Pointer to USB2_HC_DEV\r
2675 \r
2676Returns:\r
2677 \r
2678 EFI_SUCCESS Success\r
2679 EFI_DEVICE_ERROR Fail\r
2680 \r
2681--*/\r
2682;\r
2683\r
74c56167 2684VOID\r
2685ClearLegacySupport (\r
2686 IN USB2_HC_DEV *HcDev\r
2687 );\r
2688\r
2689VOID\r
2690HostReset (\r
2691 IN USB2_HC_DEV *HcDev\r
2692 );\r
2693\r
2694VOID \r
2695DumpEHCIPortsStatus (\r
2696 IN USB2_HC_DEV *HcDev\r
2697 );\r
562d2849 2698#endif\r
EFI Development Kit II mirror for PVE