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Make EdkModulePkg pass Intel IPF compiler with /W4 /WX switches, solving warning...
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Ehci / Dxe / Ehci.h
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562d2849 1/*++\r
2\r
4d1fe68e 3Copyright (c) 2006, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
562d2849 11\r
12Module Name:\r
13\r
14 Ehci.h\r
4d1fe68e 15\r
16Abstract:\r
17\r
562d2849 18\r
19Revision History\r
20--*/\r
21\r
22#ifndef _EHCI_H\r
23#define _EHCI_H\r
24\r
25//\r
26// Universal Host Controller Interface data structures and defines\r
27//\r
28#include <IndustryStandard/pci22.h>\r
29\r
71a62114 30\r
713ace4c 31extern UINTN gEHCDebugLevel;\r
32extern UINTN gEHCErrorLevel;\r
71a62114 33\r
562d2849 34\r
35#define STALL_1_MACRO_SECOND 1\r
36#define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND\r
37#define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r
38\r
4d1fe68e 39#define MEM_UNIT_SIZE 128\r
40\r
41\r
562d2849 42#define SETUP_PACKET_PID_CODE 0x02\r
43#define INPUT_PACKET_PID_CODE 0x01\r
44#define OUTPUT_PACKET_PID_CODE 0x0\r
45\r
46#define ITD_SELECT_TYPE 0x0\r
47#define QH_SELECT_TYPE 0x01\r
48#define SITD_SELECT_TYPE 0x02\r
49#define FSTN_SELECT_TYPE 0x03\r
50\r
51#define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND\r
52#define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND\r
53#define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND\r
54#define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND\r
55#define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND\r
56#define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND\r
57\r
58#define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */\r
59\r
4d1fe68e 60#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16\r
562d2849 61\r
62#define EHCI_MIN_PACKET_SIZE 8\r
63#define EHCI_MAX_PACKET_SIZE 1024\r
64#define EHCI_MAX_FRAME_LIST_LENGTH 1024\r
65#define EHCI_BLOCK_SIZE_WITH_TT 64\r
66#define EHCI_BLOCK_SIZE 512\r
67#define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)\r
68\r
69#define NAK_COUNT_RELOAD 3\r
4d1fe68e 70#define QTD_ERROR_COUNTER 3\r
562d2849 71#define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1\r
72\r
73#define QTD_STATUS_ACTIVE 0x80\r
74#define QTD_STATUS_HALTED 0x40\r
75#define QTD_STATUS_BUFFER_ERR 0x20\r
76#define QTD_STATUS_BABBLE_ERR 0x10\r
77#define QTD_STATUS_TRANSACTION_ERR 0x08\r
78#define QTD_STATUS_DO_STOP_SPLIT 0x02\r
79#define QTD_STATUS_DO_START_SPLIT 0\r
80#define QTD_STATUS_DO_PING 0x01\r
81#define QTD_STATUS_DO_OUT 0\r
82\r
83#define DATA0 0\r
84#define DATA1 1\r
85\r
86#define MICRO_FRAME_0_CHANNEL 0x01\r
87#define MICRO_FRAME_1_CHANNEL 0x02\r
88#define MICRO_FRAME_2_CHANNEL 0x04\r
89#define MICRO_FRAME_3_CHANNEL 0x08\r
90#define MICRO_FRAME_4_CHANNEL 0x10\r
91#define MICRO_FRAME_5_CHANNEL 0x20\r
92#define MICRO_FRAME_6_CHANNEL 0x40\r
93#define MICRO_FRAME_7_CHANNEL 0x80\r
94\r
95#define CONTROL_TRANSFER 0x01\r
96#define BULK_TRANSFER 0x02\r
97#define SYNC_INTERRUPT_TRANSFER 0x04\r
98#define ASYNC_INTERRUPT_TRANSFER 0x08\r
99#define SYNC_ISOCHRONOUS_TRANSFER 0x10\r
100#define ASYNC_ISOCHRONOUS_TRANSFER 0x20\r
101\r
102\r
103//\r
104// Enhanced Host Controller Registers definitions\r
105//\r
562d2849 106extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r
107extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r
108\r
109#define USBCMD 0x0 /* Command Register Offset 00-03h */\r
110#define USBCMD_RS 0x01 /* Run / Stop */\r
111#define USBCMD_HCRESET 0x02 /* Host controller reset */\r
112#define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */\r
113#define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */\r
114#define USBCMD_PSE 0x10 /* Periodic schedule enable */\r
115#define USBCMD_ASE 0x20 /* Asynchronous schedule enable */\r
116#define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */\r
117\r
118#define USBSTS 0x04 /* Statue Register Offset 04-07h */\r
119#define USBSTS_HSE 0x10 /* Host system error */\r
120#define USBSTS_IAA 0x20 /* Interrupt on async advance */\r
121#define USBSTS_HCH 0x1000 /* Host controller halted */\r
122#define USBSTS_PSS 0x4000 /* Periodic schedule status */\r
123#define USBSTS_ASS 0x8000 /* Asynchronous schedule status */\r
124\r
125#define USBINTR 0x08 /* Command Register Offset 08-0bh */\r
126\r
127#define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */\r
128\r
129#define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */\r
130\r
131#define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */\r
132\r
133#define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */\r
134\r
135#define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */\r
136#define CONFIGFLAG_CF 0x01 /* Configure Flag */\r
137\r
138#define PORTSC 0x44 /* Port Status/Control Offset 44-47h */\r
139#define PORTSC_CCS 0x01 /* Current Connect Status*/\r
140#define PORTSC_CSC 0x02 /* Connect Status Change */\r
141#define PORTSC_PED 0x04 /* Port Enable / Disable */\r
142#define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */\r
143#define PORTSC_OCA 0x10 /* Over current Active */\r
144#define PORTSC_OCC 0x20 /* Over current Change */\r
145#define PORTSC_FPR 0x40 /* Force Port Resume */\r
146#define PORTSC_SUSP 0x80 /* Port Suspend State */\r
147#define PORTSC_PR 0x100 /* Port Reset */\r
148#define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */\r
149#define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */\r
150#define PORTSC_PP 0x1000 /* Port Power */\r
151#define PORTSC_PO 0x2000 /* Port Owner */\r
152\r
153#define CAPLENGTH 0 /* Capability Register Length 00h */\r
154\r
155#define HCIVERSION 0x02 /* Interface Version Number 02-03h */\r
156\r
157#define HCSPARAMS 0x04 /* Structural Parameters 04-07h */\r
158#define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */\r
159\r
160#define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */\r
161#define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */\r
162#define HCCP_PFLF 0x02 /* Programmable Frame List Flag */\r
163#define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */\r
164\r
165#define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */\r
166\r
167#define CLASSC 0x09 /* Class Code 09-0bh */\r
168\r
169#define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */\r
170\r
171#define SBRN 0x60 /* Serial Bus Release Number 60h */\r
172\r
173#define FLADJ 0x61 /* Frame Length Adjustment Register 61h */\r
174\r
175#define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */\r
176\r
177//\r
178// PCI Configuration Registers\r
179//\r
180#define EHCI_PCI_CLASSC 0x09\r
181#define EHCI_PCI_MEMORY_BASE 0x10\r
182\r
183//\r
184// Memory Offset Registers\r
185//\r
186#define EHCI_MEMORY_CAPLENGTH 0x0\r
187#define EHCI_MEMORY_CONFIGFLAG 0x40\r
188\r
189//\r
190// USB Base Class Code,Sub-Class Code and Programming Interface\r
191//\r
192#define PCI_CLASSC_PI_EHCI 0x20\r
193\r
194#define SETUP_PACKET_ID 0x2D\r
195#define INPUT_PACKET_ID 0x69\r
196#define OUTPUT_PACKET_ID 0xE1\r
197#define ERROR_PACKET_ID 0x55\r
198\r
71a62114 199#define bit(a) (1 << (a))\r
200\r
201#define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))\r
202#define GET_32B_TO_63B(Addr) ((UINTN)RShiftU64((UINTN) Addr, 32) & (0xffffffff))\r
562d2849 203\r
204\r
205//\r
206// Ehci Data and Ctrl Structures\r
207//\r
208#pragma pack(1)\r
209\r
210typedef struct {\r
211 UINT8 PI;\r
212 UINT8 SubClassCode;\r
213 UINT8 BaseCode;\r
214} USB_CLASSC;\r
215\r
4d1fe68e 216//\r
217//32 Bytes Aligned\r
218//\r
562d2849 219typedef struct {\r
220 UINT32 NextQtdTerminate : 1;\r
221 UINT32 Rsvd1 : 4;\r
222 UINT32 NextQtdPointer : 27;\r
223\r
224 UINT32 AltNextQtdTerminate : 1;\r
225 UINT32 Rsvd2 : 4;\r
226 UINT32 AltNextQtdPointer : 27;\r
227\r
228 UINT32 Status : 8;\r
229 UINT32 PidCode : 2;\r
230 UINT32 ErrorCount : 2;\r
231 UINT32 CurrentPage : 3;\r
232 UINT32 InterruptOnComplete : 1;\r
233 UINT32 TotalBytes : 15;\r
234 UINT32 DataToggle : 1;\r
235\r
236 UINT32 CurrentOffset : 12;\r
237 UINT32 BufferPointer0 : 20;\r
238\r
239 UINT32 Rsvd3 : 12;\r
240 UINT32 BufferPointer1 : 20;\r
241\r
242 UINT32 Rsvd4 : 12;\r
243 UINT32 BufferPointer2 : 20;\r
244\r
245 UINT32 Rsvd5 : 12;\r
246 UINT32 BufferPointer3 : 20;\r
247\r
248 UINT32 Rsvd6 : 12;\r
249 UINT32 BufferPointer4 : 20;\r
250\r
4d1fe68e 251 UINT32 PAD[5];\r
562d2849 252} EHCI_QTD_HW;\r
253\r
4d1fe68e 254//\r
255//32 Bytes Aligned\r
256//\r
562d2849 257typedef struct {\r
258 UINT32 QhTerminate : 1;\r
259 UINT32 SelectType : 2;\r
260 UINT32 Rsvd1 : 2;\r
261 UINT32 QhHorizontalPointer : 27;\r
262\r
263 UINT32 DeviceAddr : 7;\r
264 UINT32 Inactive : 1;\r
265 UINT32 EndpointNum : 4;\r
266 UINT32 EndpointSpeed : 2;\r
267 UINT32 DataToggleControl : 1;\r
268 UINT32 HeadReclamationFlag : 1;\r
269 UINT32 MaxPacketLen : 11;\r
270 UINT32 ControlEndpointFlag : 1;\r
271 UINT32 NakCountReload : 4;\r
272\r
273 UINT32 InerruptScheduleMask : 8;\r
274 UINT32 SplitComletionMask : 8;\r
275 UINT32 HubAddr : 7;\r
276 UINT32 PortNum : 7;\r
277 UINT32 Multiplier : 2;\r
278\r
279 UINT32 Rsvd2 : 5;\r
280 UINT32 CurrentQtdPointer : 27;\r
281\r
282 UINT32 NextQtdTerminate : 1;\r
283 UINT32 Rsvd3 : 4;\r
284 UINT32 NextQtdPointer : 27;\r
285\r
286 UINT32 AltNextQtdTerminate : 1;\r
287 UINT32 NakCount : 4;\r
288 UINT32 AltNextQtdPointer : 27;\r
289\r
290 UINT32 Status : 8;\r
291 UINT32 PidCode : 2;\r
292 UINT32 ErrorCount : 2;\r
293 UINT32 CurrentPage : 3;\r
294 UINT32 InterruptOnComplete : 1;\r
295 UINT32 TotalBytes : 15;\r
296 UINT32 DataToggle : 1;\r
297\r
298 UINT32 CurrentOffset : 12;\r
299 UINT32 BufferPointer0 : 20;\r
300\r
301 UINT32 CompleteSplitMask : 8;\r
302 UINT32 Rsvd4 : 4;\r
303 UINT32 BufferPointer1 : 20;\r
304\r
305 UINT32 FrameTag : 5;\r
306 UINT32 SplitBytes : 7;\r
307 UINT32 BufferPointer2 : 20;\r
308\r
309 UINT32 Rsvd5 : 12;\r
310 UINT32 BufferPointer3 : 20;\r
311\r
312 UINT32 Rsvd6 : 12;\r
313 UINT32 BufferPointer4 : 20;\r
314\r
4d1fe68e 315 UINT32 Pad[5];\r
562d2849 316} EHCI_QH_HW;\r
317\r
318typedef struct {\r
319 UINT32 LinkTerminate : 1;\r
320 UINT32 SelectType : 2;\r
321 UINT32 Rsvd : 2;\r
322 UINT32 LinkPointer : 27;\r
323} FRAME_LIST_ENTRY;\r
324\r
325#pragma pack()\r
326\r
327typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY;\r
328typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY;\r
329typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST;\r
4d1fe68e 330//\r
331//Aligan On 32 Bytes\r
332//\r
ffac4bcb 333struct _EHCI_QTD_ENTITY {\r
562d2849 334 EHCI_QTD_HW Qtd;\r
335 UINT32 TotalBytes;\r
336 UINT32 StaticTotalBytes;\r
337 UINT32 StaticCurrentOffset;\r
338 EHCI_QTD_ENTITY *Prev;\r
339 EHCI_QTD_ENTITY *Next;\r
340 EHCI_QTD_ENTITY *AltNext;\r
341 EHCI_QH_ENTITY *SelfQh;\r
ffac4bcb 342};\r
4d1fe68e 343//\r
344//Aligan On 32 Bytes\r
345//\r
ffac4bcb 346struct _EHCI_QH_ENTITY {\r
562d2849 347 EHCI_QH_HW Qh;\r
348 EHCI_QH_ENTITY *Next;\r
349 EHCI_QH_ENTITY *Prev;\r
350 EHCI_QTD_ENTITY *FirstQtdPtr;\r
351 EHCI_QTD_ENTITY *LastQtdPtr;\r
352 EHCI_QTD_ENTITY *AltQtdPtr;\r
353 UINTN Interval;\r
354 UINT8 TransferType;\r
ffac4bcb 355};\r
562d2849 356\r
357#define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)\r
358#define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)\r
359\r
360\r
361//\r
362// Ehci Managment Structures\r
363//\r
364#define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r
365\r
366#define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')\r
367\r
ffac4bcb 368struct _EHCI_ASYNC_REQUEST {\r
562d2849 369 UINT8 TransferType;\r
370 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc;\r
371 VOID *Context;\r
372 EHCI_ASYNC_REQUEST *Prev;\r
373 EHCI_ASYNC_REQUEST *Next;\r
374 EHCI_QH_ENTITY *QhPtr;\r
ffac4bcb 375};\r
562d2849 376\r
377typedef struct _MEMORY_MANAGE_HEADER {\r
378 UINT8 *BitArrayPtr;\r
379 UINTN BitArraySizeInBytes;\r
380 UINT8 *MemoryBlockPtr;\r
381 UINTN MemoryBlockSizeInBytes;\r
382 VOID *Mapping;\r
383 struct _MEMORY_MANAGE_HEADER *Next;\r
384} MEMORY_MANAGE_HEADER;\r
385\r
386typedef struct _USB2_HC_DEV {\r
387 UINTN Signature;\r
388 EFI_PCI_IO_PROTOCOL *PciIo;\r
389 EFI_USB2_HC_PROTOCOL Usb2Hc;\r
390 UINTN PeriodicFrameListLength;\r
391 VOID *PeriodicFrameListBuffer;\r
392 VOID *PeriodicFrameListMap;\r
393 VOID *AsyncList;\r
394 EHCI_ASYNC_REQUEST *AsyncRequestList;\r
395 EFI_EVENT AsyncRequestEvent;\r
396 EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
397 MEMORY_MANAGE_HEADER *MemoryHeader;\r
4d1fe68e 398 UINT8 Is64BitCapable;\r
562d2849 399 UINT32 High32BitAddr;\r
4d1fe68e 400 EHCI_QH_ENTITY *NULLQH;\r
37279806 401 UINT32 UsbCapabilityLen;\r
402 UINT16 DeviceSpeed[16];\r
562d2849 403} USB2_HC_DEV;\r
404\r
405\r
92dda53e 406//\r
407// Prototypes\r
408// Driver model protocol interface\r
409//\r
410\r
411EFI_STATUS\r
412EFIAPI\r
413EhciDriverBindingSupported (\r
414 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
415 IN EFI_HANDLE Controller,\r
416 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
417 );\r
418\r
419EFI_STATUS\r
420EFIAPI\r
421EhciDriverBindingStart (\r
422 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
423 IN EFI_HANDLE Controller,\r
424 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
425 );\r
426\r
427EFI_STATUS\r
428EFIAPI\r
429EhciDriverBindingStop (\r
430 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
431 IN EFI_HANDLE Controller,\r
432 IN UINTN NumberOfChildren,\r
433 IN EFI_HANDLE *ChildHandleBuffer\r
434 );\r
435\r
436//\r
437// Ehci protocol interface\r
438//\r
439EFI_STATUS\r
440EFIAPI\r
441EhciGetCapability (\r
442 IN EFI_USB2_HC_PROTOCOL *This,\r
443 OUT UINT8 *MaxSpeed,\r
444 OUT UINT8 *PortNumber,\r
445 OUT UINT8 *Is64BitCapable\r
446 );\r
447\r
448EFI_STATUS\r
449EFIAPI\r
450EhciReset (\r
451 IN EFI_USB2_HC_PROTOCOL *This,\r
452 IN UINT16 Attributes\r
453 );\r
454\r
455EFI_STATUS\r
456EFIAPI\r
457EhciGetState (\r
458 IN EFI_USB2_HC_PROTOCOL *This,\r
459 OUT EFI_USB_HC_STATE *State\r
460 );\r
461\r
462EFI_STATUS\r
463EFIAPI\r
464EhciSetState (\r
465 IN EFI_USB2_HC_PROTOCOL *This,\r
466 IN EFI_USB_HC_STATE State\r
467 );\r
468\r
469EFI_STATUS\r
470EFIAPI\r
471EhciControlTransfer (\r
472 IN EFI_USB2_HC_PROTOCOL *This,\r
473 IN UINT8 DeviceAddress,\r
474 IN UINT8 DeviceSpeed,\r
475 IN UINTN MaximumPacketLength,\r
476 IN EFI_USB_DEVICE_REQUEST *Request,\r
477 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
478 IN OUT VOID *Data,\r
479 IN OUT UINTN *DataLength,\r
480 IN UINTN TimeOut,\r
481 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
482 OUT UINT32 *TransferResult\r
483 );\r
484\r
485EFI_STATUS\r
486EFIAPI\r
487EhciBulkTransfer (\r
488 IN EFI_USB2_HC_PROTOCOL *This,\r
489 IN UINT8 DeviceAddress,\r
490 IN UINT8 EndPointAddress,\r
491 IN UINT8 DeviceSpeed,\r
492 IN UINTN MaximumPacketLength,\r
493 IN UINT8 DataBuffersNumber,\r
494 IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],\r
495 IN OUT UINTN *DataLength,\r
496 IN OUT UINT8 *DataToggle,\r
497 IN UINTN TimeOut,\r
498 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
499 OUT UINT32 *TransferResult\r
500 );\r
501\r
502EFI_STATUS\r
503EFIAPI\r
504EhciAsyncInterruptTransfer (\r
505 IN EFI_USB2_HC_PROTOCOL * This,\r
506 IN UINT8 DeviceAddress,\r
507 IN UINT8 EndPointAddress,\r
508 IN UINT8 DeviceSpeed,\r
509 IN UINTN MaxiumPacketLength,\r
510 IN BOOLEAN IsNewTransfer,\r
511 IN OUT UINT8 *DataToggle,\r
512 IN UINTN PollingInterval,\r
513 IN UINTN DataLength,\r
514 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
515 IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,\r
516 IN VOID *Context OPTIONAL\r
517 );\r
518\r
519EFI_STATUS\r
520EFIAPI\r
521EhciSyncInterruptTransfer (\r
522 IN EFI_USB2_HC_PROTOCOL *This,\r
523 IN UINT8 DeviceAddress,\r
524 IN UINT8 EndPointAddress,\r
525 IN UINT8 DeviceSpeed,\r
526 IN UINTN MaximumPacketLength,\r
527 IN OUT VOID *Data,\r
528 IN OUT UINTN *DataLength,\r
529 IN OUT UINT8 *DataToggle,\r
530 IN UINTN TimeOut,\r
531 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
532 OUT UINT32 *TransferResult\r
533 );\r
534\r
535EFI_STATUS\r
536EFIAPI\r
537EhciIsochronousTransfer (\r
538 IN EFI_USB2_HC_PROTOCOL *This,\r
539 IN UINT8 DeviceAddress,\r
540 IN UINT8 EndPointAddress,\r
541 IN UINT8 DeviceSpeed,\r
542 IN UINTN MaximumPacketLength,\r
543 IN UINT8 DataBuffersNumber,\r
544 IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],\r
545 IN UINTN DataLength,\r
546 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
547 OUT UINT32 *TransferResult\r
548 );\r
549\r
550EFI_STATUS\r
551EFIAPI\r
552EhciAsyncIsochronousTransfer (\r
553 IN EFI_USB2_HC_PROTOCOL *This,\r
554 IN UINT8 DeviceAddress,\r
555 IN UINT8 EndPointAddress,\r
556 IN UINT8 DeviceSpeed,\r
557 IN UINTN MaximumPacketLength,\r
558 IN UINT8 DataBuffersNumber,\r
559 IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],\r
560 IN UINTN DataLength,\r
561 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
562 IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack,\r
563 IN VOID *Context\r
564 );\r
565\r
566EFI_STATUS\r
567EFIAPI\r
568EhciGetRootHubPortStatus (\r
569 IN EFI_USB2_HC_PROTOCOL *This,\r
570 IN UINT8 PortNumber,\r
571 OUT EFI_USB_PORT_STATUS *PortStatus\r
572 );\r
573\r
574EFI_STATUS\r
575EFIAPI\r
576EhciSetRootHubPortFeature (\r
577 IN EFI_USB2_HC_PROTOCOL *This,\r
578 IN UINT8 PortNumber,\r
579 IN EFI_USB_PORT_FEATURE PortFeature\r
580 );\r
581\r
582EFI_STATUS\r
583EFIAPI\r
584EhciClearRootHubPortFeature (\r
585 IN EFI_USB2_HC_PROTOCOL *This,\r
586 IN UINT8 PortNumber,\r
587 IN EFI_USB_PORT_FEATURE PortFeature\r
588 );\r
589\r
590//\r
591// EFI Component Name Functions\r
592//\r
593EFI_STATUS\r
594EFIAPI\r
595EhciComponentNameGetDriverName (\r
596 IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
597 IN CHAR8 *Language,\r
598 OUT CHAR16 **DriverName\r
599 );\r
600\r
601EFI_STATUS\r
602EFIAPI\r
603EhciComponentNameGetControllerName (\r
604 IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
605 IN EFI_HANDLE ControllerHandle,\r
606 IN EFI_HANDLE ChildHandle, OPTIONAL\r
607 IN CHAR8 *Language,\r
608 OUT CHAR16 **ControllerName\r
609 );\r
610\r
562d2849 611//\r
612// Internal Functions Declaration\r
613//\r
614\r
615//\r
616// EhciMem Functions\r
617//\r
618EFI_STATUS\r
619CreateMemoryBlock (\r
620 IN USB2_HC_DEV *HcDev,\r
621 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
622 IN UINTN MemoryBlockSizeInPages\r
623 )\r
624/*++\r
625\r
626Routine Description:\r
627\r
628 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,\r
629 and use PciIo->Map to map the common buffer for Bus Master Read/Write.\r
630\r
631Arguments:\r
632\r
633 HcDev - USB2_HC_DEV\r
634 MemoryHeader - MEMORY_MANAGE_HEADER to output\r
635 MemoryBlockSizeInPages - MemoryBlockSizeInPages\r
4d1fe68e 636\r
562d2849 637Returns:\r
638\r
639 EFI_SUCCESS Success\r
640 EFI_OUT_OF_RESOURCES Fail for no resources\r
641 EFI_UNSUPPORTED Unsupported currently\r
4d1fe68e 642\r
562d2849 643--*/\r
644;\r
645\r
646EFI_STATUS\r
647FreeMemoryHeader (\r
648 IN USB2_HC_DEV *HcDev,\r
649 IN MEMORY_MANAGE_HEADER *MemoryHeader\r
650 )\r
651/*++\r
652\r
653Routine Description:\r
654\r
655 Free Memory Header\r
656\r
657Arguments:\r
658\r
659 HcDev - USB2_HC_DEV\r
660 MemoryHeader - MemoryHeader to be freed\r
661\r
662Returns:\r
663\r
664 EFI_SUCCESS Success\r
665 EFI_INVALID_PARAMETER Parameter is error\r
666\r
667--*/\r
668;\r
669\r
670VOID\r
671InsertMemoryHeaderToList (\r
672 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
673 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
674 )\r
675/*++\r
676\r
677Routine Description:\r
678\r
679 Insert Memory Header To List\r
680\r
681Arguments:\r
682\r
683 MemoryHeader - MEMORY_MANAGE_HEADER\r
684 NewMemoryHeader - MEMORY_MANAGE_HEADER\r
685\r
686Returns:\r
687\r
688 VOID\r
689\r
690--*/\r
691;\r
692\r
693EFI_STATUS\r
694AllocMemInMemoryBlock (\r
695 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
696 OUT VOID **Pool,\r
697 IN UINTN NumberOfMemoryUnit\r
698 )\r
699/*++\r
700\r
701Routine Description:\r
702\r
703 Alloc Memory In MemoryBlock\r
704\r
705Arguments:\r
706\r
707 MemoryHeader - MEMORY_MANAGE_HEADER\r
708 Pool - Place to store pointer to memory\r
709 NumberOfMemoryUnit - Number Of Memory Unit\r
710\r
711Returns:\r
712\r
713 EFI_SUCCESS Success\r
4d1fe68e 714 EFI_NOT_FOUND Can't find the free memory\r
562d2849 715\r
716--*/\r
717;\r
718\r
719BOOLEAN\r
720IsMemoryBlockEmptied (\r
721 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
722 )\r
723/*++\r
724\r
725Routine Description:\r
726\r
727 Is Memory Block Emptied\r
728\r
729Arguments:\r
730\r
731 MemoryHeaderPtr - MEMORY_MANAGE_HEADER\r
732\r
733Returns:\r
734\r
735 TRUE Empty\r
4d1fe68e 736 FALSE Not Empty\r
562d2849 737\r
738--*/\r
739;\r
740\r
741VOID\r
742DelinkMemoryBlock (\r
743 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
744 IN MEMORY_MANAGE_HEADER *NeedFreeMemoryHeader\r
745 )\r
746/*++\r
747\r
748Routine Description:\r
749\r
750 Delink Memory Block\r
751\r
752Arguments:\r
753\r
754 FirstMemoryHeader - MEMORY_MANAGE_HEADER\r
755 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER\r
756\r
757Returns:\r
758\r
759 VOID\r
760\r
761--*/\r
762;\r
763\r
764EFI_STATUS\r
765InitialMemoryManagement (\r
766 IN USB2_HC_DEV *HcDev\r
767 )\r
768/*++\r
769\r
770Routine Description:\r
771\r
772 Initialize Memory Management\r
773\r
774Arguments:\r
775\r
776 HcDev - USB2_HC_DEV\r
777\r
778Returns:\r
779\r
780 EFI_SUCCESS Success\r
781 EFI_DEVICE_ERROR Fail\r
782\r
783--*/\r
784;\r
785\r
786EFI_STATUS\r
787DeinitialMemoryManagement (\r
788 IN USB2_HC_DEV *HcDev\r
789 )\r
790/*++\r
791\r
792Routine Description:\r
793\r
794 Deinitialize Memory Management\r
795\r
796Arguments:\r
797\r
798 HcDev - USB2_HC_DEV\r
799\r
800Returns:\r
801\r
802 EFI_SUCCESS Success\r
803 EFI_DEVICE_ERROR Fail\r
4d1fe68e 804\r
562d2849 805--*/\r
806;\r
807\r
808EFI_STATUS\r
809EhciAllocatePool (\r
810 IN USB2_HC_DEV *HcDev,\r
811 OUT UINT8 **Pool,\r
812 IN UINTN AllocSize\r
813 )\r
814/*++\r
815\r
816Routine Description:\r
817\r
818 Ehci Allocate Pool\r
819\r
820Arguments:\r
821\r
822 HcDev - USB2_HC_DEV\r
823 Pool - Place to store pointer to the memory buffer\r
824 AllocSize - Alloc Size\r
825\r
826Returns:\r
827\r
828 EFI_SUCCESS Success\r
829 EFI_DEVICE_ERROR Fail\r
4d1fe68e 830\r
562d2849 831--*/\r
832;\r
833\r
834VOID\r
835EhciFreePool (\r
836 IN USB2_HC_DEV *HcDev,\r
837 IN UINT8 *Pool,\r
838 IN UINTN AllocSize\r
839 )\r
840/*++\r
841\r
842Routine Description:\r
843\r
844 Uhci Free Pool\r
845\r
846Arguments:\r
847\r
848 HcDev - USB_HC_DEV\r
849 Pool - Pool to free\r
850 AllocSize - Pool size\r
851\r
852Returns:\r
853\r
854 VOID\r
855\r
856--*/\r
857;\r
858\r
859//\r
860// EhciReg Functions\r
861//\r
862EFI_STATUS\r
863ReadEhcCapabiltiyReg (\r
864 IN USB2_HC_DEV *HcDev,\r
865 IN UINT32 CapabiltiyRegAddr,\r
866 IN OUT UINT32 *Data\r
867 )\r
868/*++\r
869\r
870Routine Description:\r
871\r
872 Read Ehc Capabitlity register\r
4d1fe68e 873\r
562d2849 874Arguments:\r
875\r
4d1fe68e 876 HcDev - USB2_HC_DEV\r
562d2849 877 CapabiltiyRegAddr - Ehc Capability register address\r
878 Data - A pointer to data read from register\r
4d1fe68e 879\r
562d2849 880Returns:\r
881\r
882 EFI_SUCCESS Success\r
883 EFI_DEVICE_ERROR Fail\r
4d1fe68e 884\r
562d2849 885--*/\r
886;\r
887\r
888EFI_STATUS\r
889ReadEhcOperationalReg (\r
890 IN USB2_HC_DEV *HcDev,\r
891 IN UINT32 OperationalRegAddr,\r
892 IN OUT UINT32 *Data\r
893 )\r
894/*++\r
895\r
896Routine Description:\r
897\r
898 Read Ehc Operation register\r
4d1fe68e 899\r
562d2849 900Arguments:\r
901\r
4d1fe68e 902 HcDev - USB2_HC_DEV\r
562d2849 903 OperationalRegAddr - Ehc Operation register address\r
904 Data - A pointer to data read from register\r
4d1fe68e 905\r
562d2849 906Returns:\r
907\r
908 EFI_SUCCESS Success\r
909 EFI_DEVICE_ERROR Fail\r
4d1fe68e 910\r
562d2849 911--*/\r
912;\r
913\r
914EFI_STATUS\r
915WriteEhcOperationalReg (\r
916 IN USB2_HC_DEV *HcDev,\r
917 IN UINT32 OperationalRegAddr,\r
918 IN UINT32 Data\r
919 )\r
920/*++\r
921\r
922Routine Description:\r
923\r
924 Write Ehc Operation register\r
4d1fe68e 925\r
562d2849 926Arguments:\r
927\r
4d1fe68e 928 HcDev - USB2_HC_DEV\r
562d2849 929 OperationalRegAddr - Ehc Operation register address\r
930 Data - 32bit write to register\r
4d1fe68e 931\r
562d2849 932Returns:\r
933\r
934 EFI_SUCCESS Success\r
935 EFI_DEVICE_ERROR Fail\r
4d1fe68e 936\r
562d2849 937--*/\r
938;\r
939\r
940EFI_STATUS\r
941SetEhcDoorbell (\r
942 IN USB2_HC_DEV *HcDev\r
943 )\r
944/*++\r
945\r
946Routine Description:\r
947\r
948 Set Ehc door bell bit\r
4d1fe68e 949\r
562d2849 950Arguments:\r
951\r
4d1fe68e 952 HcDev - USB2_HC_DEV\r
953\r
562d2849 954Returns:\r
955\r
956 EFI_SUCCESS Success\r
957 EFI_DEVICE_ERROR Fail\r
4d1fe68e 958\r
562d2849 959--*/\r
960;\r
961\r
962EFI_STATUS\r
963SetFrameListLen (\r
964 IN USB2_HC_DEV *HcDev,\r
965 IN UINTN Length\r
966 )\r
967/*++\r
968\r
969Routine Description:\r
970\r
971 Set the length of Frame List\r
4d1fe68e 972\r
562d2849 973Arguments:\r
974\r
4d1fe68e 975 HcDev - USB2_HC_DEV\r
562d2849 976 Length - the required length of frame list\r
4d1fe68e 977\r
562d2849 978Returns:\r
979\r
980 EFI_SUCCESS Success\r
981 EFI_INVALID_PARAMETER Invalid parameter\r
982 EFI_DEVICE_ERROR Fail\r
4d1fe68e 983\r
562d2849 984--*/\r
985;\r
986\r
987BOOLEAN\r
988IsFrameListProgrammable (\r
989 IN USB2_HC_DEV *HcDev\r
990 )\r
991/*++\r
992\r
993Routine Description:\r
994\r
995 Whether frame list is programmable\r
4d1fe68e 996\r
562d2849 997Arguments:\r
998\r
4d1fe68e 999 HcDev - USB2_HC_DEV\r
1000\r
562d2849 1001Returns:\r
1002\r
1003 TRUE Programmable\r
1004 FALSE Unprogrammable\r
4d1fe68e 1005\r
562d2849 1006--*/\r
1007;\r
1008\r
1009BOOLEAN\r
1010IsPeriodicScheduleEnabled (\r
1011 IN USB2_HC_DEV *HcDev\r
1012 )\r
1013/*++\r
1014\r
1015Routine Description:\r
1016\r
1017 Whether periodic schedule is enabled\r
4d1fe68e 1018\r
562d2849 1019Arguments:\r
1020\r
4d1fe68e 1021 HcDev - USB2_HC_DEV\r
1022\r
562d2849 1023Returns:\r
1024\r
1025 TRUE Enabled\r
1026 FALSE Disabled\r
4d1fe68e 1027\r
562d2849 1028--*/\r
1029;\r
1030\r
1031BOOLEAN\r
1032IsAsyncScheduleEnabled (\r
1033 IN USB2_HC_DEV *HcDev\r
1034 )\r
1035/*++\r
1036\r
1037Routine Description:\r
1038\r
1039 Whether asynchronous schedule is enabled\r
4d1fe68e 1040\r
562d2849 1041Arguments:\r
1042\r
4d1fe68e 1043 HcDev - USB2_HC_DEV\r
1044\r
562d2849 1045Returns:\r
1046\r
1047 TRUE Enabled\r
1048 FALSE Disabled\r
4d1fe68e 1049\r
562d2849 1050--*/\r
1051;\r
1052\r
1053BOOLEAN\r
1054IsEhcPortEnabled (\r
1055 IN USB2_HC_DEV *HcDev,\r
1056 IN UINT8 PortNum\r
1057 )\r
1058/*++\r
1059\r
1060Routine Description:\r
1061\r
1062 Whether port is enabled\r
4d1fe68e 1063\r
562d2849 1064Arguments:\r
1065\r
4d1fe68e 1066 HcDev - USB2_HC_DEV\r
1067\r
562d2849 1068Returns:\r
1069\r
1070 TRUE Enabled\r
1071 FALSE Disabled\r
4d1fe68e 1072\r
562d2849 1073--*/\r
1074;\r
1075\r
1076BOOLEAN\r
1077IsEhcReseted (\r
1078 IN USB2_HC_DEV *HcDev\r
1079 )\r
1080/*++\r
1081\r
1082Routine Description:\r
1083\r
1084 Whether Ehc is halted\r
4d1fe68e 1085\r
562d2849 1086Arguments:\r
1087\r
4d1fe68e 1088 HcDev - USB2_HC_DEV\r
1089\r
562d2849 1090Returns:\r
1091\r
1092 TRUE Reseted\r
1093 FALSE Unreseted\r
4d1fe68e 1094\r
562d2849 1095--*/\r
1096;\r
1097\r
1098BOOLEAN\r
1099IsEhcHalted (\r
1100 IN USB2_HC_DEV *HcDev\r
1101 )\r
1102/*++\r
1103\r
1104Routine Description:\r
1105\r
1106 Whether Ehc is halted\r
4d1fe68e 1107\r
562d2849 1108Arguments:\r
1109\r
4d1fe68e 1110 HcDev - USB2_HC_DEV\r
1111\r
562d2849 1112Returns:\r
1113\r
1114 TRUE Halted\r
1115 FALSE Not halted\r
4d1fe68e 1116\r
562d2849 1117--*/\r
1118;\r
1119\r
1120BOOLEAN\r
1121IsEhcSysError (\r
1122 IN USB2_HC_DEV *HcDev\r
1123 )\r
1124/*++\r
1125\r
1126Routine Description:\r
1127\r
1128 Whether Ehc is system error\r
4d1fe68e 1129\r
562d2849 1130Arguments:\r
1131\r
4d1fe68e 1132 HcDev - USB2_HC_DEV\r
1133\r
562d2849 1134Returns:\r
1135\r
1136 TRUE System error\r
1137 FALSE No system error\r
4d1fe68e 1138\r
562d2849 1139--*/\r
1140;\r
1141\r
1142BOOLEAN\r
1143IsHighSpeedDevice (\r
1144 IN EFI_USB2_HC_PROTOCOL *This,\r
4d1fe68e 1145 IN UINT8 PortNum\r
562d2849 1146 )\r
1147/*++\r
1148\r
1149Routine Description:\r
1150\r
1151 Whether high speed device attached\r
4d1fe68e 1152\r
562d2849 1153Arguments:\r
1154\r
4d1fe68e 1155 HcDev - USB2_HC_DEV\r
1156\r
562d2849 1157Returns:\r
1158\r
1159 TRUE High speed\r
1160 FALSE Full speed\r
4d1fe68e 1161\r
562d2849 1162--*/\r
1163;\r
1164\r
1165EFI_STATUS\r
1166WaitForEhcReset (\r
1167 IN USB2_HC_DEV *HcDev,\r
1168 IN UINTN Timeout\r
1169 )\r
1170/*++\r
1171\r
1172Routine Description:\r
1173\r
1174 wait for Ehc reset or timeout\r
4d1fe68e 1175\r
562d2849 1176Arguments:\r
1177\r
4d1fe68e 1178 HcDev - USB2_HC_DEV\r
562d2849 1179 Timeout - timeout threshold\r
4d1fe68e 1180\r
562d2849 1181Returns:\r
1182\r
1183 EFI_SUCCESS Success\r
1184 EFI_TIMEOUT Timeout\r
4d1fe68e 1185\r
562d2849 1186--*/\r
1187;\r
1188\r
1189EFI_STATUS\r
1190WaitForEhcHalt (\r
1191 IN USB2_HC_DEV *HcDev,\r
1192 IN UINTN Timeout\r
1193 )\r
1194/*++\r
1195\r
1196Routine Description:\r
1197\r
1198 wait for Ehc halt or timeout\r
4d1fe68e 1199\r
562d2849 1200Arguments:\r
1201\r
4d1fe68e 1202 HcDev - USB2_HC_DEV\r
562d2849 1203 Timeout - timeout threshold\r
4d1fe68e 1204\r
562d2849 1205Returns:\r
1206\r
1207 EFI_SUCCESS Success\r
1208 EFI_TIMEOUT Timeout\r
4d1fe68e 1209\r
562d2849 1210--*/\r
1211;\r
1212\r
1213EFI_STATUS\r
1214WaitForEhcNotHalt (\r
1215 IN USB2_HC_DEV *HcDev,\r
1216 IN UINTN Timeout\r
1217 )\r
1218/*++\r
1219\r
1220Routine Description:\r
1221\r
1222 wait for Ehc not halt or timeout\r
4d1fe68e 1223\r
562d2849 1224Arguments:\r
1225\r
4d1fe68e 1226 HcDev - USB2_HC_DEV\r
562d2849 1227 Timeout - timeout threshold\r
4d1fe68e 1228\r
562d2849 1229Returns:\r
1230\r
1231 EFI_SUCCESS Success\r
1232 EFI_TIMEOUT Timeout\r
4d1fe68e 1233\r
562d2849 1234--*/\r
1235;\r
1236\r
1237EFI_STATUS\r
1238WaitForEhcDoorbell (\r
1239 IN USB2_HC_DEV *HcDev,\r
1240 IN UINTN Timeout\r
1241 )\r
1242/*++\r
1243\r
1244Routine Description:\r
1245\r
1246 Wait for periodic schedule disable or timeout\r
1247\r
1248Arguments:\r
1249\r
4d1fe68e 1250 HcDev - USB2_HC_DEV\r
562d2849 1251 Timeout - timeout threshold\r
1252\r
1253Returns:\r
1254\r
1255 EFI_SUCCESS Success\r
1256 EFI_TIMEOUT Timeout\r
4d1fe68e 1257\r
562d2849 1258--*/\r
1259;\r
1260\r
1261EFI_STATUS\r
1262WaitForAsyncScheduleEnable (\r
1263 IN USB2_HC_DEV *HcDev,\r
1264 IN UINTN Timeout\r
1265 )\r
1266/*++\r
1267\r
1268Routine Description:\r
1269\r
1270 Wait for Ehc asynchronous schedule enable or timeout\r
4d1fe68e 1271\r
562d2849 1272Arguments:\r
1273\r
4d1fe68e 1274 HcDev - USB2_HC_DEV\r
562d2849 1275 Timeout - timeout threshold\r
4d1fe68e 1276\r
562d2849 1277Returns:\r
1278\r
1279 EFI_SUCCESS Success\r
1280 EFI_TIMEOUT Timeout\r
4d1fe68e 1281\r
562d2849 1282--*/\r
1283;\r
1284\r
1285EFI_STATUS\r
1286WaitForAsyncScheduleDisable (\r
1287 IN USB2_HC_DEV *HcDev,\r
1288 IN UINTN Timeout\r
1289 )\r
1290/*++\r
1291\r
1292Routine Description:\r
1293\r
1294 Wait for Ehc asynchronous schedule disable or timeout\r
4d1fe68e 1295\r
562d2849 1296Arguments:\r
1297\r
4d1fe68e 1298 HcDev - USB2_HC_DEV\r
562d2849 1299 Timeout - timeout threshold\r
4d1fe68e 1300\r
562d2849 1301Returns:\r
1302\r
1303 EFI_SUCCESS Success\r
1304 EFI_TIMEOUT Timeout\r
4d1fe68e 1305\r
562d2849 1306--*/\r
1307;\r
1308\r
1309EFI_STATUS\r
1310WaitForPeriodicScheduleEnable (\r
1311 IN USB2_HC_DEV *HcDev,\r
1312 IN UINTN Timeout\r
1313 )\r
1314/*++\r
1315\r
1316Routine Description:\r
1317\r
1318 Wait for Ehc periodic schedule enable or timeout\r
4d1fe68e 1319\r
562d2849 1320Arguments:\r
1321\r
4d1fe68e 1322 HcDev - USB2_HC_DEV\r
562d2849 1323 Timeout - timeout threshold\r
4d1fe68e 1324\r
562d2849 1325Returns:\r
1326\r
1327 EFI_SUCCESS Success\r
1328 EFI_TIMEOUT Timeout\r
4d1fe68e 1329\r
562d2849 1330--*/\r
1331;\r
1332\r
1333EFI_STATUS\r
1334WaitForPeriodicScheduleDisable (\r
1335 IN USB2_HC_DEV *HcDev,\r
1336 IN UINTN Timeout\r
1337 )\r
1338/*++\r
1339\r
1340Routine Description:\r
1341\r
1342 Wait for periodic schedule disable or timeout\r
4d1fe68e 1343\r
562d2849 1344Arguments:\r
1345\r
4d1fe68e 1346 HcDev - USB2_HC_DEV\r
562d2849 1347 Timeout - timeout threshold\r
4d1fe68e 1348\r
562d2849 1349Returns:\r
1350\r
1351 EFI_SUCCESS Success\r
1352 EFI_TIMEOUT Timeout\r
4d1fe68e 1353\r
562d2849 1354--*/\r
1355;\r
1356\r
1357EFI_STATUS\r
1358GetCapabilityLen (\r
1359 IN USB2_HC_DEV *HcDev\r
1360 )\r
1361/*++\r
1362\r
1363Routine Description:\r
1364\r
1365 Get the length of capability register\r
4d1fe68e 1366\r
562d2849 1367Arguments:\r
1368\r
4d1fe68e 1369 HcDev - USB2_HC_DEV\r
1370\r
562d2849 1371Returns:\r
1372\r
1373 EFI_SUCCESS Success\r
1374 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1375\r
562d2849 1376--*/\r
1377;\r
1378\r
1379EFI_STATUS\r
1380SetFrameListBaseAddr (\r
1381 IN USB2_HC_DEV *HcDev,\r
1382 IN UINT32 FrameBuffer\r
1383 )\r
1384/*++\r
1385\r
1386Routine Description:\r
1387\r
1388 Set base address of frame list first entry\r
4d1fe68e 1389\r
562d2849 1390Arguments:\r
1391\r
4d1fe68e 1392 HcDev - USB2_HC_DEV\r
562d2849 1393 FrameBuffer - base address of first entry of frame list\r
4d1fe68e 1394\r
562d2849 1395Returns:\r
1396\r
1397 EFI_SUCCESS Success\r
1398 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1399\r
562d2849 1400--*/\r
1401;\r
1402\r
1403EFI_STATUS\r
1404SetAsyncListAddr (\r
1405 IN USB2_HC_DEV *HcDev,\r
1406 IN EHCI_QH_ENTITY *QhPtr\r
1407 )\r
1408/*++\r
1409\r
1410Routine Description:\r
1411\r
1412 Set address of first Async schedule Qh\r
4d1fe68e 1413\r
562d2849 1414Arguments:\r
1415\r
4d1fe68e 1416 HcDev - USB2_HC_DEV\r
562d2849 1417 QhPtr - A pointer to first Qh in the Async schedule\r
4d1fe68e 1418\r
562d2849 1419Returns:\r
1420\r
1421 EFI_SUCCESS Success\r
1422 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1423\r
562d2849 1424--*/\r
1425;\r
1426\r
1427EFI_STATUS\r
1428SetCtrlDataStructSeg (\r
1429 IN USB2_HC_DEV *HcDev\r
1430 )\r
1431/*++\r
1432\r
1433Routine Description:\r
1434\r
1435 Set address of first Async schedule Qh\r
4d1fe68e 1436\r
562d2849 1437Arguments:\r
1438\r
4d1fe68e 1439 HcDev - USB2_HC_DEV\r
562d2849 1440 QhPtr - A pointer to first Qh in the Async schedule\r
4d1fe68e 1441\r
562d2849 1442Returns:\r
1443\r
1444 EFI_SUCCESS Success\r
1445 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1446\r
562d2849 1447--*/\r
1448;\r
1449\r
1450EFI_STATUS\r
1451SetPortRoutingEhc (\r
1452 IN USB2_HC_DEV *HcDev\r
1453 )\r
1454/*++\r
1455\r
1456Routine Description:\r
1457\r
1458 Set Ehc port routing bit\r
4d1fe68e 1459\r
562d2849 1460Arguments:\r
1461\r
4d1fe68e 1462 HcDev - USB2_HC_DEV\r
1463\r
562d2849 1464Returns:\r
1465\r
1466 EFI_SUCCESS Success\r
1467 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1468\r
562d2849 1469--*/\r
1470;\r
1471\r
1472EFI_STATUS\r
1473EnablePeriodicSchedule (\r
1474 IN USB2_HC_DEV *HcDev\r
1475 )\r
1476/*++\r
1477\r
1478Routine Description:\r
1479\r
1480 Enable periodic schedule\r
4d1fe68e 1481\r
562d2849 1482Arguments:\r
1483\r
4d1fe68e 1484 HcDev - USB2_HC_DEV\r
1485\r
562d2849 1486Returns:\r
1487\r
1488 EFI_SUCCESS Success\r
1489 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1490\r
562d2849 1491--*/\r
1492;\r
1493\r
1494EFI_STATUS\r
1495DisablePeriodicSchedule (\r
1496 IN USB2_HC_DEV *HcDev\r
1497 )\r
1498/*++\r
1499\r
1500Routine Description:\r
1501\r
1502 Disable periodic schedule\r
4d1fe68e 1503\r
562d2849 1504Arguments:\r
1505\r
4d1fe68e 1506 HcDev - USB2_HC_DEV\r
1507\r
562d2849 1508Returns:\r
1509\r
1510 EFI_SUCCESS Success\r
1511 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1512\r
562d2849 1513--*/\r
1514;\r
1515\r
1516EFI_STATUS\r
1517EnableAsynchronousSchedule (\r
1518 IN USB2_HC_DEV *HcDev\r
1519 )\r
1520/*++\r
1521\r
1522Routine Description:\r
1523\r
1524 Enable asynchrounous schedule\r
4d1fe68e 1525\r
562d2849 1526Arguments:\r
1527\r
4d1fe68e 1528 HcDev - USB2_HC_DEV\r
1529\r
562d2849 1530Returns:\r\r
1531\r
1532 EFI_SUCCESS Success\r
1533 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1534\r
562d2849 1535--*/\r
1536;\r
1537\r
1538EFI_STATUS\r
1539DisableAsynchronousSchedule (\r
1540 IN USB2_HC_DEV *HcDev\r
1541 )\r
1542/*++\r
1543\r
1544Routine Description:\r
1545\r
1546 Disable asynchrounous schedule\r
4d1fe68e 1547\r
562d2849 1548Arguments:\r
1549\r
4d1fe68e 1550 HcDev - USB2_HC_DEV\r
1551\r
562d2849 1552Returns:\r
1553\r
1554 EFI_SUCCESS Success\r
1555 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1556\r
562d2849 1557--*/\r
1558;\r
1559\r
1560EFI_STATUS\r
1561StartScheduleExecution (\r
1562 IN USB2_HC_DEV *HcDev\r
1563 )\r
1564/*++\r
1565\r
1566Routine Description:\r
1567\r
1568 Start Ehc schedule execution\r
4d1fe68e 1569\r
562d2849 1570Arguments:\r
1571\r
4d1fe68e 1572 HcDev - USB2_HC_DEV\r
1573\r
562d2849 1574Returns:\r
1575\r
1576 EFI_SUCCESS Success\r
1577 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1578\r
562d2849 1579--*/\r
1580;\r
1581\r
1582EFI_STATUS\r
1583ResetEhc (\r
1584 IN USB2_HC_DEV *HcDev\r
1585 )\r
1586/*++\r
1587\r
1588Routine Description:\r
1589\r
1590 Reset Ehc\r
4d1fe68e 1591\r
562d2849 1592Arguments:\r
1593\r
4d1fe68e 1594 HcDev - USB2_HC_DEV\r
1595\r
562d2849 1596Returns:\r
1597\r
1598 EFI_SUCCESS Success\r
1599 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1600\r
562d2849 1601--*/\r
1602;\r
1603\r
1604EFI_STATUS\r
1605ClearEhcAllStatus (\r
1606 IN USB2_HC_DEV *HcDev\r
1607 )\r
1608/*++\r
1609\r
1610Routine Description:\r
1611\r
1612 Clear Ehc all status bits\r
4d1fe68e 1613\r
562d2849 1614Arguments:\r
1615\r
4d1fe68e 1616 HcDev - USB2_HC_DEV\r
1617\r
562d2849 1618Returns:\r
1619\r
1620 EFI_SUCCESS Success\r
1621 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1622\r
562d2849 1623--*/\r
1624;\r
1625\r
1626//\r
1627// EhciSched Functions\r
1628//\r
1629EFI_STATUS\r
1630InitialPeriodicFrameList (\r
1631 IN USB2_HC_DEV *HcDev,\r
1632 IN UINTN Length\r
1633 )\r
1634/*++\r
1635\r
1636Routine Description:\r
1637\r
1638 Initialize Periodic Schedule Frame List\r
1639\r
1640Arguments:\r
1641\r
1642 HcDev - USB2_HC_DEV\r
1643 Length - Frame List Length\r
4d1fe68e 1644\r
562d2849 1645Returns:\r
1646\r
1647 EFI_SUCCESS Success\r
1648 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1649\r
562d2849 1650--*/\r
1651;\r
1652\r
1653VOID\r
1654DeinitialPeriodicFrameList (\r
1655 IN USB2_HC_DEV *HcDev\r
1656 )\r
1657/*++\r
1658\r
1659Routine Description:\r
1660\r
1661 Deinitialize Periodic Schedule Frame List\r
1662\r
1663Arguments:\r
1664\r
1665 HcDev - USB2_HC_DEV\r
1666\r
1667Returns:\r
1668\r
1669 VOID\r
4d1fe68e 1670\r
562d2849 1671--*/\r
1672;\r
1673\r
1674EFI_STATUS\r
1675CreatePollingTimer (\r
1676 IN USB2_HC_DEV *HcDev,\r
1677 IN EFI_EVENT_NOTIFY NotifyFunction\r
1678 )\r
1679/*++\r
1680\r
1681Routine Description:\r
1682\r
1683 Create Async Request Polling Timer\r
1684\r
1685Arguments:\r
1686\r
1687 HcDev - USB2_HC_DEV\r
1688 NotifyFunction - Timer Notify Function\r
4d1fe68e 1689\r
562d2849 1690Returns:\r
1691\r
1692 EFI_SUCCESS Success\r
1693 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1694\r
562d2849 1695--*/\r
1696;\r
1697\r
1698EFI_STATUS\r
1699DestoryPollingTimer (\r
1700 IN USB2_HC_DEV *HcDev\r
1701 )\r
1702/*++\r
1703\r
1704Routine Description:\r
1705\r
1706 Destory Async Request Polling Timer\r
1707\r
1708Arguments:\r
1709\r
1710 HcDev - USB2_HC_DEV\r
4d1fe68e 1711\r
562d2849 1712Returns:\r
1713\r
1714 EFI_SUCCESS Success\r
1715 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1716\r
562d2849 1717--*/\r
1718;\r
1719\r
1720EFI_STATUS\r
1721StartPollingTimer (\r
1722 IN USB2_HC_DEV *HcDev\r
1723 )\r
1724/*++\r
1725\r
1726Routine Description:\r
1727\r
1728 Start Async Request Polling Timer\r
1729\r
1730Arguments:\r
1731\r
1732 HcDev - USB2_HC_DEV\r
4d1fe68e 1733\r
562d2849 1734Returns:\r
1735\r
1736 EFI_SUCCESS Success\r
1737 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1738\r
562d2849 1739--*/\r
1740;\r
1741\r
1742EFI_STATUS\r
1743StopPollingTimer (\r
1744 IN USB2_HC_DEV *HcDev\r
1745 )\r
1746/*++\r
1747\r
1748Routine Description:\r
1749\r
1750 Stop Async Request Polling Timer\r
1751\r
1752Arguments:\r
1753\r
1754 HcDev - USB2_HC_DEV\r
4d1fe68e 1755\r
562d2849 1756Returns:\r
1757\r
1758 EFI_SUCCESS Success\r
1759 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1760\r
562d2849 1761--*/\r
1762;\r
1763\r
1764EFI_STATUS\r
1765CreateQh (\r
1766 IN USB2_HC_DEV *HcDev,\r
1767 IN UINT8 DeviceAddr,\r
1768 IN UINT8 Endpoint,\r
1769 IN UINT8 DeviceSpeed,\r
1770 IN UINTN MaxPacketLen,\r
1771 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1772 )\r
1773/*++\r
1774\r
1775Routine Description:\r
1776\r
1777 Create Qh Structure and Pre-Initialize\r
1778\r
1779Arguments:\r
1780\r
4d1fe68e 1781 HcDev - USB2_HC_DEV\r
562d2849 1782 DeviceAddr - Address of Device\r
1783 Endpoint - Endpoint Number\r
1784 DeviceSpeed - Device Speed\r
1785 MaxPacketLen - Max Length of one Packet\r
1786 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1787\r
562d2849 1788Returns:\r
1789\r
1790 EFI_SUCCESS Success\r
1791 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1792\r
562d2849 1793--*/\r
1794;\r
1795\r
1796EFI_STATUS\r
1797CreateControlQh (\r
1798 IN USB2_HC_DEV *HcDev,\r
1799 IN UINT8 DeviceAddr,\r
1800 IN UINT8 DeviceSpeed,\r
1801 IN UINTN MaxPacketLen,\r
1802 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1803 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1804 )\r
1805/*++\r
1806\r
1807Routine Description:\r
1808\r
1809 Create Qh for Control Transfer\r
1810\r
1811Arguments:\r
1812\r
4d1fe68e 1813 HcDev - USB2_HC_DEV\r
562d2849 1814 DeviceAddr - Address of Device\r
1815 DeviceSpeed - Device Speed\r
1816 MaxPacketLen - Max Length of one Packet\r
1817 Translator - Translator Transaction for SplitX\r
1818 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1819\r
562d2849 1820Returns:\r
1821\r
1822 EFI_SUCCESS Success\r
1823 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1824\r
562d2849 1825--*/\r
1826;\r
1827\r
1828EFI_STATUS\r
1829CreateBulkQh (\r
1830 IN USB2_HC_DEV *HcDev,\r
1831 IN UINT8 DeviceAddr,\r
1832 IN UINT8 EndPointAddr,\r
1833 IN UINT8 DeviceSpeed,\r
1834 IN UINT8 DataToggle,\r
1835 IN UINTN MaxPacketLen,\r
1836 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1837 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1838 )\r
1839/*++\r
1840\r
1841Routine Description:\r
1842\r
1843 Create Qh for Bulk Transfer\r
1844\r
1845Arguments:\r
1846\r
4d1fe68e 1847 HcDev - USB2_HC_DEV\r
562d2849 1848 DeviceAddr - Address of Device\r
1849 EndPointAddr - Address of Endpoint\r
1850 DeviceSpeed - Device Speed\r
1851 MaxPacketLen - Max Length of one Packet\r
1852 Translator - Translator Transaction for SplitX\r
1853 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1854\r
562d2849 1855Returns:\r
1856\r
1857 EFI_SUCCESS Success\r
1858 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1859\r
562d2849 1860--*/\r
1861;\r
1862\r
1863EFI_STATUS\r
1864CreateInterruptQh (\r
1865 IN USB2_HC_DEV *HcDev,\r
1866 IN UINT8 DeviceAddr,\r
1867 IN UINT8 EndPointAddr,\r
1868 IN UINT8 DeviceSpeed,\r
1869 IN UINT8 DataToggle,\r
1870 IN UINTN MaxPacketLen,\r
1871 IN UINTN Interval,\r
1872 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
1873 OUT EHCI_QH_ENTITY **QhPtrPtr\r
1874 )\r
1875/*++\r
1876\r
1877Routine Description:\r
1878\r
1879 Create Qh for Control Transfer\r
1880\r
1881Arguments:\r
1882\r
4d1fe68e 1883 HcDev - USB2_HC_DEV\r
562d2849 1884 DeviceAddr - Address of Device\r
1885 EndPointAddr - Address of Endpoint\r
1886 DeviceSpeed - Device Speed\r
1887 MaxPacketLen - Max Length of one Packet\r
1888 Interval - value of interval\r
1889 Translator - Translator Transaction for SplitX\r
1890 QhPtrPtr - A pointer of pointer to Qh for return\r
4d1fe68e 1891\r
562d2849 1892Returns:\r
1893\r
1894 EFI_SUCCESS Success\r
1895 EFI_DEVICE_ERROR Fail\r
4d1fe68e 1896\r
562d2849 1897--*/\r
1898;\r
1899\r
1900VOID\r
1901DestoryQh (\r
1902 IN USB2_HC_DEV *HcDev,\r
1903 IN EHCI_QH_ENTITY *QhPtr\r
1904 )\r
1905/*++\r
1906\r
1907Routine Description:\r
1908\r
4d1fe68e 1909 Destory Qh Structure\r
1910\r
562d2849 1911Arguments:\r
1912\r
4d1fe68e 1913 HcDev - USB2_HC_DEV\r
562d2849 1914 QhPtr - A pointer to Qh\r
4d1fe68e 1915\r
562d2849 1916Returns:\r
1917\r
1918 VOID\r
4d1fe68e 1919\r
562d2849 1920--*/\r
1921;\r
1922\r
1923EFI_STATUS\r
1924CreateQtd (\r
1925 IN USB2_HC_DEV *HcDev,\r
1926 IN UINT8 *DataPtr,\r
1927 IN UINTN DataLen,\r
1928 IN UINT8 PktId,\r
1929 IN UINT8 Toggle,\r
1930 IN UINT8 QtdStatus,\r
1931 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1932 )\r
1933/*++\r
1934\r
1935Routine Description:\r
1936\r
1937 Create Qtd Structure and Pre-Initialize it\r
1938\r
1939Arguments:\r
1940\r
4d1fe68e 1941 HcDev - USB2_HC_DEV\r
562d2849 1942 DataPtr - A pointer to user data buffer to transfer\r
1943 DataLen - Length of user data to transfer\r
1944 PktId - Packet Identification of this Qtd\r
1945 Toggle - Data Toggle of this Qtd\r
1946 QtdStatus - Default value of status of this Qtd\r
1947 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 1948\r
562d2849 1949Returns:\r
1950\r
1951 EFI_SUCCESS Success\r
1952 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 1953\r
562d2849 1954--*/\r
1955;\r
1956\r
1957EFI_STATUS\r
1958CreateSetupQtd (\r
1959 IN USB2_HC_DEV *HcDev,\r
1960 IN UINT8 *DevReqPtr,\r
1961 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1962 )\r
1963/*++\r
1964\r
1965Routine Description:\r
1966\r
4d1fe68e 1967 Create Qtd Structure for Setup\r
562d2849 1968\r
1969Arguments:\r
1970\r
4d1fe68e 1971 HcDev - USB2_HC_DEV\r
562d2849 1972 DevReqPtr - A pointer to Device Request Data\r
1973 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 1974\r
562d2849 1975Returns:\r
1976\r
1977 EFI_SUCCESS Success\r
1978 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 1979\r
562d2849 1980--*/\r
1981;\r
1982\r
1983EFI_STATUS\r
1984CreateDataQtd (\r
1985 IN USB2_HC_DEV *HcDev,\r
1986 IN UINT8 *DataPtr,\r
1987 IN UINTN DataLen,\r
1988 IN UINT8 PktId,\r
1989 IN UINT8 Toggle,\r
1990 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
1991 )\r
1992/*++\r
1993\r
1994Routine Description:\r
1995\r
4d1fe68e 1996 Create Qtd Structure for data\r
562d2849 1997\r
1998Arguments:\r
1999\r
4d1fe68e 2000 HcDev - USB2_HC_DEV\r
562d2849 2001 DataPtr - A pointer to user data buffer to transfer\r
2002 DataLen - Length of user data to transfer\r
2003 PktId - Packet Identification of this Qtd\r
2004 Toggle - Data Toggle of this Qtd\r
2005 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 2006\r
562d2849 2007Returns:\r
2008\r
2009 EFI_SUCCESS Success\r
2010 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 2011\r
562d2849 2012--*/\r
2013;\r
2014\r
2015EFI_STATUS\r
2016CreateStatusQtd (\r
2017 IN USB2_HC_DEV *HcDev,\r
2018 IN UINT8 PktId,\r
2019 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
2020 )\r
2021/*++\r
2022\r
2023Routine Description:\r
2024\r
4d1fe68e 2025 Create Qtd Structure for status\r
562d2849 2026\r
2027Arguments:\r
2028\r
4d1fe68e 2029 HcDev - USB2_HC_DEV\r
562d2849 2030 PktId - Packet Identification of this Qtd\r
2031 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 2032\r
562d2849 2033Returns:\r
2034\r
2035 EFI_SUCCESS Success\r
2036 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 2037\r
562d2849 2038--*/\r
2039;\r
2040\r
2041EFI_STATUS\r
2042CreateAltQtd (\r
2043 IN USB2_HC_DEV *HcDev,\r
2044 IN UINT8 PktId,\r
2045 OUT EHCI_QTD_ENTITY **QtdPtrPtr\r
2046 )\r
2047/*++\r
2048\r
2049Routine Description:\r
2050\r
4d1fe68e 2051 Create Qtd Structure for Alternative\r
562d2849 2052\r
2053Arguments:\r
2054\r
4d1fe68e 2055 HcDev - USB2_HC_DEV\r
562d2849 2056 PktId - Packet Identification of this Qtd\r
2057 QtdPtrPtr - A pointer of pointer to Qtd for return\r
4d1fe68e 2058\r
562d2849 2059Returns:\r
2060\r
2061 EFI_SUCCESS Success\r
2062 EFI_OUT_OF_RESOURCES Cannot allocate resources\r
4d1fe68e 2063\r
562d2849 2064--*/\r
2065;\r
2066\r
2067EFI_STATUS\r
2068CreateControlQtds (\r
2069 IN USB2_HC_DEV *HcDev,\r
2070 IN UINT8 DataPktId,\r
2071 IN UINT8 *RequestCursor,\r
2072 IN UINT8 *DataCursor,\r
2073 IN UINTN DataLen,\r
2074 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
2075 OUT EHCI_QTD_ENTITY **ControlQtdsHead\r
2076 )\r
2077/*++\r
2078\r
2079Routine Description:\r
2080\r
4d1fe68e 2081 Create Qtds list for Control Transfer\r
562d2849 2082\r
2083Arguments:\r
2084\r
4d1fe68e 2085 HcDev - USB2_HC_DEV\r
562d2849 2086 DataPktId - Packet Identification of Data Qtds\r
2087 RequestCursor - A pointer to request structure buffer to transfer\r
2088 DataCursor - A pointer to user data buffer to transfer\r
2089 DataLen - Length of user data to transfer\r
2090 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
4d1fe68e 2091\r
562d2849 2092Returns:\r
2093\r
2094 EFI_SUCCESS Success\r
2095 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2096\r
562d2849 2097--*/\r
2098;\r
2099\r
2100EFI_STATUS\r
2101CreateBulkOrInterruptQtds (\r
2102 IN USB2_HC_DEV *HcDev,\r
2103 IN UINT8 PktId,\r
2104 IN UINT8 *DataCursor,\r
2105 IN UINTN DataLen,\r
2106 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r
2107 OUT EHCI_QTD_ENTITY **QtdsHead\r
2108 )\r
2109/*++\r
2110\r
2111Routine Description:\r
2112\r
4d1fe68e 2113 Create Qtds list for Bulk or Interrupt Transfer\r
562d2849 2114\r
2115Arguments:\r
2116\r
4d1fe68e 2117 HcDev - USB2_HC_DEV\r
562d2849 2118 PktId - Packet Identification of Qtds\r
2119 DataCursor - A pointer to user data buffer to transfer\r
2120 DataLen - Length of user data to transfer\r
2121 DataToggle - Data Toggle to start\r
2122 Translator - Translator Transaction for SplitX\r
2123 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return\r
4d1fe68e 2124\r
562d2849 2125Returns:\r
2126\r
2127 EFI_SUCCESS Success\r
2128 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2129\r
562d2849 2130--*/\r
2131;\r
2132\r
2133VOID\r
2134DestoryQtds (\r
2135 IN USB2_HC_DEV *HcDev,\r
2136 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2137 )\r
2138/*++\r
2139\r
2140Routine Description:\r
2141\r
2142 Destory all Qtds in the list\r
2143\r
2144Arguments:\r
2145\r
4d1fe68e 2146 HcDev - USB2_HC_DEV\r
2147 FirstQtdPtr - A pointer to first Qtd in the list\r
2148\r
562d2849 2149Returns:\r
2150\r
2151 VOID\r
2152\r
2153--*/\r
2154;\r
2155\r
2156VOID\r
2157LinkQtdToQtd (\r
2158 IN EHCI_QTD_ENTITY *PreQtdPtr,\r
2159 IN EHCI_QTD_ENTITY *QtdPtr\r
2160 )\r
2161/*++\r
2162\r
2163Routine Description:\r
2164\r
2165 Link Qtds together\r
4d1fe68e 2166\r
562d2849 2167Arguments:\r
2168\r
2169 PreQtdPtr - A pointer to pre Qtd\r
2170 QtdPtr - A pointer to next Qtd\r
4d1fe68e 2171\r
562d2849 2172Returns:\r
2173\r
2174 VOID\r
2175\r
2176--*/\r
2177;\r
2178\r
2179VOID\r
2180LinkQtdsToAltQtd (\r
2181 IN EHCI_QTD_ENTITY *FirstQtdPtr,\r
2182 IN EHCI_QTD_ENTITY *AltQtdPtr\r
2183 )\r
2184/*++\r
2185\r
2186Routine Description:\r
2187\r
2188 Link AlterQtds together\r
4d1fe68e 2189\r
562d2849 2190Arguments:\r
2191\r
2192 FirstQtdPtr - A pointer to first Qtd in the list\r
2193 AltQtdPtr - A pointer to alternative Qtd\r
4d1fe68e 2194\r
562d2849 2195Returns:\r
2196 VOID\r
2197\r
2198--*/\r
2199;\r
2200\r
2201VOID\r
2202LinkQtdToQh (\r
2203 IN EHCI_QH_ENTITY *QhPtr,\r
2204 IN EHCI_QTD_ENTITY *QtdEntryPtr\r
2205 )\r
2206/*++\r
2207\r
2208Routine Description:\r
2209\r
2210 Link Qtds list to Qh\r
4d1fe68e 2211\r
562d2849 2212Arguments:\r
2213\r
2214 QhPtr - A pointer to Qh\r
2215 QtdPtr - A pointer to first Qtd in the list\r
4d1fe68e 2216\r
562d2849 2217Returns:\r
2218\r
2219 VOID\r
2220\r
2221--*/\r
2222;\r
2223\r
2224EFI_STATUS\r
2225LinkQhToAsyncList (\r
2226 IN USB2_HC_DEV *HcDev,\r
2227 IN EHCI_QH_ENTITY *QhPtr\r
2228 )\r
2229/*++\r
2230\r
2231Routine Description:\r
2232\r
2233 Link Qh to Async Schedule List\r
4d1fe68e 2234\r
562d2849 2235Arguments:\r
2236\r
4d1fe68e 2237 HcDev - USB2_HC_DEV\r
562d2849 2238 QhPtr - A pointer to Qh\r
4d1fe68e 2239\r
562d2849 2240Returns:\r
2241\r
2242 EFI_SUCCESS Success\r
2243 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2244\r
562d2849 2245--*/\r
2246;\r
2247\r
2248EFI_STATUS\r
2249UnlinkQhFromAsyncList (\r
2250 IN USB2_HC_DEV *HcDev,\r
2251 IN EHCI_QH_ENTITY *QhPtr\r
2252 )\r
2253/*++\r
2254\r
2255Routine Description:\r
2256\r
2257 Unlink Qh from Async Schedule List\r
4d1fe68e 2258\r
562d2849 2259Arguments:\r
2260\r
4d1fe68e 2261 HcDev - USB2_HC_DEV\r
562d2849 2262 QhPtr - A pointer to Qh\r
4d1fe68e 2263\r
562d2849 2264Returns:\r
2265\r
2266 EFI_SUCCESS Success\r
2267 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2268\r
562d2849 2269--*/\r
2270;\r
2271\r
2272VOID\r
2273LinkQhToPeriodicList (\r
2274 IN USB2_HC_DEV *HcDev,\r
2275 IN EHCI_QH_ENTITY *QhPtr\r
2276 )\r
2277/*++\r
2278\r
2279Routine Description:\r
2280\r
2281 Link Qh to Periodic Schedule List\r
4d1fe68e 2282\r
562d2849 2283Arguments:\r
2284\r
4d1fe68e 2285 HcDev - USB2_HC_DEV\r
562d2849 2286 QhPtr - A pointer to Qh\r
4d1fe68e 2287\r
562d2849 2288Returns:\r
2289\r
2290 VOID\r
2291\r
2292--*/\r
2293;\r
2294\r
2295VOID\r
2296UnlinkQhFromPeriodicList (\r
2297 IN USB2_HC_DEV *HcDev,\r
2298 IN EHCI_QH_ENTITY *QhPtr,\r
2299 IN UINTN Interval\r
2300 )\r
2301/*++\r
2302\r
2303Routine Description:\r
2304\r
2305 Unlink Qh from Periodic Schedule List\r
4d1fe68e 2306\r
562d2849 2307Arguments:\r
2308\r
4d1fe68e 2309 HcDev - USB2_HC_DEV\r
562d2849 2310 QhPtr - A pointer to Qh\r
2311 Interval - Interval of this periodic transfer\r
4d1fe68e 2312\r
562d2849 2313Returns:\r
2314\r
2315 VOID\r
4d1fe68e 2316\r
562d2849 2317--*/\r
2318;\r
2319\r
2320VOID\r
2321LinkToAsyncReqeust (\r
2322 IN USB2_HC_DEV *HcDev,\r
2323 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2324 )\r
2325/*++\r
2326\r
2327Routine Description:\r
2328\r
2329 Llink AsyncRequest Entry to Async Request List\r
4d1fe68e 2330\r
562d2849 2331Arguments:\r
2332\r
4d1fe68e 2333 HcDev - USB2_HC_DEV\r
562d2849 2334 AsyncRequestPtr - A pointer to Async Request Entry\r
4d1fe68e 2335\r
562d2849 2336Returns:\r
2337\r
2338 VOID\r
4d1fe68e 2339\r
562d2849 2340--*/\r
2341;\r
2342\r
2343VOID\r
2344UnlinkFromAsyncReqeust (\r
2345 IN USB2_HC_DEV *HcDev,\r
2346 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr\r
2347 )\r
2348/*++\r
2349\r
2350Routine Description:\r
2351\r
2352 Unlink AsyncRequest Entry from Async Request List\r
4d1fe68e 2353\r
562d2849 2354Arguments:\r
2355\r
4d1fe68e 2356 HcDev - USB2_HC_DEV\r
562d2849 2357 AsyncRequestPtr - A pointer to Async Request Entry\r
4d1fe68e 2358\r
562d2849 2359Returns:\r
2360\r
2361 VOID\r
4d1fe68e 2362\r
562d2849 2363--*/\r
2364;\r
2365\r
2366UINTN\r
2367GetNumberOfQtd (\r
2368 IN EHCI_QTD_ENTITY *FirstQtdPtr\r
2369 )\r
2370/*++\r
2371\r
2372Routine Description:\r
2373\r
2374 Number of Qtds in the list\r
4d1fe68e 2375\r
562d2849 2376Arguments:\r
2377\r
2378 FirstQtdPtr - A pointer to first Qtd in the list\r
4d1fe68e 2379\r
562d2849 2380Returns:\r
2381\r
2382 Number of Qtds in the list\r
2383\r
2384--*/\r
2385;\r
2386\r
562d2849 2387\r
562d2849 2388\r
2389UINTN\r
2390GetCapacityOfQtd (\r
2391 IN UINT8 *BufferCursor\r
2392 )\r
2393/*++\r
2394\r
2395Routine Description:\r
2396\r
2397 Get Capacity of Qtd\r
4d1fe68e 2398\r
562d2849 2399Arguments:\r
2400\r
2401 BufferCursor - BufferCursor of the Qtd\r
4d1fe68e 2402\r
562d2849 2403Returns:\r
2404\r
2405 Capacity of Qtd\r
2406\r
2407--*/\r
2408;\r
2409\r
2410UINTN\r
2411GetApproxiOfInterval (\r
2412 IN UINTN Interval\r
2413 )\r
2414/*++\r
2415\r
2416Routine Description:\r
2417\r
2418 Get the approximate value in the 2 index sequence\r
4d1fe68e 2419\r
562d2849 2420Arguments:\r
2421\r
2422 Interval - the value of interval\r
4d1fe68e 2423\r
562d2849 2424Returns:\r
2425\r
2426 approximate value of interval in the 2 index sequence\r
4d1fe68e 2427\r
562d2849 2428--*/\r
2429;\r
2430\r
2431EHCI_QTD_HW *\r
2432GetQtdNextPointer (\r
2433 IN EHCI_QTD_HW *HwQtdPtr\r
2434 )\r
2435/*++\r
2436\r
2437Routine Description:\r
2438\r
2439 Get Qtd next pointer field\r
4d1fe68e 2440\r
562d2849 2441Arguments:\r
2442\r
2443 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2444\r
562d2849 2445Returns:\r
2446\r
2447 A pointer to next hardware Qtd structure\r
4d1fe68e 2448\r
562d2849 2449--*/\r
2450;\r
2451\r
2452BOOLEAN\r
2453IsQtdStatusActive (\r
2454 IN EHCI_QTD_HW *HwQtdPtr\r
2455 )\r
2456/*++\r
2457\r
2458Routine Description:\r
2459\r
2460 Whether Qtd status is active or not\r
4d1fe68e 2461\r
562d2849 2462Arguments:\r
2463\r
2464 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2465\r
562d2849 2466Returns:\r
2467\r
2468 TRUE Active\r
2469 FALSE Inactive\r
4d1fe68e 2470\r
562d2849 2471--*/\r
2472;\r
2473\r
2474BOOLEAN\r
2475IsQtdStatusHalted (\r
2476 IN EHCI_QTD_HW *HwQtdPtr\r
2477 )\r
2478/*++\r
2479\r
2480Routine Description:\r
2481\r
2482 Whether Qtd status is halted or not\r
4d1fe68e 2483\r
562d2849 2484Arguments:\r
2485\r
2486 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2487\r
562d2849 2488Returns:\r\r
2489\r
2490 TRUE Halted\r
2491 FALSE Not halted\r
4d1fe68e 2492\r
562d2849 2493--*/\r
2494;\r
2495\r
2496BOOLEAN\r
2497IsQtdStatusBufferError (\r
2498 IN EHCI_QTD_HW *HwQtdPtr\r
2499 )\r
2500/*++\r
2501\r
2502Routine Description:\r
2503\r
2504 Whether Qtd status is buffer error or not\r
4d1fe68e 2505\r
562d2849 2506Arguments:\r
2507\r
2508 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2509\r
562d2849 2510Returns:\r
2511\r
2512 TRUE Buffer error\r
2513 FALSE No buffer error\r
4d1fe68e 2514\r
562d2849 2515--*/\r
2516;\r
2517\r
2518BOOLEAN\r
2519IsQtdStatusBabbleError (\r
2520 IN EHCI_QTD_HW *HwQtdPtr\r
2521 )\r
2522/*++\r
2523\r
2524Routine Description:\r
2525\r
2526 Whether Qtd status is babble error or not\r
4d1fe68e 2527\r
562d2849 2528Arguments:\r
2529\r
2530 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2531\r
562d2849 2532Returns:\r
2533\r
2534 TRUE Babble error\r
2535 FALSE No babble error\r
4d1fe68e 2536\r
562d2849 2537--*/\r
2538;\r
2539\r
2540BOOLEAN\r
2541IsQtdStatusTransactionError (\r
2542 IN EHCI_QTD_HW *HwQtdPtr\r
2543 )\r
2544/*++\r
2545\r
2546Routine Description:\r
2547\r
2548 Whether Qtd status is transaction error or not\r
4d1fe68e 2549\r
562d2849 2550Arguments:\r
2551\r
2552 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2553\r
562d2849 2554Returns:\r
2555\r
2556 TRUE Transaction error\r
2557 FALSE No transaction error\r
4d1fe68e 2558\r
562d2849 2559--*/\r
2560;\r
2561\r
2562BOOLEAN\r
2563IsDataInTransfer (\r
2564 IN UINT8 EndPointAddress\r
2565 )\r
2566/*++\r
2567\r
2568Routine Description:\r
2569\r
2570 Whether is a DataIn direction transfer\r
4d1fe68e 2571\r
562d2849 2572Arguments:\r
2573\r
4d1fe68e 2574 EndPointAddress - address of the endpoint\r
2575\r
562d2849 2576Returns:\r
2577\r
2578 TRUE DataIn\r
2579 FALSE DataOut\r
4d1fe68e 2580\r
562d2849 2581--*/\r
2582;\r
2583\r
2584EFI_STATUS\r
2585MapDataBuffer (\r
2586 IN USB2_HC_DEV *HcDev,\r
2587 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
2588 IN OUT VOID *Data,\r
2589 IN OUT UINTN *DataLength,\r
2590 OUT UINT8 *PktId,\r
2591 OUT UINT8 **DataCursor,\r
2592 OUT VOID **DataMap\r
2593 )\r
2594/*++\r
2595\r
2596Routine Description:\r
2597\r
2598 Map address of user data buffer\r
4d1fe68e 2599\r
562d2849 2600Arguments:\r
2601\r
4d1fe68e 2602 HcDev - USB2_HC_DEV\r
562d2849 2603 TransferDirection - direction of transfer\r
4d1fe68e 2604 Data - A pointer to user data buffer\r
562d2849 2605 DataLength - length of user data\r
2606 PktId - Packte Identificaion\r
2607 DataCursor - mapped address to return\r
2608 DataMap - identificaion of this mapping to return\r
4d1fe68e 2609\r
562d2849 2610Returns:\r
2611\r
2612 EFI_SUCCESS Success\r
2613 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2614\r
562d2849 2615--*/\r
2616;\r
2617\r
2618EFI_STATUS\r
2619MapRequestBuffer (\r
2620 IN USB2_HC_DEV *HcDev,\r
2621 IN OUT VOID *Request,\r
2622 OUT UINT8 **RequestCursor,\r
2623 OUT VOID **RequestMap\r
2624 )\r
2625/*++\r
2626\r
2627Routine Description:\r
2628\r
2629 Map address of request structure buffer\r
4d1fe68e 2630\r
562d2849 2631Arguments:\r
2632\r
4d1fe68e 2633 HcDev - USB2_HC_DEV\r
562d2849 2634 Request - A pointer to request structure\r
2635 RequestCursor - Mapped address of request structure to return\r
2636 RequestMap - Identificaion of this mapping to return\r
4d1fe68e 2637\r
562d2849 2638Returns:\r
2639\r
2640 EFI_SUCCESS Success\r
2641 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2642\r
562d2849 2643--*/\r
2644;\r
2645\r
2646VOID\r
2647SetQtdBufferPointer (\r
2648 IN EHCI_QTD_HW *QtdHwPtr,\r
2649 IN VOID *DataPtr,\r
2650 IN UINTN DataLen\r
2651 )\r
2652/*++\r
2653\r
2654Routine Description:\r
2655\r
2656 Set data buffer pointers in Qtd\r
2657\r
2658Arguments:\r
2659\r
4d1fe68e 2660 QtdHwPtr - A pointer to Qtd hardware structure\r
562d2849 2661 DataPtr - A pointer to user data buffer\r
2662 DataLen - Length of the user data buffer\r
4d1fe68e 2663\r
562d2849 2664Returns:\r
2665\r
2666 VOID\r
2667\r
2668--*/\r
2669;\r
2670\r
2671EHCI_QTD_HW *\r
2672GetQtdAlternateNextPointer (\r
2673 IN EHCI_QTD_HW *HwQtdPtr\r
2674 )\r
2675/*++\r
2676\r
2677Routine Description:\r
2678\r
2679 Get Qtd alternate next pointer field\r
4d1fe68e 2680\r
562d2849 2681Arguments:\r
2682\r
2683 HwQtdPtr - A pointer to hardware Qtd structure\r
4d1fe68e 2684\r
562d2849 2685Returns:\r
2686\r
2687 A pointer to hardware alternate Qtd\r
4d1fe68e 2688\r
562d2849 2689--*/\r
2690;\r
2691\r
2692VOID\r
2693ZeroOutQhOverlay (\r
2694 IN EHCI_QH_ENTITY *QhPtr\r
2695 )\r
2696/*++\r
2697\r
2698Routine Description:\r
2699\r
2700 Zero out the fields in Qh structure\r
4d1fe68e 2701\r
562d2849 2702Arguments:\r
2703\r
2704 QhPtr - A pointer to Qh structure\r
4d1fe68e 2705\r
562d2849 2706Returns:\r
2707\r
2708 VOID\r
4d1fe68e 2709\r
562d2849 2710--*/\r
2711;\r
2712\r
2713VOID\r
2714UpdateAsyncRequestTransfer (\r
2715 IN EHCI_ASYNC_REQUEST *AsyncRequestPtr,\r
2716 IN UINT32 TransferResult,\r
2717 IN UINTN ErrTDPos\r
2718 )\r
2719/*++\r
2720\r
2721Routine Description:\r
2722\r
2723 Update asynchronous request transfer\r
4d1fe68e 2724\r
562d2849 2725Arguments:\r
2726\r
4d1fe68e 2727 AsyncRequestPtr - A pointer to async request\r
2728 TransferResult - transfer result\r
562d2849 2729 ErrQtdPos - postion of error Qtd\r
4d1fe68e 2730\r
562d2849 2731Returns:\r
2732\r
2733 VOID\r
4d1fe68e 2734\r
562d2849 2735--*/\r
2736;\r
2737\r
2738\r
2739EFI_STATUS\r
2740DeleteAsyncRequestTransfer (\r
2741 IN USB2_HC_DEV *HcDev,\r
2742 IN UINT8 DeviceAddress,\r
2743 IN UINT8 EndPointAddress,\r
2744 OUT UINT8 *DataToggle\r
2745 )\r
2746/*++\r
2747\r
2748Routine Description:\r
2749\r
2750 Delete all asynchronous request transfer\r
4d1fe68e 2751\r
562d2849 2752Arguments:\r
2753\r
4d1fe68e 2754 HcDev - USB2_HC_DEV\r
562d2849 2755 DeviceAddress - address of usb device\r
2756 EndPointAddress - address of endpoint\r
2757 DataToggle - stored data toggle\r
4d1fe68e 2758\r
562d2849 2759Returns:\r
2760\r
2761 EFI_SUCCESS Success\r
2762 EFI_DEVICE_ERROR Fail\r
2763\r
2764--*/\r
2765;\r
2766\r
2767VOID\r
2768CleanUpAllAsyncRequestTransfer (\r
2769 IN USB2_HC_DEV *HcDev\r
2770 )\r
2771/*++\r
2772\r
2773Routine Description:\r
2774\r
2775 Clean up all asynchronous request transfer\r
4d1fe68e 2776\r
562d2849 2777Arguments:\r
2778\r
4d1fe68e 2779 HcDev - USB2_HC_DEV\r
2780\r
562d2849 2781Returns:\r
2782 VOID\r
4d1fe68e 2783\r
562d2849 2784--*/\r
2785;\r
2786\r
2787EFI_STATUS\r
2788ExecuteTransfer (\r
2789 IN USB2_HC_DEV *HcDev,\r
2790 IN BOOLEAN IsControl,\r
2791 IN EHCI_QH_ENTITY *QhPtr,\r
2792 IN OUT UINTN *ActualLen,\r
2793 OUT UINT8 *DataToggle,\r
2794 IN UINTN TimeOut,\r
2795 OUT UINT32 *TransferResult\r
2796 )\r
2797/*++\r
2798\r
2799Routine Description:\r
2800\r
2801 Execute Bulk or SyncInterrupt Transfer\r
2802\r
2803Arguments:\r
2804\r
2805 HcDev - USB2_HC_DEV\r
2806 IsControl - Is control transfer or not\r
2807 QhPtr - A pointer to Qh\r
4d1fe68e 2808 ActualLen - Actual transfered Len\r
562d2849 2809 DataToggle - Data Toggle\r
2810 TimeOut - TimeOut threshold\r
2811 TransferResult - Transfer result\r
4d1fe68e 2812\r
562d2849 2813Returns:\r
2814\r
2815 EFI_SUCCESS Sucess\r
2816 EFI_DEVICE_ERROR Error\r
4d1fe68e 2817\r
562d2849 2818--*/\r
2819;\r
2820\r
2821BOOLEAN\r
2822CheckQtdsTransferResult (\r
2823 IN BOOLEAN IsControl,\r
2824 IN EHCI_QH_ENTITY *QhPtr,\r
2825 OUT UINT32 *Result,\r
2826 OUT UINTN *ErrQtdPos,\r
2827 OUT UINTN *ActualLen\r
2828 )\r
2829/*++\r
2830\r
2831Routine Description:\r
2832\r
2833 Check transfer result of Qtds\r
2834\r
2835Arguments:\r
2836\r
2837 IsControl - Is control transfer or not\r
2838 QhPtr - A pointer to Qh\r
2839 Result - Transfer result\r
2840 ErrQtdPos - Error TD Position\r
2841 ActualLen - Actual Transfer Size\r
2842\r
2843Returns:\r
2844\r
2845 TRUE Qtds finished\r
2846 FALSE Not finish\r
4d1fe68e 2847\r
562d2849 2848--*/\r
2849;\r
2850\r
2851EFI_STATUS\r
2852AsyncRequestMoniter (\r
2853 IN EFI_EVENT Event,\r
2854 IN VOID *Context\r
2855 )\r
2856/*++\r
2857\r
2858Routine Description:\r
4d1fe68e 2859\r
562d2849 2860 Interrupt transfer periodic check handler\r
4d1fe68e 2861\r
562d2849 2862Arguments:\r
2863\r
2864 Event - Interrupt event\r
2865 Context - Pointer to USB2_HC_DEV\r
4d1fe68e 2866\r
562d2849 2867Returns:\r
4d1fe68e 2868\r
562d2849 2869 EFI_SUCCESS Success\r
2870 EFI_DEVICE_ERROR Fail\r
4d1fe68e 2871\r
2872--*/\r
2873;\r
2874\r
2875\r
2876EFI_STATUS\r
2877CreateNULLQH (\r
2878 IN USB2_HC_DEV *HcDev\r
2879 )\r
2880/*++\r
2881\r
2882Routine Description:\r
2883\r
2884 Create the NULL QH to make it as the Async QH header\r
2885\r
2886Arguments:\r
2887\r
2888 HcDev - USB2_HC_DEV\r
2889\r
2890Returns:\r
2891\r
2892 EFI_SUCCESS Success\r
562d2849 2893--*/\r
2894;\r
2895\r
4d1fe68e 2896VOID\r
2897DestroyNULLQH (\r
2898 IN USB2_HC_DEV *HcDev\r
2899 );\r
2900\r
74c56167 2901VOID\r
2902ClearLegacySupport (\r
2903 IN USB2_HC_DEV *HcDev\r
2904 );\r
2905\r
2906VOID\r
2907HostReset (\r
2908 IN USB2_HC_DEV *HcDev\r
2909 );\r
2910\r
4d1fe68e 2911\r
2912VOID\r
74c56167 2913DumpEHCIPortsStatus (\r
2914 IN USB2_HC_DEV *HcDev\r
2915 );\r
4d1fe68e 2916\r
2917\r
562d2849 2918#endif\r
EFI Development Kit II mirror for PVE