| 878ddf1f |
1 | /*++\r |
| 2 | Copyright (c) 2006, Intel Corporation \r |
| 3 | All rights reserved. This program and the accompanying materials \r |
| 4 | are licensed and made available under the terms and conditions of the BSD License \r |
| 5 | which accompanies this distribution. The full text of the license may be found at \r |
| 6 | http://opensource.org/licenses/bsd-license.php \r |
| 7 | \r |
| 8 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 9 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 10 | \r |
| 11 | Module Name:\r |
| 12 | \r |
| 13 | idedata.h\r |
| 14 | \r |
| 15 | Abstract:\r |
| 16 | \r |
| 17 | Header file for IDE Bus Driver's Data Structures\r |
| 18 | \r |
| 19 | Revision History\r |
| 20 | ++*/\r |
| 21 | \r |
| 22 | // TODO: fix comment to end with --*/\r |
| 23 | #ifndef _IDE_DATA_H\r |
| 24 | #define _IDE_DATA_H\r |
| 25 | \r |
| 26 | //\r |
| 27 | // bit definition\r |
| 28 | //\r |
| 29 | #define bit0 (1 << 0)\r |
| 30 | #define bit1 (1 << 1)\r |
| 31 | #define bit2 (1 << 2)\r |
| 32 | #define bit3 (1 << 3)\r |
| 33 | #define bit4 (1 << 4)\r |
| 34 | #define bit5 (1 << 5)\r |
| 35 | #define bit6 (1 << 6)\r |
| 36 | #define bit7 (1 << 7)\r |
| 37 | #define bit8 (1 << 8)\r |
| 38 | #define bit9 (1 << 9)\r |
| 39 | #define bit10 (1 << 10)\r |
| 40 | #define bit11 (1 << 11)\r |
| 41 | #define bit12 (1 << 12)\r |
| 42 | #define bit13 (1 << 13)\r |
| 43 | #define bit14 (1 << 14)\r |
| 44 | #define bit15 (1 << 15)\r |
| 45 | #define bit16 (1 << 16)\r |
| 46 | #define bit17 (1 << 17)\r |
| 47 | #define bit18 (1 << 18)\r |
| 48 | #define bit19 (1 << 19)\r |
| 49 | #define bit20 (1 << 20)\r |
| 50 | #define bit21 (1 << 21)\r |
| 51 | #define bit22 (1 << 22)\r |
| 52 | #define bit23 (1 << 23)\r |
| 53 | #define bit24 (1 << 24)\r |
| 54 | #define bit25 (1 << 25)\r |
| 55 | #define bit26 (1 << 26)\r |
| 56 | #define bit27 (1 << 27)\r |
| 57 | #define bit28 (1 << 28)\r |
| 58 | #define bit29 (1 << 29)\r |
| 59 | #define bit30 (1 << 30)\r |
| 60 | #define bit31 (1 << 31)\r |
| 61 | \r |
| 62 | //\r |
| 63 | // common constants\r |
| 64 | //\r |
| 65 | #define STALL_1_MILLI_SECOND 1000 // stall 1 ms\r |
| 66 | #define STALL_1_SECOND 1000000 // stall 1 second\r |
| 67 | typedef enum {\r |
| 68 | IdePrimary = 0,\r |
| 69 | IdeSecondary = 1,\r |
| 70 | IdeMaxChannel = 2\r |
| 71 | } EFI_IDE_CHANNEL;\r |
| 72 | \r |
| 73 | typedef enum {\r |
| 74 | IdeMaster = 0,\r |
| 75 | IdeSlave = 1,\r |
| 76 | IdeMaxDevice = 2\r |
| 77 | } EFI_IDE_DEVICE;\r |
| 78 | \r |
| 79 | typedef enum {\r |
| 80 | IdeMagnetic, /* ZIP Drive or LS120 Floppy Drive */\r |
| 81 | IdeCdRom, /* ATAPI CDROM */\r |
| 82 | IdeHardDisk, /* Hard Disk */\r |
| 83 | Ide48bitAddressingHardDisk, /* Hard Disk larger than 120GB */\r |
| 84 | IdeUnknown\r |
| 85 | } IDE_DEVICE_TYPE;\r |
| 86 | \r |
| 87 | //\r |
| 88 | // IDE Registers\r |
| 89 | //\r |
| 90 | typedef union {\r |
| 91 | UINT16 Command; /* when write */\r |
| 92 | UINT16 Status; /* when read */\r |
| 93 | } IDE_CMD_OR_STATUS;\r |
| 94 | \r |
| 95 | typedef union {\r |
| 96 | UINT16 Error; /* when read */\r |
| 97 | UINT16 Feature; /* when write */\r |
| 98 | } IDE_ERROR_OR_FEATURE;\r |
| 99 | \r |
| 100 | typedef union {\r |
| 101 | UINT16 AltStatus; /* when read */\r |
| 102 | UINT16 DeviceControl; /* when write */\r |
| 103 | } IDE_AltStatus_OR_DeviceControl;\r |
| 104 | \r |
| 105 | //\r |
| 106 | // IDE registers set\r |
| 107 | //\r |
| 108 | typedef struct {\r |
| 109 | UINT16 Data;\r |
| 110 | IDE_ERROR_OR_FEATURE Reg1;\r |
| 111 | UINT16 SectorCount;\r |
| 112 | UINT16 SectorNumber;\r |
| 113 | UINT16 CylinderLsb;\r |
| 114 | UINT16 CylinderMsb;\r |
| 115 | UINT16 Head;\r |
| 116 | IDE_CMD_OR_STATUS Reg;\r |
| 117 | \r |
| 118 | IDE_AltStatus_OR_DeviceControl Alt;\r |
| 119 | UINT16 DriveAddress;\r |
| 120 | \r |
| 121 | UINT16 MasterSlave;\r |
| 122 | UINT16 BusMasterBaseAddr;\r |
| 123 | } IDE_BASE_REGISTERS;\r |
| 124 | \r |
| 125 | //\r |
| 126 | // IDE registers' base addresses\r |
| 127 | //\r |
| 128 | typedef struct {\r |
| 129 | UINT16 CommandBlockBaseAddr;\r |
| 130 | UINT16 ControlBlockBaseAddr;\r |
| 131 | UINT16 BusMasterBaseAddr;\r |
| 132 | } IDE_REGISTERS_BASE_ADDR;\r |
| 133 | \r |
| 134 | //\r |
| 135 | // Bit definitions in Programming Interface byte of the Class Code field\r |
| 136 | // in PCI IDE controller's Configuration Space\r |
| 137 | //\r |
| 138 | #define IDE_PRIMARY_OPERATING_MODE bit0\r |
| 139 | #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1\r |
| 140 | #define IDE_SECONDARY_OPERATING_MODE bit2\r |
| 141 | #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3\r |
| 142 | \r |
| 143 | //\r |
| 144 | // IDE registers bit definitions\r |
| 145 | //\r |
| 146 | \r |
| 147 | //\r |
| 148 | // Err Reg\r |
| 149 | //\r |
| 150 | #define BBK_ERR bit7 /* Bad block detected */\r |
| 151 | #define UNC_ERR bit6 /* Uncorrectable Data */\r |
| 152 | #define MC_ERR bit5 /* Media Change */\r |
| 153 | #define IDNF_ERR bit4 /* ID Not Found */\r |
| 154 | #define MCR_ERR bit3 /* Media Change Requested */\r |
| 155 | #define ABRT_ERR bit2 /* Aborted Command */\r |
| 156 | #define TK0NF_ERR bit1 /* Track 0 Not Found */\r |
| 157 | #define AMNF_ERR bit0 /* Address Mark Not Found */\r |
| 158 | \r |
| 159 | //\r |
| 160 | // Device/Head Reg\r |
| 161 | //\r |
| 162 | #define LBA_MODE bit6\r |
| 163 | #define DEV bit4\r |
| 164 | #define HS3 bit3\r |
| 165 | #define HS2 bit2\r |
| 166 | #define HS1 bit1\r |
| 167 | #define HS0 bit0\r |
| 168 | #define CHS_MODE (0)\r |
| 169 | #define DRV0 (0)\r |
| 170 | #define DRV1 (1)\r |
| 171 | #define MST_DRV DRV0\r |
| 172 | #define SLV_DRV DRV1\r |
| 173 | \r |
| 174 | //\r |
| 175 | // Status Reg\r |
| 176 | //\r |
| 177 | #define BSY bit7 /* Controller Busy */\r |
| 178 | #define DRDY bit6 /* Drive Ready */\r |
| 179 | #define DWF bit5 /* Drive Write Fault */\r |
| 180 | #define DSC bit4 /* Disk Seek Complete */\r |
| 181 | #define DRQ bit3 /* Data Request */\r |
| 182 | #define CORR bit2 /* Corrected Data */\r |
| 183 | #define IDX bit1 /* Index */\r |
| 184 | #define ERR bit0 /* Error */\r |
| 185 | \r |
| 186 | //\r |
| 187 | // Device Control Reg\r |
| 188 | //\r |
| 189 | #define SRST bit2 /* Software Reset */\r |
| 190 | #define IEN_L bit1 /* Interrupt Enable #*/\r |
| 191 | \r |
| 192 | //\r |
| 193 | // Bus Master Reg\r |
| 194 | //\r |
| 195 | #define BMIC_nREAD bit3\r |
| 196 | #define BMIC_START bit0\r |
| 197 | #define BMIS_INTERRUPT bit2\r |
| 198 | #define BMIS_ERROR bit1\r |
| 199 | \r |
| 200 | #define BMICP_OFFSET 0x00\r |
| 201 | #define BMISP_OFFSET 0x02\r |
| 202 | #define BMIDP_OFFSET 0x04\r |
| 203 | #define BMICS_OFFSET 0x08\r |
| 204 | #define BMISS_OFFSET 0x0A\r |
| 205 | #define BMIDS_OFFSET 0x0C\r |
| 206 | \r |
| 207 | //\r |
| 208 | // Time Out Value For IDE Device Polling\r |
| 209 | //\r |
| 210 | \r |
| 211 | //\r |
| 212 | // ATATIMEOUT is used for waiting time out for ATA device\r |
| 213 | //\r |
| 214 | \r |
| 215 | //\r |
| 216 | // 1 second\r |
| 217 | //\r |
| 218 | #define ATATIMEOUT 1000 \r |
| 219 | \r |
| 220 | //\r |
| 221 | // ATAPITIMEOUT is used for waiting operation\r |
| 222 | // except read and write time out for ATAPI device\r |
| 223 | //\r |
| 224 | \r |
| 225 | //\r |
| 226 | // 1 second\r |
| 227 | //\r |
| 228 | #define ATAPITIMEOUT 1000 \r |
| 229 | \r |
| 230 | //\r |
| 231 | // ATAPILONGTIMEOUT is used for waiting read and\r |
| 232 | // write operation timeout for ATAPI device\r |
| 233 | //\r |
| 234 | \r |
| 235 | //\r |
| 236 | // 2 seconds\r |
| 237 | //\r |
| 238 | #define CDROMLONGTIMEOUT 2000 \r |
| 239 | \r |
| 240 | //\r |
| 241 | // 5 seconds\r |
| 242 | //\r |
| 243 | #define ATAPILONGTIMEOUT 5000 \r |
| 244 | \r |
| 245 | //\r |
| 246 | // ATA Commands Code\r |
| 247 | //\r |
| 248 | #define ATA_INITIALIZE_DEVICE 0x91\r |
| 249 | \r |
| 250 | //\r |
| 251 | // Class 1\r |
| 252 | //\r |
| 253 | #define IDENTIFY_DRIVE_CMD 0xec\r |
| 254 | #define READ_BUFFER_CMD 0xe4\r |
| 255 | #define READ_SECTORS_CMD 0x20\r |
| 256 | #define READ_SECTORS_WITH_RETRY_CMD 0x21\r |
| 257 | #define READ_LONG_CMD 0x22\r |
| 258 | #define READ_LONG_WITH_RETRY_CMD 0x23\r |
| 259 | //\r |
| 260 | // Class 1 - Atapi6 enhanced commands\r |
| 261 | //\r |
| 262 | #define READ_SECTORS_EXT_CMD 0x24\r |
| 263 | \r |
| 264 | //\r |
| 265 | // Class 2\r |
| 266 | //\r |
| 267 | #define FORMAT_TRACK_CMD 0x50\r |
| 268 | #define WRITE_BUFFER_CMD 0xe8\r |
| 269 | #define WRITE_SECTORS_CMD 0x30\r |
| 270 | #define WRITE_SECTORS_WITH_RETRY_CMD 0x31\r |
| 271 | #define WRITE_LONG_CMD 0x32\r |
| 272 | #define WRITE_LONG_WITH_RETRY_CMD 0x33\r |
| 273 | #define WRITE_VERIFY_CMD 0x3c\r |
| 274 | //\r |
| 275 | // Class 2 - Atapi6 enhanced commands\r |
| 276 | //\r |
| 277 | #define WRITE_SECTORS_EXT_CMD 0x34\r |
| 278 | \r |
| 279 | //\r |
| 280 | // Class 3\r |
| 281 | //\r |
| 282 | #define ACK_MEDIA_CHANGE_CMD 0xdb\r |
| 283 | #define BOOT_POST_BOOT_CMD 0xdc\r |
| 284 | #define BOOT_PRE_BOOT_CMD 0xdd\r |
| 285 | #define CHECK_POWER_MODE_CMD 0x98\r |
| 286 | #define CHECK_POWER_MODE_CMD_ALIAS 0xe5\r |
| 287 | #define DOOR_LOCK_CMD 0xde\r |
| 288 | #define DOOR_UNLOCK_CMD 0xdf\r |
| 289 | #define EXEC_DRIVE_DIAG_CMD 0x90\r |
| 290 | #define IDLE_CMD_ALIAS 0x97\r |
| 291 | #define IDLE_CMD 0xe3\r |
| 292 | #define IDLE_IMMEDIATE_CMD 0x95\r |
| 293 | #define IDLE_IMMEDIATE_CMD_ALIAS 0xe1\r |
| 294 | #define INIT_DRIVE_PARAM_CMD 0x91\r |
| 295 | #define RECALIBRATE_CMD 0x10 /* aliased to 1x */\r |
| 296 | #define READ_DRIVE_STATE_CMD 0xe9\r |
| 297 | #define SET_MULTIPLE_MODE_CMD 0xC6\r |
| 298 | #define READ_DRIVE_STATE_CMD 0xe9\r |
| 299 | #define READ_VERIFY_CMD 0x40\r |
| 300 | #define READ_VERIFY_WITH_RETRY_CMD 0x41\r |
| 301 | #define SEEK_CMD 0x70 /* aliased to 7x */\r |
| 302 | #define SET_FEATURES_CMD 0xef\r |
| 303 | #define STANDBY_CMD 0x96\r |
| 304 | #define STANDBY_CMD_ALIAS 0xe2\r |
| 305 | #define STANDBY_IMMEDIATE_CMD 0x94\r |
| 306 | #define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0\r |
| 307 | \r |
| 308 | //\r |
| 309 | // Class 4\r |
| 310 | //\r |
| 311 | #define READ_DMA_CMD 0xc8\r |
| 312 | #define READ_DMA_WITH_RETRY_CMD 0xc9\r |
| 313 | #define READ_DMA_EXT_CMD 0x25\r |
| 314 | #define WRITE_DMA_CMD 0xca\r |
| 315 | #define WRITE_DMA_WITH_RETRY_CMD 0xcb\r |
| 316 | #define WRITE_DMA_EXT_CMD 0x35\r |
| 317 | \r |
| 318 | //\r |
| 319 | // Class 5\r |
| 320 | //\r |
| 321 | #define READ_MULTIPLE_CMD 0xc4\r |
| 322 | #define REST_CMD 0xe7\r |
| 323 | #define RESTORE_DRIVE_STATE_CMD 0xea\r |
| 324 | #define SET_SLEEP_MODE_CMD 0x99\r |
| 325 | #define SET_SLEEP_MODE_CMD_ALIAS 0xe6\r |
| 326 | #define WRITE_MULTIPLE_CMD 0xc5\r |
| 327 | #define WRITE_SAME_CMD 0xe9\r |
| 328 | \r |
| 329 | //\r |
| 330 | // Class 6 - Host protected area access feature set\r |
| 331 | //\r |
| 332 | #define READ_NATIVE_MAX_ADDRESS_CMD 0xf8\r |
| 333 | #define SET_MAX_ADDRESS_CMD 0xf9\r |
| 334 | \r |
| 335 | //\r |
| 336 | // Class 6 - ATA/ATAPI-6 enhanced commands\r |
| 337 | //\r |
| 338 | #define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27\r |
| 339 | #define SET_MAX_ADDRESS_CMD_EXT 0x37\r |
| 340 | \r |
| 341 | //\r |
| 342 | // Class 6 - SET_MAX related sub command (in feature register)\r |
| 343 | //\r |
| 344 | #define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00\r |
| 345 | #define PARTIES_SET_PASSWORD_SUB_CMD 0x01\r |
| 346 | #define PARTIES_LOCK_SUB_CMD 0x02\r |
| 347 | #define PARTIES_UNLOCK_SUB_CMD 0x03\r |
| 348 | #define PARTIES_FREEZE_SUB_CMD 0x04\r |
| 349 | \r |
| 350 | //\r |
| 351 | // S.M.A.R.T\r |
| 352 | //\r |
| 353 | #define ATA_SMART_CMD 0xb0\r |
| 354 | #define ATA_CONSTANT_C2 0xc2\r |
| 355 | #define ATA_CONSTANT_4F 0x4f\r |
| 356 | #define ATA_SMART_ENABLE_OPERATION 0xd8\r |
| 357 | #define ATA_SMART_RETURN_STATUS 0xda\r |
| 358 | \r |
| 359 | //\r |
| 360 | // Error codes for Exec Drive Diag\r |
| 361 | //\r |
| 362 | #define DRIV_DIAG_NO_ERROR (0x01)\r |
| 363 | #define DRIV_DIAG_FORMATTER_ERROR (0x02)\r |
| 364 | #define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)\r |
| 365 | #define DRIV_DIAG_ECC_CKT_ERRROR (0x04)\r |
| 366 | #define DRIV_DIAG_UP_ERROR (0x05)\r |
| 367 | #define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */\r |
| 368 | \r |
| 369 | //\r |
| 370 | // Codes for Format Track\r |
| 371 | //\r |
| 372 | #define FORMAT_GOOD_SECTOR (0x00)\r |
| 373 | #define FORMAT_SUSPEND_ALLOC (0x01)\r |
| 374 | #define FORMAT_REALLOC_SECTOR (0x02)\r |
| 375 | #define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)\r |
| 376 | \r |
| 377 | //\r |
| 378 | // IDE_IDENTIFY bits\r |
| 379 | // config bits :\r |
| 380 | //\r |
| 381 | #define ID_CONFIG_RESERVED0 bit0\r |
| 382 | #define ID_CONFIG_HARD_SECTORED_DRIVE bit1\r |
| 383 | #define ID_CONFIG_SOFT_SECTORED_DRIVE bit2\r |
| 384 | #define ID_CONFIG_NON_MFM bit3\r |
| 385 | #define ID_CONFIG_15uS_HEAD_SWITCHING bit4\r |
| 386 | #define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5\r |
| 387 | #define ID_CONFIG_HARD_DRIVE bit6\r |
| 388 | #define ID_CONFIG_CHANGEABLE_MEDIUM bit7\r |
| 389 | #define ID_CONFIG_DATA_RATE_TO_5MHZ bit8\r |
| 390 | #define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9\r |
| 391 | #define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10\r |
| 392 | #define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11\r |
| 393 | #define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12\r |
| 394 | #define ID_CONFIG_TRACK_OFFSET_AVAIL bit13\r |
| 395 | #define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14\r |
| 396 | #define ID_CONFIG_RESERVED1 bit15\r |
| 397 | \r |
| 398 | #define ID_DOUBLE_WORD_IO_POSSIBLE bit01\r |
| 399 | #define ID_LBA_SUPPORTED bit9\r |
| 400 | #define ID_DMA_SUPPORTED bit8\r |
| 401 | \r |
| 402 | #define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)\r |
| 403 | #define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)\r |
| 404 | #define SET_FEATURE_TRANSFER_MODE (0x03)\r |
| 405 | #define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)\r |
| 406 | #define SET_FEATURE_DISABLE_RETRIES (0x33)\r |
| 407 | //\r |
| 408 | // for Read & Write Longs\r |
| 409 | //\r |
| 410 | #define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)\r |
| 411 | #define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)\r |
| 412 | #define SET_FEATURE_DISABLE_READ_AHEAD (0x55)\r |
| 413 | #define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)\r |
| 414 | #define SET_FEATURE_DISABLE_ECC (0x77)\r |
| 415 | #define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)\r |
| 416 | #define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)\r |
| 417 | #define SET_FEATURE_ENABLE_ECC (0x88)\r |
| 418 | #define SET_FEATURE_ENABLE_RETRIES (0x99)\r |
| 419 | #define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)\r |
| 420 | #define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)\r |
| 421 | #define SET_FEATURE_ALLOW_REST_MODE (0xac)\r |
| 422 | //\r |
| 423 | // for Read & Write Longs\r |
| 424 | //\r |
| 425 | #define SET_FEATURE_4BYTE_ECC (0xbb)\r |
| 426 | #define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)\r |
| 427 | #define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)\r |
| 428 | \r |
| 429 | #define BLOCK_TRANSFER_MODE (0x00)\r |
| 430 | #define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)\r |
| 431 | #define MULTI_WORD_DMA_TRANSFER_MODE (0x20)\r |
| 432 | #define TRANSFER_MODE_MASK (0x07) // 3 LSBs\r |
| 433 | \r |
| 434 | //\r |
| 435 | // Drive 0 - Head 0\r |
| 436 | //\r |
| 437 | #define DEFAULT_DRIVE (0x00)\r |
| 438 | #define DEFAULT_CMD (0xa0)\r |
| 439 | //\r |
| 440 | // default content of device control register, disable INT\r |
| 441 | //\r |
| 442 | #define DEFAULT_CTL (0x0a)\r |
| 443 | #define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)\r |
| 444 | \r |
| 445 | //\r |
| 446 | // ATAPI6 related data structure definition\r |
| 447 | //\r |
| 448 | \r |
| 449 | //\r |
| 450 | // The maximum sectors count in 28 bit addressing mode\r |
| 451 | //\r |
| 452 | #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff\r |
| 453 | \r |
| 454 | //\r |
| 455 | // Move the IDENTIFY section to DXE\Protocol\IdeControllerInit\r |
| 456 | //\r |
| 457 | \r |
| 458 | //\r |
| 459 | // ATAPI Command\r |
| 460 | //\r |
| 461 | #define ATAPI_SOFT_RESET_CMD 0x08\r |
| 462 | #define ATAPI_PACKET_CMD 0xA0\r |
| 463 | #define PACKET_CMD 0xA0\r |
| 464 | #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1\r |
| 465 | #define ATAPI_SERVICE_CMD 0xA2\r |
| 466 | \r |
| 467 | //\r |
| 468 | // ATAPI Packet Command\r |
| 469 | //\r |
| 470 | #pragma pack(1)\r |
| 471 | \r |
| 472 | typedef struct {\r |
| 473 | UINT8 opcode;\r |
| 474 | UINT8 reserved_1;\r |
| 475 | UINT8 reserved_2;\r |
| 476 | UINT8 reserved_3;\r |
| 477 | UINT8 reserved_4;\r |
| 478 | UINT8 reserved_5;\r |
| 479 | UINT8 reserved_6;\r |
| 480 | UINT8 reserved_7;\r |
| 481 | UINT8 reserved_8;\r |
| 482 | UINT8 reserved_9;\r |
| 483 | UINT8 reserved_10;\r |
| 484 | UINT8 reserved_11;\r |
| 485 | } TEST_UNIT_READY_CMD;\r |
| 486 | \r |
| 487 | typedef struct {\r |
| 488 | UINT8 opcode;\r |
| 489 | UINT8 reserved_1 : 4;\r |
| 490 | UINT8 lun : 4;\r |
| 491 | UINT8 page_code;\r |
| 492 | UINT8 reserved_3;\r |
| 493 | UINT8 allocation_length;\r |
| 494 | UINT8 reserved_5;\r |
| 495 | UINT8 reserved_6;\r |
| 496 | UINT8 reserved_7;\r |
| 497 | UINT8 reserved_8;\r |
| 498 | UINT8 reserved_9;\r |
| 499 | UINT8 reserved_10;\r |
| 500 | UINT8 reserved_11;\r |
| 501 | } INQUIRY_CMD;\r |
| 502 | \r |
| 503 | typedef struct {\r |
| 504 | UINT8 opcode;\r |
| 505 | UINT8 reserved_1 : 4;\r |
| 506 | UINT8 lun : 4;\r |
| 507 | UINT8 reserved_2;\r |
| 508 | UINT8 reserved_3;\r |
| 509 | UINT8 allocation_length;\r |
| 510 | UINT8 reserved_5;\r |
| 511 | UINT8 reserved_6;\r |
| 512 | UINT8 reserved_7;\r |
| 513 | UINT8 reserved_8;\r |
| 514 | UINT8 reserved_9;\r |
| 515 | UINT8 reserved_10;\r |
| 516 | UINT8 reserved_11;\r |
| 517 | } REQUEST_SENSE_CMD;\r |
| 518 | \r |
| 519 | typedef struct {\r |
| 520 | UINT8 opcode;\r |
| 521 | UINT8 reserved_1 : 4;\r |
| 522 | UINT8 lun : 4;\r |
| 523 | UINT8 page_code : 4;\r |
| 524 | UINT8 page_control : 4;\r |
| 525 | UINT8 reserved_3;\r |
| 526 | UINT8 reserved_4;\r |
| 527 | UINT8 reserved_5;\r |
| 528 | UINT8 reserved_6;\r |
| 529 | UINT8 parameter_list_length_hi;\r |
| 530 | UINT8 parameter_list_length_lo;\r |
| 531 | UINT8 reserved_9;\r |
| 532 | UINT8 reserved_10;\r |
| 533 | UINT8 reserved_11;\r |
| 534 | } MODE_SENSE_CMD;\r |
| 535 | \r |
| 536 | typedef struct {\r |
| 537 | UINT8 opcode;\r |
| 538 | UINT8 reserved_1 : 5;\r |
| 539 | UINT8 lun : 3;\r |
| 540 | UINT8 Lba0;\r |
| 541 | UINT8 Lba1;\r |
| 542 | UINT8 Lba2;\r |
| 543 | UINT8 Lba3;\r |
| 544 | UINT8 reserved_6;\r |
| 545 | UINT8 TranLen0;\r |
| 546 | UINT8 TranLen1;\r |
| 547 | UINT8 reserved_9;\r |
| 548 | UINT8 reserved_10;\r |
| 549 | UINT8 reserved_11;\r |
| 550 | } READ10_CMD;\r |
| 551 | \r |
| 552 | typedef struct {\r |
| 553 | UINT8 opcode;\r |
| 554 | UINT8 reserved_1;\r |
| 555 | UINT8 reserved_2;\r |
| 556 | UINT8 reserved_3;\r |
| 557 | UINT8 reserved_4;\r |
| 558 | UINT8 reserved_5;\r |
| 559 | UINT8 reserved_6;\r |
| 560 | UINT8 allocation_length_hi;\r |
| 561 | UINT8 allocation_length_lo;\r |
| 562 | UINT8 reserved_9;\r |
| 563 | UINT8 reserved_10;\r |
| 564 | UINT8 reserved_11;\r |
| 565 | } READ_FORMAT_CAP_CMD;\r |
| 566 | \r |
| 567 | typedef union {\r |
| 568 | UINT16 Data16[6];\r |
| 569 | TEST_UNIT_READY_CMD TestUnitReady;\r |
| 570 | READ10_CMD Read10;\r |
| 571 | REQUEST_SENSE_CMD RequestSence;\r |
| 572 | INQUIRY_CMD Inquiry;\r |
| 573 | MODE_SENSE_CMD ModeSense;\r |
| 574 | READ_FORMAT_CAP_CMD ReadFormatCapacity;\r |
| 575 | } ATAPI_PACKET_COMMAND;\r |
| 576 | \r |
| 577 | typedef struct {\r |
| 578 | UINT32 RegionBaseAddr;\r |
| 579 | UINT16 ByteCount;\r |
| 580 | UINT16 EndOfTable;\r |
| 581 | } IDE_DMA_PRD;\r |
| 582 | \r |
| 583 | #define MAX_DMA_EXT_COMMAND_SECTORS 0x10000\r |
| 584 | #define MAX_DMA_COMMAND_SECTORS 0x100\r |
| 585 | \r |
| 586 | #pragma pack()\r |
| 587 | \r |
| 588 | //\r |
| 589 | // Packet Command Code\r |
| 590 | //\r |
| 591 | #define TEST_UNIT_READY 0x00\r |
| 592 | #define REZERO 0x01\r |
| 593 | #define REQUEST_SENSE 0x03\r |
| 594 | #define FORMAT_UNIT 0x04\r |
| 595 | #define REASSIGN_BLOCKS 0x07\r |
| 596 | #define INQUIRY 0x12\r |
| 597 | #define START_STOP_UNIT 0x1B\r |
| 598 | #define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E\r |
| 599 | #define READ_FORMAT_CAPACITY 0x23\r |
| 600 | #define OLD_FORMAT_UNIT 0x24\r |
| 601 | #define READ_CAPACITY 0x25\r |
| 602 | #define READ_10 0x28\r |
| 603 | #define WRITE_10 0x2A\r |
| 604 | #define SEEK 0x2B\r |
| 605 | #define SEND_DIAGNOSTICS 0x3D\r |
| 606 | #define WRITE_VERIFY 0x2E\r |
| 607 | #define VERIFY 0x2F\r |
| 608 | #define READ_DEFECT_DATA 0x37\r |
| 609 | #define WRITE_BUFFER 0x38\r |
| 610 | #define READ_BUFFER 0x3C\r |
| 611 | #define READ_LONG 0x3E\r |
| 612 | #define WRITE_LONG 0x3F\r |
| 613 | #define MODE_SELECT 0x55\r |
| 614 | #define MODE_SENSE 0x5A\r |
| 615 | #define READ_12 0xA8\r |
| 616 | #define WRITE_12 0xAA\r |
| 617 | #define MAX_ATAPI_BYTE_COUNT (0xfffe)\r |
| 618 | \r |
| 619 | //\r |
| 620 | // Sense Key\r |
| 621 | //\r |
| 622 | #define REQUEST_SENSE_ERROR (0x70)\r |
| 623 | #define SK_NO_SENSE (0x0)\r |
| 624 | #define SK_RECOVERY_ERROR (0x1)\r |
| 625 | #define SK_NOT_READY (0x2)\r |
| 626 | #define SK_MEDIUM_ERROR (0x3)\r |
| 627 | #define SK_HARDWARE_ERROR (0x4)\r |
| 628 | #define SK_ILLEGAL_REQUEST (0x5)\r |
| 629 | #define SK_UNIT_ATTENTION (0x6)\r |
| 630 | #define SK_DATA_PROTECT (0x7)\r |
| 631 | #define SK_BLANK_CHECK (0x8)\r |
| 632 | #define SK_VENDOR_SPECIFIC (0x9)\r |
| 633 | #define SK_RESERVED_A (0xA)\r |
| 634 | #define SK_ABORT (0xB)\r |
| 635 | #define SK_RESERVED_C (0xC)\r |
| 636 | #define SK_OVERFLOW (0xD)\r |
| 637 | #define SK_MISCOMPARE (0xE)\r |
| 638 | #define SK_RESERVED_F (0xF)\r |
| 639 | \r |
| 640 | //\r |
| 641 | // Additional Sense Codes\r |
| 642 | //\r |
| 643 | #define ASC_NOT_READY (0x04)\r |
| 644 | #define ASC_MEDIA_ERR1 (0x10)\r |
| 645 | #define ASC_MEDIA_ERR2 (0x11)\r |
| 646 | #define ASC_MEDIA_ERR3 (0x14)\r |
| 647 | #define ASC_MEDIA_ERR4 (0x30)\r |
| 648 | #define ASC_MEDIA_UPSIDE_DOWN (0x06)\r |
| 649 | #define ASC_INVALID_CMD (0x20)\r |
| 650 | #define ASC_LBA_OUT_OF_RANGE (0x21)\r |
| 651 | #define ASC_INVALID_FIELD (0x24)\r |
| 652 | #define ASC_WRITE_PROTECTED (0x27)\r |
| 653 | #define ASC_MEDIA_CHANGE (0x28)\r |
| 654 | #define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */\r |
| 655 | #define ASC_ILLEGAL_FIELD (0x26)\r |
| 656 | #define ASC_NO_MEDIA (0x3A)\r |
| 657 | #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r |
| 658 | \r |
| 659 | //\r |
| 660 | // Additional Sense Code Qualifier\r |
| 661 | //\r |
| 662 | #define ASCQ_IN_PROGRESS (0x01)\r |
| 663 | \r |
| 664 | #define SETFEATURE TRUE\r |
| 665 | #define CLEARFEATURE FALSE\r |
| 666 | \r |
| 667 | //\r |
| 668 | // ATAPI Data structure\r |
| 669 | //\r |
| 670 | #pragma pack(1)\r |
| 671 | \r |
| 672 | typedef struct {\r |
| 673 | UINT8 peripheral_type;\r |
| 674 | UINT8 RMB;\r |
| 675 | UINT8 version;\r |
| 676 | UINT8 response_data_format;\r |
| 677 | UINT8 addnl_length;\r |
| 678 | UINT8 reserved_5;\r |
| 679 | UINT8 reserved_6;\r |
| 680 | UINT8 reserved_7;\r |
| 681 | UINT8 vendor_info[8];\r |
| 682 | UINT8 product_id[12];\r |
| 683 | UINT8 eeprom_product_code[4];\r |
| 684 | UINT8 firmware_rev_level[4];\r |
| 685 | UINT8 firmware_sub_rev_level[1];\r |
| 686 | UINT8 reserved_37;\r |
| 687 | UINT8 reserved_38;\r |
| 688 | UINT8 reserved_39;\r |
| 689 | UINT8 max_capacity_hi;\r |
| 690 | UINT8 max_capacity_mid;\r |
| 691 | UINT8 max_capacity_lo;\r |
| 692 | UINT8 reserved_43_95[95 - 43 + 1];\r |
| 693 | } INQUIRY_DATA;\r |
| 694 | \r |
| 695 | typedef struct {\r |
| 696 | UINT8 peripheral_type;\r |
| 697 | UINT8 RMB;\r |
| 698 | UINT8 version;\r |
| 699 | UINT8 response_data_format;\r |
| 700 | UINT8 addnl_length;\r |
| 701 | UINT8 reserved_5;\r |
| 702 | UINT8 reserved_6;\r |
| 703 | UINT8 reserved_7;\r |
| 704 | UINT8 vendor_info[8];\r |
| 705 | UINT8 product_id[16];\r |
| 706 | UINT8 product_revision_level[4];\r |
| 707 | UINT8 vendor_specific[20];\r |
| 708 | UINT8 reserved_56_95[40];\r |
| 709 | } CDROM_INQUIRY_DATA;\r |
| 710 | \r |
| 711 | typedef struct {\r |
| 712 | UINT8 error_code : 7;\r |
| 713 | UINT8 valid : 1;\r |
| 714 | UINT8 reserved_1;\r |
| 715 | UINT8 sense_key : 4;\r |
| 716 | UINT8 reserved_21 : 1;\r |
| 717 | UINT8 ILI : 1;\r |
| 718 | UINT8 reserved_22 : 2;\r |
| 719 | UINT8 vendor_specific_3;\r |
| 720 | UINT8 vendor_specific_4;\r |
| 721 | UINT8 vendor_specific_5;\r |
| 722 | UINT8 vendor_specific_6;\r |
| 723 | UINT8 addnl_sense_length; // n - 7\r |
| 724 | UINT8 vendor_specific_8;\r |
| 725 | UINT8 vendor_specific_9;\r |
| 726 | UINT8 vendor_specific_10;\r |
| 727 | UINT8 vendor_specific_11;\r |
| 728 | UINT8 addnl_sense_code; // mandatory\r |
| 729 | UINT8 addnl_sense_code_qualifier; // mandatory\r |
| 730 | UINT8 field_replaceable_unit_code; // optional\r |
| 731 | UINT8 reserved_15;\r |
| 732 | UINT8 reserved_16;\r |
| 733 | UINT8 reserved_17;\r |
| 734 | //\r |
| 735 | // Followed by additional sense bytes : FIXME\r |
| 736 | //\r |
| 737 | } REQUEST_SENSE_DATA;\r |
| 738 | \r |
| 739 | typedef struct {\r |
| 740 | UINT8 LastLba3;\r |
| 741 | UINT8 LastLba2;\r |
| 742 | UINT8 LastLba1;\r |
| 743 | UINT8 LastLba0;\r |
| 744 | UINT8 BlockSize3;\r |
| 745 | UINT8 BlockSize2;\r |
| 746 | UINT8 BlockSize1;\r |
| 747 | UINT8 BlockSize0;\r |
| 748 | } READ_CAPACITY_DATA;\r |
| 749 | \r |
| 750 | typedef struct {\r |
| 751 | UINT8 reserved_0;\r |
| 752 | UINT8 reserved_1;\r |
| 753 | UINT8 reserved_2;\r |
| 754 | UINT8 Capacity_Length;\r |
| 755 | UINT8 LastLba3;\r |
| 756 | UINT8 LastLba2;\r |
| 757 | UINT8 LastLba1;\r |
| 758 | UINT8 LastLba0;\r |
| 759 | UINT8 DesCode : 2;\r |
| 760 | UINT8 reserved_9 : 6;\r |
| 761 | UINT8 BlockSize2;\r |
| 762 | UINT8 BlockSize1;\r |
| 763 | UINT8 BlockSize0;\r |
| 764 | } READ_FORMAT_CAPACITY_DATA;\r |
| 765 | \r |
| 766 | #pragma pack()\r |
| 767 | \r |
| 768 | //\r |
| 769 | // PIO mode definition\r |
| 770 | //\r |
| 771 | typedef enum {\r |
| 772 | ATA_PIO_MODE_BELOW_2,\r |
| 773 | ATA_PIO_MODE_2,\r |
| 774 | ATA_PIO_MODE_3,\r |
| 775 | ATA_PIO_MODE_4\r |
| 776 | } ATA_PIO_MODE;\r |
| 777 | \r |
| 778 | //\r |
| 779 | // Multi word DMA definition\r |
| 780 | //\r |
| 781 | typedef enum {\r |
| 782 | ATA_MDMA_MODE_0,\r |
| 783 | ATA_MDMA_MODE_1,\r |
| 784 | ATA_MDMA_MODE_2\r |
| 785 | } ATA_MDMA_MODE;\r |
| 786 | \r |
| 787 | //\r |
| 788 | // UDMA mode definition\r |
| 789 | //\r |
| 790 | typedef enum {\r |
| 791 | ATA_UDMA_MODE_0,\r |
| 792 | ATA_UDMA_MODE_1,\r |
| 793 | ATA_UDMA_MODE_2,\r |
| 794 | ATA_UDMA_MODE_3,\r |
| 795 | ATA_UDMA_MODE_4,\r |
| 796 | ATA_UDMA_MODE_5\r |
| 797 | } ATA_UDMA_MODE;\r |
| 798 | \r |
| 799 | #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00\r |
| 800 | #define ATA_MODE_CATEGORY_FLOW_PIO 0x01\r |
| 801 | #define ATA_MODE_CATEGORY_MDMA 0x04\r |
| 802 | #define ATA_MODE_CATEGORY_UDMA 0x08\r |
| 803 | \r |
| 804 | #pragma pack(1)\r |
| 805 | \r |
| 806 | typedef struct {\r |
| 807 | UINT8 ModeNumber : 3;\r |
| 808 | UINT8 ModeCategory : 5;\r |
| 809 | } ATA_TRANSFER_MODE;\r |
| 810 | \r |
| 811 | typedef struct {\r |
| 812 | UINT8 Sector;\r |
| 813 | UINT8 Heads;\r |
| 814 | UINT8 MultipleSector;\r |
| 815 | } ATA_DRIVE_PARMS;\r |
| 816 | \r |
| 817 | #pragma pack()\r |
| 818 | //\r |
| 819 | // IORDY Sample Point field value\r |
| 820 | //\r |
| 821 | #define ISP_5_CLK 0\r |
| 822 | #define ISP_4_CLK 1\r |
| 823 | #define ISP_3_CLK 2\r |
| 824 | #define ISP_2_CLK 3\r |
| 825 | \r |
| 826 | //\r |
| 827 | // Recovery Time field value\r |
| 828 | //\r |
| 829 | #define RECVY_4_CLK 0\r |
| 830 | #define RECVY_3_CLK 1\r |
| 831 | #define RECVY_2_CLK 2\r |
| 832 | #define RECVY_1_CLK 3\r |
| 833 | \r |
| 834 | //\r |
| 835 | // Slave IDE Timing Register Enable\r |
| 836 | //\r |
| 837 | #define SITRE bit14\r |
| 838 | \r |
| 839 | //\r |
| 840 | // DMA Timing Enable Only Select 1\r |
| 841 | //\r |
| 842 | #define DTE1 bit7\r |
| 843 | \r |
| 844 | //\r |
| 845 | // Pre-fetch and Posting Enable Select 1\r |
| 846 | //\r |
| 847 | #define PPE1 bit6\r |
| 848 | \r |
| 849 | //\r |
| 850 | // IORDY Sample Point Enable Select 1\r |
| 851 | //\r |
| 852 | #define IE1 bit5\r |
| 853 | \r |
| 854 | //\r |
| 855 | // Fast Timing Bank Drive Select 1\r |
| 856 | //\r |
| 857 | #define TIME1 bit4\r |
| 858 | \r |
| 859 | //\r |
| 860 | // DMA Timing Enable Only Select 0\r |
| 861 | //\r |
| 862 | #define DTE0 bit3\r |
| 863 | \r |
| 864 | //\r |
| 865 | // Pre-fetch and Posting Enable Select 0\r |
| 866 | //\r |
| 867 | #define PPE0 bit2\r |
| 868 | \r |
| 869 | //\r |
| 870 | // IOREY Sample Point Enable Select 0\r |
| 871 | //\r |
| 872 | #define IE0 bit1\r |
| 873 | \r |
| 874 | //\r |
| 875 | // Fast Timing Bank Drive Select 0\r |
| 876 | //\r |
| 877 | #define TIME0 bit0\r |
| 878 | \r |
| 879 | #endif\r |
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