In IdeBus driver block I/O read/write interface, it will always try to use UDMA mode...
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / IdeBus / Dxe / idedata.h
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ed72955c 1/** @file\r
2 Header file for IDE Bus Driver's Data Structures\r
878ddf1f 3\r
ed72955c 4 Copyright (c) 2006, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
878ddf1f 9\r
ed72955c 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
878ddf1f 12\r
ed72955c 13**/\r
878ddf1f 14\r
878ddf1f 15#ifndef _IDE_DATA_H\r
16#define _IDE_DATA_H\r
17\r
18//\r
19// bit definition\r
20//\r
21#define bit0 (1 << 0)\r
22#define bit1 (1 << 1)\r
23#define bit2 (1 << 2)\r
24#define bit3 (1 << 3)\r
25#define bit4 (1 << 4)\r
26#define bit5 (1 << 5)\r
27#define bit6 (1 << 6)\r
28#define bit7 (1 << 7)\r
29#define bit8 (1 << 8)\r
30#define bit9 (1 << 9)\r
31#define bit10 (1 << 10)\r
32#define bit11 (1 << 11)\r
33#define bit12 (1 << 12)\r
34#define bit13 (1 << 13)\r
35#define bit14 (1 << 14)\r
36#define bit15 (1 << 15)\r
37#define bit16 (1 << 16)\r
38#define bit17 (1 << 17)\r
39#define bit18 (1 << 18)\r
40#define bit19 (1 << 19)\r
41#define bit20 (1 << 20)\r
42#define bit21 (1 << 21)\r
43#define bit22 (1 << 22)\r
44#define bit23 (1 << 23)\r
45#define bit24 (1 << 24)\r
46#define bit25 (1 << 25)\r
47#define bit26 (1 << 26)\r
48#define bit27 (1 << 27)\r
49#define bit28 (1 << 28)\r
50#define bit29 (1 << 29)\r
51#define bit30 (1 << 30)\r
52#define bit31 (1 << 31)\r
53\r
54//\r
55// common constants\r
56//\r
57#define STALL_1_MILLI_SECOND 1000 // stall 1 ms\r
58#define STALL_1_SECOND 1000000 // stall 1 second\r
59typedef enum {\r
60 IdePrimary = 0,\r
61 IdeSecondary = 1,\r
62 IdeMaxChannel = 2\r
63} EFI_IDE_CHANNEL;\r
64\r
65typedef enum {\r
66 IdeMaster = 0,\r
67 IdeSlave = 1,\r
68 IdeMaxDevice = 2\r
69} EFI_IDE_DEVICE;\r
70\r
71typedef enum {\r
72 IdeMagnetic, /* ZIP Drive or LS120 Floppy Drive */\r
73 IdeCdRom, /* ATAPI CDROM */\r
74 IdeHardDisk, /* Hard Disk */\r
75 Ide48bitAddressingHardDisk, /* Hard Disk larger than 120GB */\r
76 IdeUnknown\r
77} IDE_DEVICE_TYPE;\r
78\r
a98f11c5 79typedef enum {\r
80 SenseNoSenseKey,\r
81 SenseDeviceNotReadyNoRetry,\r
82 SenseDeviceNotReadyNeedRetry,\r
83 SenseNoMedia,\r
84 SenseMediaChange,\r
85 SenseMediaError,\r
86 SenseOtherSense\r
87} SENSE_RESULT;\r
88\r
bc4e770c 89typedef enum {\r
90 AtaUdmaReadOp,\r
91 AtaUdmaReadExtOp,\r
92 AtaUdmaWriteOp,\r
93 AtaUdmaWriteExtOp\r
94} ATA_UDMA_OPERATION;\r
95\r
878ddf1f 96//\r
97// IDE Registers\r
98//\r
99typedef union {\r
100 UINT16 Command; /* when write */\r
101 UINT16 Status; /* when read */\r
102} IDE_CMD_OR_STATUS;\r
103\r
104typedef union {\r
105 UINT16 Error; /* when read */\r
106 UINT16 Feature; /* when write */\r
107} IDE_ERROR_OR_FEATURE;\r
108\r
109typedef union {\r
110 UINT16 AltStatus; /* when read */\r
111 UINT16 DeviceControl; /* when write */\r
112} IDE_AltStatus_OR_DeviceControl;\r
113\r
114//\r
115// IDE registers set\r
116//\r
117typedef struct {\r
118 UINT16 Data;\r
119 IDE_ERROR_OR_FEATURE Reg1;\r
120 UINT16 SectorCount;\r
121 UINT16 SectorNumber;\r
122 UINT16 CylinderLsb;\r
123 UINT16 CylinderMsb;\r
124 UINT16 Head;\r
125 IDE_CMD_OR_STATUS Reg;\r
126\r
127 IDE_AltStatus_OR_DeviceControl Alt;\r
128 UINT16 DriveAddress;\r
129\r
130 UINT16 MasterSlave;\r
131 UINT16 BusMasterBaseAddr;\r
132} IDE_BASE_REGISTERS;\r
133\r
134//\r
135// IDE registers' base addresses\r
136//\r
137typedef struct {\r
138 UINT16 CommandBlockBaseAddr;\r
139 UINT16 ControlBlockBaseAddr;\r
140 UINT16 BusMasterBaseAddr;\r
141} IDE_REGISTERS_BASE_ADDR;\r
142\r
143//\r
144// Bit definitions in Programming Interface byte of the Class Code field\r
145// in PCI IDE controller's Configuration Space\r
146//\r
147#define IDE_PRIMARY_OPERATING_MODE bit0\r
148#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1\r
149#define IDE_SECONDARY_OPERATING_MODE bit2\r
150#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3\r
151\r
152//\r
153// IDE registers bit definitions\r
154//\r
155\r
156//\r
157// Err Reg\r
158//\r
159#define BBK_ERR bit7 /* Bad block detected */\r
160#define UNC_ERR bit6 /* Uncorrectable Data */\r
161#define MC_ERR bit5 /* Media Change */\r
162#define IDNF_ERR bit4 /* ID Not Found */\r
163#define MCR_ERR bit3 /* Media Change Requested */\r
164#define ABRT_ERR bit2 /* Aborted Command */\r
165#define TK0NF_ERR bit1 /* Track 0 Not Found */\r
166#define AMNF_ERR bit0 /* Address Mark Not Found */\r
167\r
168//\r
169// Device/Head Reg\r
170//\r
171#define LBA_MODE bit6\r
172#define DEV bit4\r
173#define HS3 bit3\r
174#define HS2 bit2\r
175#define HS1 bit1\r
176#define HS0 bit0\r
177#define CHS_MODE (0)\r
178#define DRV0 (0)\r
179#define DRV1 (1)\r
180#define MST_DRV DRV0\r
181#define SLV_DRV DRV1\r
182\r
183//\r
184// Status Reg\r
185//\r
186#define BSY bit7 /* Controller Busy */\r
187#define DRDY bit6 /* Drive Ready */\r
188#define DWF bit5 /* Drive Write Fault */\r
189#define DSC bit4 /* Disk Seek Complete */\r
190#define DRQ bit3 /* Data Request */\r
191#define CORR bit2 /* Corrected Data */\r
192#define IDX bit1 /* Index */\r
193#define ERR bit0 /* Error */\r
194\r
195//\r
196// Device Control Reg\r
197//\r
198#define SRST bit2 /* Software Reset */\r
199#define IEN_L bit1 /* Interrupt Enable #*/\r
200\r
201//\r
202// Bus Master Reg\r
203//\r
204#define BMIC_nREAD bit3\r
205#define BMIC_START bit0\r
206#define BMIS_INTERRUPT bit2\r
207#define BMIS_ERROR bit1\r
208\r
209#define BMICP_OFFSET 0x00\r
210#define BMISP_OFFSET 0x02\r
211#define BMIDP_OFFSET 0x04\r
212#define BMICS_OFFSET 0x08\r
213#define BMISS_OFFSET 0x0A\r
214#define BMIDS_OFFSET 0x0C\r
215\r
216//\r
217// Time Out Value For IDE Device Polling\r
218//\r
219\r
220//\r
221// ATATIMEOUT is used for waiting time out for ATA device\r
222//\r
223\r
224//\r
225// 1 second\r
226//\r
227#define ATATIMEOUT 1000 \r
228\r
229//\r
230// ATAPITIMEOUT is used for waiting operation\r
231// except read and write time out for ATAPI device\r
232//\r
233\r
234//\r
235// 1 second\r
236//\r
237#define ATAPITIMEOUT 1000 \r
238\r
239//\r
240// ATAPILONGTIMEOUT is used for waiting read and\r
241// write operation timeout for ATAPI device\r
242//\r
243\r
244//\r
245// 2 seconds\r
246//\r
247#define CDROMLONGTIMEOUT 2000 \r
248\r
249//\r
250// 5 seconds\r
251//\r
252#define ATAPILONGTIMEOUT 5000 \r
253\r
a98f11c5 254//\r
255// 10 seconds\r
256//\r
257#define ATASMARTTIMEOUT 10000\r
258\r
878ddf1f 259//\r
260// ATA Commands Code\r
261//\r
262#define ATA_INITIALIZE_DEVICE 0x91\r
263\r
264//\r
265// Class 1\r
266//\r
267#define IDENTIFY_DRIVE_CMD 0xec\r
268#define READ_BUFFER_CMD 0xe4\r
269#define READ_SECTORS_CMD 0x20\r
270#define READ_SECTORS_WITH_RETRY_CMD 0x21\r
271#define READ_LONG_CMD 0x22\r
272#define READ_LONG_WITH_RETRY_CMD 0x23\r
273//\r
274// Class 1 - Atapi6 enhanced commands\r
275//\r
276#define READ_SECTORS_EXT_CMD 0x24\r
277\r
278//\r
279// Class 2\r
280//\r
281#define FORMAT_TRACK_CMD 0x50\r
282#define WRITE_BUFFER_CMD 0xe8\r
283#define WRITE_SECTORS_CMD 0x30\r
284#define WRITE_SECTORS_WITH_RETRY_CMD 0x31\r
285#define WRITE_LONG_CMD 0x32\r
286#define WRITE_LONG_WITH_RETRY_CMD 0x33\r
287#define WRITE_VERIFY_CMD 0x3c\r
288//\r
289// Class 2 - Atapi6 enhanced commands\r
290//\r
291#define WRITE_SECTORS_EXT_CMD 0x34\r
292\r
293//\r
294// Class 3\r
295//\r
296#define ACK_MEDIA_CHANGE_CMD 0xdb\r
297#define BOOT_POST_BOOT_CMD 0xdc\r
298#define BOOT_PRE_BOOT_CMD 0xdd\r
299#define CHECK_POWER_MODE_CMD 0x98\r
300#define CHECK_POWER_MODE_CMD_ALIAS 0xe5\r
301#define DOOR_LOCK_CMD 0xde\r
302#define DOOR_UNLOCK_CMD 0xdf\r
303#define EXEC_DRIVE_DIAG_CMD 0x90\r
304#define IDLE_CMD_ALIAS 0x97\r
305#define IDLE_CMD 0xe3\r
306#define IDLE_IMMEDIATE_CMD 0x95\r
307#define IDLE_IMMEDIATE_CMD_ALIAS 0xe1\r
308#define INIT_DRIVE_PARAM_CMD 0x91\r
309#define RECALIBRATE_CMD 0x10 /* aliased to 1x */\r
310#define READ_DRIVE_STATE_CMD 0xe9\r
311#define SET_MULTIPLE_MODE_CMD 0xC6\r
312#define READ_DRIVE_STATE_CMD 0xe9\r
313#define READ_VERIFY_CMD 0x40\r
314#define READ_VERIFY_WITH_RETRY_CMD 0x41\r
315#define SEEK_CMD 0x70 /* aliased to 7x */\r
316#define SET_FEATURES_CMD 0xef\r
317#define STANDBY_CMD 0x96\r
318#define STANDBY_CMD_ALIAS 0xe2\r
319#define STANDBY_IMMEDIATE_CMD 0x94\r
320#define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0\r
321\r
322//\r
323// Class 4\r
324//\r
325#define READ_DMA_CMD 0xc8\r
326#define READ_DMA_WITH_RETRY_CMD 0xc9\r
327#define READ_DMA_EXT_CMD 0x25\r
328#define WRITE_DMA_CMD 0xca\r
329#define WRITE_DMA_WITH_RETRY_CMD 0xcb\r
330#define WRITE_DMA_EXT_CMD 0x35\r
331\r
332//\r
333// Class 5\r
334//\r
335#define READ_MULTIPLE_CMD 0xc4\r
336#define REST_CMD 0xe7\r
337#define RESTORE_DRIVE_STATE_CMD 0xea\r
338#define SET_SLEEP_MODE_CMD 0x99\r
339#define SET_SLEEP_MODE_CMD_ALIAS 0xe6\r
340#define WRITE_MULTIPLE_CMD 0xc5\r
341#define WRITE_SAME_CMD 0xe9\r
342\r
343//\r
344// Class 6 - Host protected area access feature set\r
345//\r
346#define READ_NATIVE_MAX_ADDRESS_CMD 0xf8\r
347#define SET_MAX_ADDRESS_CMD 0xf9\r
348\r
349//\r
350// Class 6 - ATA/ATAPI-6 enhanced commands\r
351//\r
352#define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27\r
353#define SET_MAX_ADDRESS_CMD_EXT 0x37\r
354\r
355//\r
356// Class 6 - SET_MAX related sub command (in feature register)\r
357//\r
358#define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00\r
359#define PARTIES_SET_PASSWORD_SUB_CMD 0x01\r
360#define PARTIES_LOCK_SUB_CMD 0x02\r
361#define PARTIES_UNLOCK_SUB_CMD 0x03\r
362#define PARTIES_FREEZE_SUB_CMD 0x04\r
363\r
364//\r
365// S.M.A.R.T\r
366//\r
367#define ATA_SMART_CMD 0xb0\r
368#define ATA_CONSTANT_C2 0xc2\r
369#define ATA_CONSTANT_4F 0x4f\r
370#define ATA_SMART_ENABLE_OPERATION 0xd8\r
371#define ATA_SMART_RETURN_STATUS 0xda\r
372\r
373//\r
374// Error codes for Exec Drive Diag\r
375//\r
376#define DRIV_DIAG_NO_ERROR (0x01)\r
377#define DRIV_DIAG_FORMATTER_ERROR (0x02)\r
378#define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)\r
379#define DRIV_DIAG_ECC_CKT_ERRROR (0x04)\r
380#define DRIV_DIAG_UP_ERROR (0x05)\r
381#define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */\r
382\r
383//\r
384// Codes for Format Track\r
385//\r
386#define FORMAT_GOOD_SECTOR (0x00)\r
387#define FORMAT_SUSPEND_ALLOC (0x01)\r
388#define FORMAT_REALLOC_SECTOR (0x02)\r
389#define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)\r
390\r
391//\r
392// IDE_IDENTIFY bits\r
393// config bits :\r
394//\r
395#define ID_CONFIG_RESERVED0 bit0\r
396#define ID_CONFIG_HARD_SECTORED_DRIVE bit1\r
397#define ID_CONFIG_SOFT_SECTORED_DRIVE bit2\r
398#define ID_CONFIG_NON_MFM bit3\r
399#define ID_CONFIG_15uS_HEAD_SWITCHING bit4\r
400#define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5\r
401#define ID_CONFIG_HARD_DRIVE bit6\r
402#define ID_CONFIG_CHANGEABLE_MEDIUM bit7\r
403#define ID_CONFIG_DATA_RATE_TO_5MHZ bit8\r
404#define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9\r
405#define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10\r
406#define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11\r
407#define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12\r
408#define ID_CONFIG_TRACK_OFFSET_AVAIL bit13\r
409#define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14\r
410#define ID_CONFIG_RESERVED1 bit15\r
411\r
412#define ID_DOUBLE_WORD_IO_POSSIBLE bit01\r
413#define ID_LBA_SUPPORTED bit9\r
414#define ID_DMA_SUPPORTED bit8\r
415\r
416#define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)\r
417#define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)\r
418#define SET_FEATURE_TRANSFER_MODE (0x03)\r
419#define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)\r
420#define SET_FEATURE_DISABLE_RETRIES (0x33)\r
421//\r
422// for Read & Write Longs\r
423//\r
424#define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)\r
425#define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)\r
426#define SET_FEATURE_DISABLE_READ_AHEAD (0x55)\r
427#define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)\r
428#define SET_FEATURE_DISABLE_ECC (0x77)\r
429#define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)\r
430#define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)\r
431#define SET_FEATURE_ENABLE_ECC (0x88)\r
432#define SET_FEATURE_ENABLE_RETRIES (0x99)\r
433#define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)\r
434#define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)\r
435#define SET_FEATURE_ALLOW_REST_MODE (0xac)\r
436//\r
437// for Read & Write Longs\r
438//\r
439#define SET_FEATURE_4BYTE_ECC (0xbb)\r
440#define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)\r
441#define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)\r
442\r
443#define BLOCK_TRANSFER_MODE (0x00)\r
444#define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)\r
445#define MULTI_WORD_DMA_TRANSFER_MODE (0x20)\r
446#define TRANSFER_MODE_MASK (0x07) // 3 LSBs\r
447\r
448//\r
449// Drive 0 - Head 0\r
450//\r
451#define DEFAULT_DRIVE (0x00)\r
452#define DEFAULT_CMD (0xa0)\r
453//\r
454// default content of device control register, disable INT\r
455//\r
456#define DEFAULT_CTL (0x0a)\r
457#define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)\r
458\r
459//\r
460// ATAPI6 related data structure definition\r
461//\r
462\r
463//\r
464// The maximum sectors count in 28 bit addressing mode\r
465//\r
466#define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff\r
467\r
468//\r
469// Move the IDENTIFY section to DXE\Protocol\IdeControllerInit\r
470//\r
471\r
472//\r
473// ATAPI Command\r
474//\r
475#define ATAPI_SOFT_RESET_CMD 0x08\r
476#define ATAPI_PACKET_CMD 0xA0\r
477#define PACKET_CMD 0xA0\r
478#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1\r
479#define ATAPI_SERVICE_CMD 0xA2\r
480\r
481//\r
482// ATAPI Packet Command\r
483//\r
484#pragma pack(1)\r
485\r
486typedef struct {\r
487 UINT8 opcode;\r
488 UINT8 reserved_1;\r
489 UINT8 reserved_2;\r
490 UINT8 reserved_3;\r
491 UINT8 reserved_4;\r
492 UINT8 reserved_5;\r
493 UINT8 reserved_6;\r
494 UINT8 reserved_7;\r
495 UINT8 reserved_8;\r
496 UINT8 reserved_9;\r
497 UINT8 reserved_10;\r
498 UINT8 reserved_11;\r
499} TEST_UNIT_READY_CMD;\r
500\r
501typedef struct {\r
502 UINT8 opcode;\r
503 UINT8 reserved_1 : 4;\r
504 UINT8 lun : 4;\r
505 UINT8 page_code;\r
506 UINT8 reserved_3;\r
507 UINT8 allocation_length;\r
508 UINT8 reserved_5;\r
509 UINT8 reserved_6;\r
510 UINT8 reserved_7;\r
511 UINT8 reserved_8;\r
512 UINT8 reserved_9;\r
513 UINT8 reserved_10;\r
514 UINT8 reserved_11;\r
515} INQUIRY_CMD;\r
516\r
517typedef struct {\r
518 UINT8 opcode;\r
519 UINT8 reserved_1 : 4;\r
520 UINT8 lun : 4;\r
521 UINT8 reserved_2;\r
522 UINT8 reserved_3;\r
523 UINT8 allocation_length;\r
524 UINT8 reserved_5;\r
525 UINT8 reserved_6;\r
526 UINT8 reserved_7;\r
527 UINT8 reserved_8;\r
528 UINT8 reserved_9;\r
529 UINT8 reserved_10;\r
530 UINT8 reserved_11;\r
531} REQUEST_SENSE_CMD;\r
532\r
533typedef struct {\r
534 UINT8 opcode;\r
535 UINT8 reserved_1 : 4;\r
536 UINT8 lun : 4;\r
537 UINT8 page_code : 4;\r
538 UINT8 page_control : 4;\r
539 UINT8 reserved_3;\r
540 UINT8 reserved_4;\r
541 UINT8 reserved_5;\r
542 UINT8 reserved_6;\r
543 UINT8 parameter_list_length_hi;\r
544 UINT8 parameter_list_length_lo;\r
545 UINT8 reserved_9;\r
546 UINT8 reserved_10;\r
547 UINT8 reserved_11;\r
548} MODE_SENSE_CMD;\r
549\r
550typedef struct {\r
551 UINT8 opcode;\r
552 UINT8 reserved_1 : 5;\r
553 UINT8 lun : 3;\r
554 UINT8 Lba0;\r
555 UINT8 Lba1;\r
556 UINT8 Lba2;\r
557 UINT8 Lba3;\r
558 UINT8 reserved_6;\r
559 UINT8 TranLen0;\r
560 UINT8 TranLen1;\r
561 UINT8 reserved_9;\r
562 UINT8 reserved_10;\r
563 UINT8 reserved_11;\r
564} READ10_CMD;\r
565\r
566typedef struct {\r
567 UINT8 opcode;\r
568 UINT8 reserved_1;\r
569 UINT8 reserved_2;\r
570 UINT8 reserved_3;\r
571 UINT8 reserved_4;\r
572 UINT8 reserved_5;\r
573 UINT8 reserved_6;\r
574 UINT8 allocation_length_hi;\r
575 UINT8 allocation_length_lo;\r
576 UINT8 reserved_9;\r
577 UINT8 reserved_10;\r
578 UINT8 reserved_11;\r
579} READ_FORMAT_CAP_CMD;\r
580\r
581typedef union {\r
582 UINT16 Data16[6];\r
583 TEST_UNIT_READY_CMD TestUnitReady;\r
584 READ10_CMD Read10;\r
585 REQUEST_SENSE_CMD RequestSence;\r
586 INQUIRY_CMD Inquiry;\r
587 MODE_SENSE_CMD ModeSense;\r
588 READ_FORMAT_CAP_CMD ReadFormatCapacity;\r
589} ATAPI_PACKET_COMMAND;\r
590\r
591typedef struct {\r
592 UINT32 RegionBaseAddr;\r
593 UINT16 ByteCount;\r
594 UINT16 EndOfTable;\r
595} IDE_DMA_PRD;\r
596\r
597#define MAX_DMA_EXT_COMMAND_SECTORS 0x10000\r
598#define MAX_DMA_COMMAND_SECTORS 0x100\r
599\r
600#pragma pack()\r
601\r
602//\r
603// Packet Command Code\r
604//\r
605#define TEST_UNIT_READY 0x00\r
606#define REZERO 0x01\r
607#define REQUEST_SENSE 0x03\r
608#define FORMAT_UNIT 0x04\r
609#define REASSIGN_BLOCKS 0x07\r
610#define INQUIRY 0x12\r
611#define START_STOP_UNIT 0x1B\r
612#define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E\r
613#define READ_FORMAT_CAPACITY 0x23\r
614#define OLD_FORMAT_UNIT 0x24\r
615#define READ_CAPACITY 0x25\r
616#define READ_10 0x28\r
617#define WRITE_10 0x2A\r
618#define SEEK 0x2B\r
619#define SEND_DIAGNOSTICS 0x3D\r
620#define WRITE_VERIFY 0x2E\r
621#define VERIFY 0x2F\r
622#define READ_DEFECT_DATA 0x37\r
623#define WRITE_BUFFER 0x38\r
624#define READ_BUFFER 0x3C\r
625#define READ_LONG 0x3E\r
626#define WRITE_LONG 0x3F\r
627#define MODE_SELECT 0x55\r
628#define MODE_SENSE 0x5A\r
629#define READ_12 0xA8\r
630#define WRITE_12 0xAA\r
631#define MAX_ATAPI_BYTE_COUNT (0xfffe)\r
632\r
633//\r
634// Sense Key\r
635//\r
636#define REQUEST_SENSE_ERROR (0x70)\r
637#define SK_NO_SENSE (0x0)\r
638#define SK_RECOVERY_ERROR (0x1)\r
639#define SK_NOT_READY (0x2)\r
640#define SK_MEDIUM_ERROR (0x3)\r
641#define SK_HARDWARE_ERROR (0x4)\r
642#define SK_ILLEGAL_REQUEST (0x5)\r
643#define SK_UNIT_ATTENTION (0x6)\r
644#define SK_DATA_PROTECT (0x7)\r
645#define SK_BLANK_CHECK (0x8)\r
646#define SK_VENDOR_SPECIFIC (0x9)\r
647#define SK_RESERVED_A (0xA)\r
648#define SK_ABORT (0xB)\r
649#define SK_RESERVED_C (0xC)\r
650#define SK_OVERFLOW (0xD)\r
651#define SK_MISCOMPARE (0xE)\r
652#define SK_RESERVED_F (0xF)\r
653\r
654//\r
655// Additional Sense Codes\r
656//\r
657#define ASC_NOT_READY (0x04)\r
658#define ASC_MEDIA_ERR1 (0x10)\r
659#define ASC_MEDIA_ERR2 (0x11)\r
660#define ASC_MEDIA_ERR3 (0x14)\r
661#define ASC_MEDIA_ERR4 (0x30)\r
662#define ASC_MEDIA_UPSIDE_DOWN (0x06)\r
663#define ASC_INVALID_CMD (0x20)\r
664#define ASC_LBA_OUT_OF_RANGE (0x21)\r
665#define ASC_INVALID_FIELD (0x24)\r
666#define ASC_WRITE_PROTECTED (0x27)\r
667#define ASC_MEDIA_CHANGE (0x28)\r
668#define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */\r
669#define ASC_ILLEGAL_FIELD (0x26)\r
670#define ASC_NO_MEDIA (0x3A)\r
671#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r
672\r
673//\r
674// Additional Sense Code Qualifier\r
675//\r
676#define ASCQ_IN_PROGRESS (0x01)\r
677\r
678#define SETFEATURE TRUE\r
679#define CLEARFEATURE FALSE\r
680\r
681//\r
682// ATAPI Data structure\r
683//\r
684#pragma pack(1)\r
685\r
686typedef struct {\r
687 UINT8 peripheral_type;\r
688 UINT8 RMB;\r
689 UINT8 version;\r
690 UINT8 response_data_format;\r
691 UINT8 addnl_length;\r
692 UINT8 reserved_5;\r
693 UINT8 reserved_6;\r
694 UINT8 reserved_7;\r
695 UINT8 vendor_info[8];\r
696 UINT8 product_id[12];\r
697 UINT8 eeprom_product_code[4];\r
698 UINT8 firmware_rev_level[4];\r
699 UINT8 firmware_sub_rev_level[1];\r
700 UINT8 reserved_37;\r
701 UINT8 reserved_38;\r
702 UINT8 reserved_39;\r
703 UINT8 max_capacity_hi;\r
704 UINT8 max_capacity_mid;\r
705 UINT8 max_capacity_lo;\r
706 UINT8 reserved_43_95[95 - 43 + 1];\r
707} INQUIRY_DATA;\r
708\r
709typedef struct {\r
710 UINT8 peripheral_type;\r
711 UINT8 RMB;\r
712 UINT8 version;\r
713 UINT8 response_data_format;\r
714 UINT8 addnl_length;\r
715 UINT8 reserved_5;\r
716 UINT8 reserved_6;\r
717 UINT8 reserved_7;\r
718 UINT8 vendor_info[8];\r
719 UINT8 product_id[16];\r
720 UINT8 product_revision_level[4];\r
721 UINT8 vendor_specific[20];\r
722 UINT8 reserved_56_95[40];\r
723} CDROM_INQUIRY_DATA;\r
724\r
725typedef struct {\r
726 UINT8 error_code : 7;\r
727 UINT8 valid : 1;\r
728 UINT8 reserved_1;\r
729 UINT8 sense_key : 4;\r
730 UINT8 reserved_21 : 1;\r
731 UINT8 ILI : 1;\r
732 UINT8 reserved_22 : 2;\r
733 UINT8 vendor_specific_3;\r
734 UINT8 vendor_specific_4;\r
735 UINT8 vendor_specific_5;\r
736 UINT8 vendor_specific_6;\r
737 UINT8 addnl_sense_length; // n - 7\r
738 UINT8 vendor_specific_8;\r
739 UINT8 vendor_specific_9;\r
740 UINT8 vendor_specific_10;\r
741 UINT8 vendor_specific_11;\r
742 UINT8 addnl_sense_code; // mandatory\r
743 UINT8 addnl_sense_code_qualifier; // mandatory\r
744 UINT8 field_replaceable_unit_code; // optional\r
745 UINT8 reserved_15;\r
746 UINT8 reserved_16;\r
747 UINT8 reserved_17;\r
748 //\r
749 // Followed by additional sense bytes : FIXME\r
750 //\r
751} REQUEST_SENSE_DATA;\r
752\r
753typedef struct {\r
754 UINT8 LastLba3;\r
755 UINT8 LastLba2;\r
756 UINT8 LastLba1;\r
757 UINT8 LastLba0;\r
758 UINT8 BlockSize3;\r
759 UINT8 BlockSize2;\r
760 UINT8 BlockSize1;\r
761 UINT8 BlockSize0;\r
762} READ_CAPACITY_DATA;\r
763\r
764typedef struct {\r
765 UINT8 reserved_0;\r
766 UINT8 reserved_1;\r
767 UINT8 reserved_2;\r
768 UINT8 Capacity_Length;\r
769 UINT8 LastLba3;\r
770 UINT8 LastLba2;\r
771 UINT8 LastLba1;\r
772 UINT8 LastLba0;\r
773 UINT8 DesCode : 2;\r
774 UINT8 reserved_9 : 6;\r
775 UINT8 BlockSize2;\r
776 UINT8 BlockSize1;\r
777 UINT8 BlockSize0;\r
778} READ_FORMAT_CAPACITY_DATA;\r
779\r
780#pragma pack()\r
781\r
782//\r
783// PIO mode definition\r
784//\r
785typedef enum {\r
786 ATA_PIO_MODE_BELOW_2,\r
787 ATA_PIO_MODE_2,\r
788 ATA_PIO_MODE_3,\r
789 ATA_PIO_MODE_4\r
790} ATA_PIO_MODE;\r
791\r
792//\r
793// Multi word DMA definition\r
794//\r
795typedef enum {\r
796 ATA_MDMA_MODE_0,\r
797 ATA_MDMA_MODE_1,\r
798 ATA_MDMA_MODE_2\r
799} ATA_MDMA_MODE;\r
800\r
801//\r
802// UDMA mode definition\r
803//\r
804typedef enum {\r
805 ATA_UDMA_MODE_0,\r
806 ATA_UDMA_MODE_1,\r
807 ATA_UDMA_MODE_2,\r
808 ATA_UDMA_MODE_3,\r
809 ATA_UDMA_MODE_4,\r
810 ATA_UDMA_MODE_5\r
811} ATA_UDMA_MODE;\r
812\r
813#define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00\r
814#define ATA_MODE_CATEGORY_FLOW_PIO 0x01\r
815#define ATA_MODE_CATEGORY_MDMA 0x04\r
816#define ATA_MODE_CATEGORY_UDMA 0x08\r
817\r
818#pragma pack(1)\r
819\r
820typedef struct {\r
821 UINT8 ModeNumber : 3;\r
822 UINT8 ModeCategory : 5;\r
823} ATA_TRANSFER_MODE;\r
824\r
825typedef struct {\r
826 UINT8 Sector;\r
827 UINT8 Heads;\r
828 UINT8 MultipleSector;\r
829} ATA_DRIVE_PARMS;\r
830\r
831#pragma pack()\r
832//\r
833// IORDY Sample Point field value\r
834//\r
835#define ISP_5_CLK 0\r
836#define ISP_4_CLK 1\r
837#define ISP_3_CLK 2\r
838#define ISP_2_CLK 3\r
839\r
840//\r
841// Recovery Time field value\r
842//\r
843#define RECVY_4_CLK 0\r
844#define RECVY_3_CLK 1\r
845#define RECVY_2_CLK 2\r
846#define RECVY_1_CLK 3\r
847\r
848//\r
849// Slave IDE Timing Register Enable\r
850//\r
851#define SITRE bit14\r
852\r
853//\r
854// DMA Timing Enable Only Select 1\r
855//\r
856#define DTE1 bit7\r
857\r
858//\r
859// Pre-fetch and Posting Enable Select 1\r
860//\r
861#define PPE1 bit6\r
862\r
863//\r
864// IORDY Sample Point Enable Select 1\r
865//\r
866#define IE1 bit5\r
867\r
868//\r
869// Fast Timing Bank Drive Select 1\r
870//\r
871#define TIME1 bit4\r
872\r
873//\r
874// DMA Timing Enable Only Select 0\r
875//\r
876#define DTE0 bit3\r
877\r
878//\r
879// Pre-fetch and Posting Enable Select 0\r
880//\r
881#define PPE0 bit2\r
882\r
883//\r
884// IOREY Sample Point Enable Select 0\r
885//\r
886#define IE0 bit1\r
887\r
888//\r
889// Fast Timing Bank Drive Select 0\r
890//\r
891#define TIME0 bit0\r
892\r
893#endif\r