ed72955c |
1 | /** @file\r |
2 | Header file for IDE Bus Driver's Data Structures\r |
878ddf1f |
3 | \r |
ed72955c |
4 | Copyright (c) 2006, Intel Corporation \r |
5 | All rights reserved. This program and the accompanying materials \r |
6 | are licensed and made available under the terms and conditions of the BSD License \r |
7 | which accompanies this distribution. The full text of the license may be found at \r |
8 | http://opensource.org/licenses/bsd-license.php \r |
878ddf1f |
9 | \r |
ed72955c |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
878ddf1f |
12 | \r |
ed72955c |
13 | **/\r |
878ddf1f |
14 | \r |
878ddf1f |
15 | #ifndef _IDE_DATA_H\r |
16 | #define _IDE_DATA_H\r |
17 | \r |
18 | //\r |
19 | // bit definition\r |
20 | //\r |
21 | #define bit0 (1 << 0)\r |
22 | #define bit1 (1 << 1)\r |
23 | #define bit2 (1 << 2)\r |
24 | #define bit3 (1 << 3)\r |
25 | #define bit4 (1 << 4)\r |
26 | #define bit5 (1 << 5)\r |
27 | #define bit6 (1 << 6)\r |
28 | #define bit7 (1 << 7)\r |
29 | #define bit8 (1 << 8)\r |
30 | #define bit9 (1 << 9)\r |
31 | #define bit10 (1 << 10)\r |
32 | #define bit11 (1 << 11)\r |
33 | #define bit12 (1 << 12)\r |
34 | #define bit13 (1 << 13)\r |
35 | #define bit14 (1 << 14)\r |
36 | #define bit15 (1 << 15)\r |
37 | #define bit16 (1 << 16)\r |
38 | #define bit17 (1 << 17)\r |
39 | #define bit18 (1 << 18)\r |
40 | #define bit19 (1 << 19)\r |
41 | #define bit20 (1 << 20)\r |
42 | #define bit21 (1 << 21)\r |
43 | #define bit22 (1 << 22)\r |
44 | #define bit23 (1 << 23)\r |
45 | #define bit24 (1 << 24)\r |
46 | #define bit25 (1 << 25)\r |
47 | #define bit26 (1 << 26)\r |
48 | #define bit27 (1 << 27)\r |
49 | #define bit28 (1 << 28)\r |
50 | #define bit29 (1 << 29)\r |
51 | #define bit30 (1 << 30)\r |
52 | #define bit31 (1 << 31)\r |
53 | \r |
54 | //\r |
55 | // common constants\r |
56 | //\r |
57 | #define STALL_1_MILLI_SECOND 1000 // stall 1 ms\r |
58 | #define STALL_1_SECOND 1000000 // stall 1 second\r |
59 | typedef enum {\r |
60 | IdePrimary = 0,\r |
61 | IdeSecondary = 1,\r |
62 | IdeMaxChannel = 2\r |
63 | } EFI_IDE_CHANNEL;\r |
64 | \r |
65 | typedef enum {\r |
66 | IdeMaster = 0,\r |
67 | IdeSlave = 1,\r |
68 | IdeMaxDevice = 2\r |
69 | } EFI_IDE_DEVICE;\r |
70 | \r |
71 | typedef enum {\r |
72 | IdeMagnetic, /* ZIP Drive or LS120 Floppy Drive */\r |
73 | IdeCdRom, /* ATAPI CDROM */\r |
74 | IdeHardDisk, /* Hard Disk */\r |
75 | Ide48bitAddressingHardDisk, /* Hard Disk larger than 120GB */\r |
76 | IdeUnknown\r |
77 | } IDE_DEVICE_TYPE;\r |
78 | \r |
79 | //\r |
80 | // IDE Registers\r |
81 | //\r |
82 | typedef union {\r |
83 | UINT16 Command; /* when write */\r |
84 | UINT16 Status; /* when read */\r |
85 | } IDE_CMD_OR_STATUS;\r |
86 | \r |
87 | typedef union {\r |
88 | UINT16 Error; /* when read */\r |
89 | UINT16 Feature; /* when write */\r |
90 | } IDE_ERROR_OR_FEATURE;\r |
91 | \r |
92 | typedef union {\r |
93 | UINT16 AltStatus; /* when read */\r |
94 | UINT16 DeviceControl; /* when write */\r |
95 | } IDE_AltStatus_OR_DeviceControl;\r |
96 | \r |
97 | //\r |
98 | // IDE registers set\r |
99 | //\r |
100 | typedef struct {\r |
101 | UINT16 Data;\r |
102 | IDE_ERROR_OR_FEATURE Reg1;\r |
103 | UINT16 SectorCount;\r |
104 | UINT16 SectorNumber;\r |
105 | UINT16 CylinderLsb;\r |
106 | UINT16 CylinderMsb;\r |
107 | UINT16 Head;\r |
108 | IDE_CMD_OR_STATUS Reg;\r |
109 | \r |
110 | IDE_AltStatus_OR_DeviceControl Alt;\r |
111 | UINT16 DriveAddress;\r |
112 | \r |
113 | UINT16 MasterSlave;\r |
114 | UINT16 BusMasterBaseAddr;\r |
115 | } IDE_BASE_REGISTERS;\r |
116 | \r |
117 | //\r |
118 | // IDE registers' base addresses\r |
119 | //\r |
120 | typedef struct {\r |
121 | UINT16 CommandBlockBaseAddr;\r |
122 | UINT16 ControlBlockBaseAddr;\r |
123 | UINT16 BusMasterBaseAddr;\r |
124 | } IDE_REGISTERS_BASE_ADDR;\r |
125 | \r |
126 | //\r |
127 | // Bit definitions in Programming Interface byte of the Class Code field\r |
128 | // in PCI IDE controller's Configuration Space\r |
129 | //\r |
130 | #define IDE_PRIMARY_OPERATING_MODE bit0\r |
131 | #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1\r |
132 | #define IDE_SECONDARY_OPERATING_MODE bit2\r |
133 | #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3\r |
134 | \r |
135 | //\r |
136 | // IDE registers bit definitions\r |
137 | //\r |
138 | \r |
139 | //\r |
140 | // Err Reg\r |
141 | //\r |
142 | #define BBK_ERR bit7 /* Bad block detected */\r |
143 | #define UNC_ERR bit6 /* Uncorrectable Data */\r |
144 | #define MC_ERR bit5 /* Media Change */\r |
145 | #define IDNF_ERR bit4 /* ID Not Found */\r |
146 | #define MCR_ERR bit3 /* Media Change Requested */\r |
147 | #define ABRT_ERR bit2 /* Aborted Command */\r |
148 | #define TK0NF_ERR bit1 /* Track 0 Not Found */\r |
149 | #define AMNF_ERR bit0 /* Address Mark Not Found */\r |
150 | \r |
151 | //\r |
152 | // Device/Head Reg\r |
153 | //\r |
154 | #define LBA_MODE bit6\r |
155 | #define DEV bit4\r |
156 | #define HS3 bit3\r |
157 | #define HS2 bit2\r |
158 | #define HS1 bit1\r |
159 | #define HS0 bit0\r |
160 | #define CHS_MODE (0)\r |
161 | #define DRV0 (0)\r |
162 | #define DRV1 (1)\r |
163 | #define MST_DRV DRV0\r |
164 | #define SLV_DRV DRV1\r |
165 | \r |
166 | //\r |
167 | // Status Reg\r |
168 | //\r |
169 | #define BSY bit7 /* Controller Busy */\r |
170 | #define DRDY bit6 /* Drive Ready */\r |
171 | #define DWF bit5 /* Drive Write Fault */\r |
172 | #define DSC bit4 /* Disk Seek Complete */\r |
173 | #define DRQ bit3 /* Data Request */\r |
174 | #define CORR bit2 /* Corrected Data */\r |
175 | #define IDX bit1 /* Index */\r |
176 | #define ERR bit0 /* Error */\r |
177 | \r |
178 | //\r |
179 | // Device Control Reg\r |
180 | //\r |
181 | #define SRST bit2 /* Software Reset */\r |
182 | #define IEN_L bit1 /* Interrupt Enable #*/\r |
183 | \r |
184 | //\r |
185 | // Bus Master Reg\r |
186 | //\r |
187 | #define BMIC_nREAD bit3\r |
188 | #define BMIC_START bit0\r |
189 | #define BMIS_INTERRUPT bit2\r |
190 | #define BMIS_ERROR bit1\r |
191 | \r |
192 | #define BMICP_OFFSET 0x00\r |
193 | #define BMISP_OFFSET 0x02\r |
194 | #define BMIDP_OFFSET 0x04\r |
195 | #define BMICS_OFFSET 0x08\r |
196 | #define BMISS_OFFSET 0x0A\r |
197 | #define BMIDS_OFFSET 0x0C\r |
198 | \r |
199 | //\r |
200 | // Time Out Value For IDE Device Polling\r |
201 | //\r |
202 | \r |
203 | //\r |
204 | // ATATIMEOUT is used for waiting time out for ATA device\r |
205 | //\r |
206 | \r |
207 | //\r |
208 | // 1 second\r |
209 | //\r |
210 | #define ATATIMEOUT 1000 \r |
211 | \r |
212 | //\r |
213 | // ATAPITIMEOUT is used for waiting operation\r |
214 | // except read and write time out for ATAPI device\r |
215 | //\r |
216 | \r |
217 | //\r |
218 | // 1 second\r |
219 | //\r |
220 | #define ATAPITIMEOUT 1000 \r |
221 | \r |
222 | //\r |
223 | // ATAPILONGTIMEOUT is used for waiting read and\r |
224 | // write operation timeout for ATAPI device\r |
225 | //\r |
226 | \r |
227 | //\r |
228 | // 2 seconds\r |
229 | //\r |
230 | #define CDROMLONGTIMEOUT 2000 \r |
231 | \r |
232 | //\r |
233 | // 5 seconds\r |
234 | //\r |
235 | #define ATAPILONGTIMEOUT 5000 \r |
236 | \r |
237 | //\r |
238 | // ATA Commands Code\r |
239 | //\r |
240 | #define ATA_INITIALIZE_DEVICE 0x91\r |
241 | \r |
242 | //\r |
243 | // Class 1\r |
244 | //\r |
245 | #define IDENTIFY_DRIVE_CMD 0xec\r |
246 | #define READ_BUFFER_CMD 0xe4\r |
247 | #define READ_SECTORS_CMD 0x20\r |
248 | #define READ_SECTORS_WITH_RETRY_CMD 0x21\r |
249 | #define READ_LONG_CMD 0x22\r |
250 | #define READ_LONG_WITH_RETRY_CMD 0x23\r |
251 | //\r |
252 | // Class 1 - Atapi6 enhanced commands\r |
253 | //\r |
254 | #define READ_SECTORS_EXT_CMD 0x24\r |
255 | \r |
256 | //\r |
257 | // Class 2\r |
258 | //\r |
259 | #define FORMAT_TRACK_CMD 0x50\r |
260 | #define WRITE_BUFFER_CMD 0xe8\r |
261 | #define WRITE_SECTORS_CMD 0x30\r |
262 | #define WRITE_SECTORS_WITH_RETRY_CMD 0x31\r |
263 | #define WRITE_LONG_CMD 0x32\r |
264 | #define WRITE_LONG_WITH_RETRY_CMD 0x33\r |
265 | #define WRITE_VERIFY_CMD 0x3c\r |
266 | //\r |
267 | // Class 2 - Atapi6 enhanced commands\r |
268 | //\r |
269 | #define WRITE_SECTORS_EXT_CMD 0x34\r |
270 | \r |
271 | //\r |
272 | // Class 3\r |
273 | //\r |
274 | #define ACK_MEDIA_CHANGE_CMD 0xdb\r |
275 | #define BOOT_POST_BOOT_CMD 0xdc\r |
276 | #define BOOT_PRE_BOOT_CMD 0xdd\r |
277 | #define CHECK_POWER_MODE_CMD 0x98\r |
278 | #define CHECK_POWER_MODE_CMD_ALIAS 0xe5\r |
279 | #define DOOR_LOCK_CMD 0xde\r |
280 | #define DOOR_UNLOCK_CMD 0xdf\r |
281 | #define EXEC_DRIVE_DIAG_CMD 0x90\r |
282 | #define IDLE_CMD_ALIAS 0x97\r |
283 | #define IDLE_CMD 0xe3\r |
284 | #define IDLE_IMMEDIATE_CMD 0x95\r |
285 | #define IDLE_IMMEDIATE_CMD_ALIAS 0xe1\r |
286 | #define INIT_DRIVE_PARAM_CMD 0x91\r |
287 | #define RECALIBRATE_CMD 0x10 /* aliased to 1x */\r |
288 | #define READ_DRIVE_STATE_CMD 0xe9\r |
289 | #define SET_MULTIPLE_MODE_CMD 0xC6\r |
290 | #define READ_DRIVE_STATE_CMD 0xe9\r |
291 | #define READ_VERIFY_CMD 0x40\r |
292 | #define READ_VERIFY_WITH_RETRY_CMD 0x41\r |
293 | #define SEEK_CMD 0x70 /* aliased to 7x */\r |
294 | #define SET_FEATURES_CMD 0xef\r |
295 | #define STANDBY_CMD 0x96\r |
296 | #define STANDBY_CMD_ALIAS 0xe2\r |
297 | #define STANDBY_IMMEDIATE_CMD 0x94\r |
298 | #define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0\r |
299 | \r |
300 | //\r |
301 | // Class 4\r |
302 | //\r |
303 | #define READ_DMA_CMD 0xc8\r |
304 | #define READ_DMA_WITH_RETRY_CMD 0xc9\r |
305 | #define READ_DMA_EXT_CMD 0x25\r |
306 | #define WRITE_DMA_CMD 0xca\r |
307 | #define WRITE_DMA_WITH_RETRY_CMD 0xcb\r |
308 | #define WRITE_DMA_EXT_CMD 0x35\r |
309 | \r |
310 | //\r |
311 | // Class 5\r |
312 | //\r |
313 | #define READ_MULTIPLE_CMD 0xc4\r |
314 | #define REST_CMD 0xe7\r |
315 | #define RESTORE_DRIVE_STATE_CMD 0xea\r |
316 | #define SET_SLEEP_MODE_CMD 0x99\r |
317 | #define SET_SLEEP_MODE_CMD_ALIAS 0xe6\r |
318 | #define WRITE_MULTIPLE_CMD 0xc5\r |
319 | #define WRITE_SAME_CMD 0xe9\r |
320 | \r |
321 | //\r |
322 | // Class 6 - Host protected area access feature set\r |
323 | //\r |
324 | #define READ_NATIVE_MAX_ADDRESS_CMD 0xf8\r |
325 | #define SET_MAX_ADDRESS_CMD 0xf9\r |
326 | \r |
327 | //\r |
328 | // Class 6 - ATA/ATAPI-6 enhanced commands\r |
329 | //\r |
330 | #define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27\r |
331 | #define SET_MAX_ADDRESS_CMD_EXT 0x37\r |
332 | \r |
333 | //\r |
334 | // Class 6 - SET_MAX related sub command (in feature register)\r |
335 | //\r |
336 | #define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00\r |
337 | #define PARTIES_SET_PASSWORD_SUB_CMD 0x01\r |
338 | #define PARTIES_LOCK_SUB_CMD 0x02\r |
339 | #define PARTIES_UNLOCK_SUB_CMD 0x03\r |
340 | #define PARTIES_FREEZE_SUB_CMD 0x04\r |
341 | \r |
342 | //\r |
343 | // S.M.A.R.T\r |
344 | //\r |
345 | #define ATA_SMART_CMD 0xb0\r |
346 | #define ATA_CONSTANT_C2 0xc2\r |
347 | #define ATA_CONSTANT_4F 0x4f\r |
348 | #define ATA_SMART_ENABLE_OPERATION 0xd8\r |
349 | #define ATA_SMART_RETURN_STATUS 0xda\r |
350 | \r |
351 | //\r |
352 | // Error codes for Exec Drive Diag\r |
353 | //\r |
354 | #define DRIV_DIAG_NO_ERROR (0x01)\r |
355 | #define DRIV_DIAG_FORMATTER_ERROR (0x02)\r |
356 | #define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)\r |
357 | #define DRIV_DIAG_ECC_CKT_ERRROR (0x04)\r |
358 | #define DRIV_DIAG_UP_ERROR (0x05)\r |
359 | #define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */\r |
360 | \r |
361 | //\r |
362 | // Codes for Format Track\r |
363 | //\r |
364 | #define FORMAT_GOOD_SECTOR (0x00)\r |
365 | #define FORMAT_SUSPEND_ALLOC (0x01)\r |
366 | #define FORMAT_REALLOC_SECTOR (0x02)\r |
367 | #define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)\r |
368 | \r |
369 | //\r |
370 | // IDE_IDENTIFY bits\r |
371 | // config bits :\r |
372 | //\r |
373 | #define ID_CONFIG_RESERVED0 bit0\r |
374 | #define ID_CONFIG_HARD_SECTORED_DRIVE bit1\r |
375 | #define ID_CONFIG_SOFT_SECTORED_DRIVE bit2\r |
376 | #define ID_CONFIG_NON_MFM bit3\r |
377 | #define ID_CONFIG_15uS_HEAD_SWITCHING bit4\r |
378 | #define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5\r |
379 | #define ID_CONFIG_HARD_DRIVE bit6\r |
380 | #define ID_CONFIG_CHANGEABLE_MEDIUM bit7\r |
381 | #define ID_CONFIG_DATA_RATE_TO_5MHZ bit8\r |
382 | #define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9\r |
383 | #define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10\r |
384 | #define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11\r |
385 | #define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12\r |
386 | #define ID_CONFIG_TRACK_OFFSET_AVAIL bit13\r |
387 | #define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14\r |
388 | #define ID_CONFIG_RESERVED1 bit15\r |
389 | \r |
390 | #define ID_DOUBLE_WORD_IO_POSSIBLE bit01\r |
391 | #define ID_LBA_SUPPORTED bit9\r |
392 | #define ID_DMA_SUPPORTED bit8\r |
393 | \r |
394 | #define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)\r |
395 | #define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)\r |
396 | #define SET_FEATURE_TRANSFER_MODE (0x03)\r |
397 | #define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)\r |
398 | #define SET_FEATURE_DISABLE_RETRIES (0x33)\r |
399 | //\r |
400 | // for Read & Write Longs\r |
401 | //\r |
402 | #define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)\r |
403 | #define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)\r |
404 | #define SET_FEATURE_DISABLE_READ_AHEAD (0x55)\r |
405 | #define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)\r |
406 | #define SET_FEATURE_DISABLE_ECC (0x77)\r |
407 | #define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)\r |
408 | #define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)\r |
409 | #define SET_FEATURE_ENABLE_ECC (0x88)\r |
410 | #define SET_FEATURE_ENABLE_RETRIES (0x99)\r |
411 | #define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)\r |
412 | #define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)\r |
413 | #define SET_FEATURE_ALLOW_REST_MODE (0xac)\r |
414 | //\r |
415 | // for Read & Write Longs\r |
416 | //\r |
417 | #define SET_FEATURE_4BYTE_ECC (0xbb)\r |
418 | #define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)\r |
419 | #define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)\r |
420 | \r |
421 | #define BLOCK_TRANSFER_MODE (0x00)\r |
422 | #define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)\r |
423 | #define MULTI_WORD_DMA_TRANSFER_MODE (0x20)\r |
424 | #define TRANSFER_MODE_MASK (0x07) // 3 LSBs\r |
425 | \r |
426 | //\r |
427 | // Drive 0 - Head 0\r |
428 | //\r |
429 | #define DEFAULT_DRIVE (0x00)\r |
430 | #define DEFAULT_CMD (0xa0)\r |
431 | //\r |
432 | // default content of device control register, disable INT\r |
433 | //\r |
434 | #define DEFAULT_CTL (0x0a)\r |
435 | #define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)\r |
436 | \r |
437 | //\r |
438 | // ATAPI6 related data structure definition\r |
439 | //\r |
440 | \r |
441 | //\r |
442 | // The maximum sectors count in 28 bit addressing mode\r |
443 | //\r |
444 | #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff\r |
445 | \r |
446 | //\r |
447 | // Move the IDENTIFY section to DXE\Protocol\IdeControllerInit\r |
448 | //\r |
449 | \r |
450 | //\r |
451 | // ATAPI Command\r |
452 | //\r |
453 | #define ATAPI_SOFT_RESET_CMD 0x08\r |
454 | #define ATAPI_PACKET_CMD 0xA0\r |
455 | #define PACKET_CMD 0xA0\r |
456 | #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1\r |
457 | #define ATAPI_SERVICE_CMD 0xA2\r |
458 | \r |
459 | //\r |
460 | // ATAPI Packet Command\r |
461 | //\r |
462 | #pragma pack(1)\r |
463 | \r |
464 | typedef struct {\r |
465 | UINT8 opcode;\r |
466 | UINT8 reserved_1;\r |
467 | UINT8 reserved_2;\r |
468 | UINT8 reserved_3;\r |
469 | UINT8 reserved_4;\r |
470 | UINT8 reserved_5;\r |
471 | UINT8 reserved_6;\r |
472 | UINT8 reserved_7;\r |
473 | UINT8 reserved_8;\r |
474 | UINT8 reserved_9;\r |
475 | UINT8 reserved_10;\r |
476 | UINT8 reserved_11;\r |
477 | } TEST_UNIT_READY_CMD;\r |
478 | \r |
479 | typedef struct {\r |
480 | UINT8 opcode;\r |
481 | UINT8 reserved_1 : 4;\r |
482 | UINT8 lun : 4;\r |
483 | UINT8 page_code;\r |
484 | UINT8 reserved_3;\r |
485 | UINT8 allocation_length;\r |
486 | UINT8 reserved_5;\r |
487 | UINT8 reserved_6;\r |
488 | UINT8 reserved_7;\r |
489 | UINT8 reserved_8;\r |
490 | UINT8 reserved_9;\r |
491 | UINT8 reserved_10;\r |
492 | UINT8 reserved_11;\r |
493 | } INQUIRY_CMD;\r |
494 | \r |
495 | typedef struct {\r |
496 | UINT8 opcode;\r |
497 | UINT8 reserved_1 : 4;\r |
498 | UINT8 lun : 4;\r |
499 | UINT8 reserved_2;\r |
500 | UINT8 reserved_3;\r |
501 | UINT8 allocation_length;\r |
502 | UINT8 reserved_5;\r |
503 | UINT8 reserved_6;\r |
504 | UINT8 reserved_7;\r |
505 | UINT8 reserved_8;\r |
506 | UINT8 reserved_9;\r |
507 | UINT8 reserved_10;\r |
508 | UINT8 reserved_11;\r |
509 | } REQUEST_SENSE_CMD;\r |
510 | \r |
511 | typedef struct {\r |
512 | UINT8 opcode;\r |
513 | UINT8 reserved_1 : 4;\r |
514 | UINT8 lun : 4;\r |
515 | UINT8 page_code : 4;\r |
516 | UINT8 page_control : 4;\r |
517 | UINT8 reserved_3;\r |
518 | UINT8 reserved_4;\r |
519 | UINT8 reserved_5;\r |
520 | UINT8 reserved_6;\r |
521 | UINT8 parameter_list_length_hi;\r |
522 | UINT8 parameter_list_length_lo;\r |
523 | UINT8 reserved_9;\r |
524 | UINT8 reserved_10;\r |
525 | UINT8 reserved_11;\r |
526 | } MODE_SENSE_CMD;\r |
527 | \r |
528 | typedef struct {\r |
529 | UINT8 opcode;\r |
530 | UINT8 reserved_1 : 5;\r |
531 | UINT8 lun : 3;\r |
532 | UINT8 Lba0;\r |
533 | UINT8 Lba1;\r |
534 | UINT8 Lba2;\r |
535 | UINT8 Lba3;\r |
536 | UINT8 reserved_6;\r |
537 | UINT8 TranLen0;\r |
538 | UINT8 TranLen1;\r |
539 | UINT8 reserved_9;\r |
540 | UINT8 reserved_10;\r |
541 | UINT8 reserved_11;\r |
542 | } READ10_CMD;\r |
543 | \r |
544 | typedef struct {\r |
545 | UINT8 opcode;\r |
546 | UINT8 reserved_1;\r |
547 | UINT8 reserved_2;\r |
548 | UINT8 reserved_3;\r |
549 | UINT8 reserved_4;\r |
550 | UINT8 reserved_5;\r |
551 | UINT8 reserved_6;\r |
552 | UINT8 allocation_length_hi;\r |
553 | UINT8 allocation_length_lo;\r |
554 | UINT8 reserved_9;\r |
555 | UINT8 reserved_10;\r |
556 | UINT8 reserved_11;\r |
557 | } READ_FORMAT_CAP_CMD;\r |
558 | \r |
559 | typedef union {\r |
560 | UINT16 Data16[6];\r |
561 | TEST_UNIT_READY_CMD TestUnitReady;\r |
562 | READ10_CMD Read10;\r |
563 | REQUEST_SENSE_CMD RequestSence;\r |
564 | INQUIRY_CMD Inquiry;\r |
565 | MODE_SENSE_CMD ModeSense;\r |
566 | READ_FORMAT_CAP_CMD ReadFormatCapacity;\r |
567 | } ATAPI_PACKET_COMMAND;\r |
568 | \r |
569 | typedef struct {\r |
570 | UINT32 RegionBaseAddr;\r |
571 | UINT16 ByteCount;\r |
572 | UINT16 EndOfTable;\r |
573 | } IDE_DMA_PRD;\r |
574 | \r |
575 | #define MAX_DMA_EXT_COMMAND_SECTORS 0x10000\r |
576 | #define MAX_DMA_COMMAND_SECTORS 0x100\r |
577 | \r |
578 | #pragma pack()\r |
579 | \r |
580 | //\r |
581 | // Packet Command Code\r |
582 | //\r |
583 | #define TEST_UNIT_READY 0x00\r |
584 | #define REZERO 0x01\r |
585 | #define REQUEST_SENSE 0x03\r |
586 | #define FORMAT_UNIT 0x04\r |
587 | #define REASSIGN_BLOCKS 0x07\r |
588 | #define INQUIRY 0x12\r |
589 | #define START_STOP_UNIT 0x1B\r |
590 | #define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E\r |
591 | #define READ_FORMAT_CAPACITY 0x23\r |
592 | #define OLD_FORMAT_UNIT 0x24\r |
593 | #define READ_CAPACITY 0x25\r |
594 | #define READ_10 0x28\r |
595 | #define WRITE_10 0x2A\r |
596 | #define SEEK 0x2B\r |
597 | #define SEND_DIAGNOSTICS 0x3D\r |
598 | #define WRITE_VERIFY 0x2E\r |
599 | #define VERIFY 0x2F\r |
600 | #define READ_DEFECT_DATA 0x37\r |
601 | #define WRITE_BUFFER 0x38\r |
602 | #define READ_BUFFER 0x3C\r |
603 | #define READ_LONG 0x3E\r |
604 | #define WRITE_LONG 0x3F\r |
605 | #define MODE_SELECT 0x55\r |
606 | #define MODE_SENSE 0x5A\r |
607 | #define READ_12 0xA8\r |
608 | #define WRITE_12 0xAA\r |
609 | #define MAX_ATAPI_BYTE_COUNT (0xfffe)\r |
610 | \r |
611 | //\r |
612 | // Sense Key\r |
613 | //\r |
614 | #define REQUEST_SENSE_ERROR (0x70)\r |
615 | #define SK_NO_SENSE (0x0)\r |
616 | #define SK_RECOVERY_ERROR (0x1)\r |
617 | #define SK_NOT_READY (0x2)\r |
618 | #define SK_MEDIUM_ERROR (0x3)\r |
619 | #define SK_HARDWARE_ERROR (0x4)\r |
620 | #define SK_ILLEGAL_REQUEST (0x5)\r |
621 | #define SK_UNIT_ATTENTION (0x6)\r |
622 | #define SK_DATA_PROTECT (0x7)\r |
623 | #define SK_BLANK_CHECK (0x8)\r |
624 | #define SK_VENDOR_SPECIFIC (0x9)\r |
625 | #define SK_RESERVED_A (0xA)\r |
626 | #define SK_ABORT (0xB)\r |
627 | #define SK_RESERVED_C (0xC)\r |
628 | #define SK_OVERFLOW (0xD)\r |
629 | #define SK_MISCOMPARE (0xE)\r |
630 | #define SK_RESERVED_F (0xF)\r |
631 | \r |
632 | //\r |
633 | // Additional Sense Codes\r |
634 | //\r |
635 | #define ASC_NOT_READY (0x04)\r |
636 | #define ASC_MEDIA_ERR1 (0x10)\r |
637 | #define ASC_MEDIA_ERR2 (0x11)\r |
638 | #define ASC_MEDIA_ERR3 (0x14)\r |
639 | #define ASC_MEDIA_ERR4 (0x30)\r |
640 | #define ASC_MEDIA_UPSIDE_DOWN (0x06)\r |
641 | #define ASC_INVALID_CMD (0x20)\r |
642 | #define ASC_LBA_OUT_OF_RANGE (0x21)\r |
643 | #define ASC_INVALID_FIELD (0x24)\r |
644 | #define ASC_WRITE_PROTECTED (0x27)\r |
645 | #define ASC_MEDIA_CHANGE (0x28)\r |
646 | #define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */\r |
647 | #define ASC_ILLEGAL_FIELD (0x26)\r |
648 | #define ASC_NO_MEDIA (0x3A)\r |
649 | #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r |
650 | \r |
651 | //\r |
652 | // Additional Sense Code Qualifier\r |
653 | //\r |
654 | #define ASCQ_IN_PROGRESS (0x01)\r |
655 | \r |
656 | #define SETFEATURE TRUE\r |
657 | #define CLEARFEATURE FALSE\r |
658 | \r |
659 | //\r |
660 | // ATAPI Data structure\r |
661 | //\r |
662 | #pragma pack(1)\r |
663 | \r |
664 | typedef struct {\r |
665 | UINT8 peripheral_type;\r |
666 | UINT8 RMB;\r |
667 | UINT8 version;\r |
668 | UINT8 response_data_format;\r |
669 | UINT8 addnl_length;\r |
670 | UINT8 reserved_5;\r |
671 | UINT8 reserved_6;\r |
672 | UINT8 reserved_7;\r |
673 | UINT8 vendor_info[8];\r |
674 | UINT8 product_id[12];\r |
675 | UINT8 eeprom_product_code[4];\r |
676 | UINT8 firmware_rev_level[4];\r |
677 | UINT8 firmware_sub_rev_level[1];\r |
678 | UINT8 reserved_37;\r |
679 | UINT8 reserved_38;\r |
680 | UINT8 reserved_39;\r |
681 | UINT8 max_capacity_hi;\r |
682 | UINT8 max_capacity_mid;\r |
683 | UINT8 max_capacity_lo;\r |
684 | UINT8 reserved_43_95[95 - 43 + 1];\r |
685 | } INQUIRY_DATA;\r |
686 | \r |
687 | typedef struct {\r |
688 | UINT8 peripheral_type;\r |
689 | UINT8 RMB;\r |
690 | UINT8 version;\r |
691 | UINT8 response_data_format;\r |
692 | UINT8 addnl_length;\r |
693 | UINT8 reserved_5;\r |
694 | UINT8 reserved_6;\r |
695 | UINT8 reserved_7;\r |
696 | UINT8 vendor_info[8];\r |
697 | UINT8 product_id[16];\r |
698 | UINT8 product_revision_level[4];\r |
699 | UINT8 vendor_specific[20];\r |
700 | UINT8 reserved_56_95[40];\r |
701 | } CDROM_INQUIRY_DATA;\r |
702 | \r |
703 | typedef struct {\r |
704 | UINT8 error_code : 7;\r |
705 | UINT8 valid : 1;\r |
706 | UINT8 reserved_1;\r |
707 | UINT8 sense_key : 4;\r |
708 | UINT8 reserved_21 : 1;\r |
709 | UINT8 ILI : 1;\r |
710 | UINT8 reserved_22 : 2;\r |
711 | UINT8 vendor_specific_3;\r |
712 | UINT8 vendor_specific_4;\r |
713 | UINT8 vendor_specific_5;\r |
714 | UINT8 vendor_specific_6;\r |
715 | UINT8 addnl_sense_length; // n - 7\r |
716 | UINT8 vendor_specific_8;\r |
717 | UINT8 vendor_specific_9;\r |
718 | UINT8 vendor_specific_10;\r |
719 | UINT8 vendor_specific_11;\r |
720 | UINT8 addnl_sense_code; // mandatory\r |
721 | UINT8 addnl_sense_code_qualifier; // mandatory\r |
722 | UINT8 field_replaceable_unit_code; // optional\r |
723 | UINT8 reserved_15;\r |
724 | UINT8 reserved_16;\r |
725 | UINT8 reserved_17;\r |
726 | //\r |
727 | // Followed by additional sense bytes : FIXME\r |
728 | //\r |
729 | } REQUEST_SENSE_DATA;\r |
730 | \r |
731 | typedef struct {\r |
732 | UINT8 LastLba3;\r |
733 | UINT8 LastLba2;\r |
734 | UINT8 LastLba1;\r |
735 | UINT8 LastLba0;\r |
736 | UINT8 BlockSize3;\r |
737 | UINT8 BlockSize2;\r |
738 | UINT8 BlockSize1;\r |
739 | UINT8 BlockSize0;\r |
740 | } READ_CAPACITY_DATA;\r |
741 | \r |
742 | typedef struct {\r |
743 | UINT8 reserved_0;\r |
744 | UINT8 reserved_1;\r |
745 | UINT8 reserved_2;\r |
746 | UINT8 Capacity_Length;\r |
747 | UINT8 LastLba3;\r |
748 | UINT8 LastLba2;\r |
749 | UINT8 LastLba1;\r |
750 | UINT8 LastLba0;\r |
751 | UINT8 DesCode : 2;\r |
752 | UINT8 reserved_9 : 6;\r |
753 | UINT8 BlockSize2;\r |
754 | UINT8 BlockSize1;\r |
755 | UINT8 BlockSize0;\r |
756 | } READ_FORMAT_CAPACITY_DATA;\r |
757 | \r |
758 | #pragma pack()\r |
759 | \r |
760 | //\r |
761 | // PIO mode definition\r |
762 | //\r |
763 | typedef enum {\r |
764 | ATA_PIO_MODE_BELOW_2,\r |
765 | ATA_PIO_MODE_2,\r |
766 | ATA_PIO_MODE_3,\r |
767 | ATA_PIO_MODE_4\r |
768 | } ATA_PIO_MODE;\r |
769 | \r |
770 | //\r |
771 | // Multi word DMA definition\r |
772 | //\r |
773 | typedef enum {\r |
774 | ATA_MDMA_MODE_0,\r |
775 | ATA_MDMA_MODE_1,\r |
776 | ATA_MDMA_MODE_2\r |
777 | } ATA_MDMA_MODE;\r |
778 | \r |
779 | //\r |
780 | // UDMA mode definition\r |
781 | //\r |
782 | typedef enum {\r |
783 | ATA_UDMA_MODE_0,\r |
784 | ATA_UDMA_MODE_1,\r |
785 | ATA_UDMA_MODE_2,\r |
786 | ATA_UDMA_MODE_3,\r |
787 | ATA_UDMA_MODE_4,\r |
788 | ATA_UDMA_MODE_5\r |
789 | } ATA_UDMA_MODE;\r |
790 | \r |
791 | #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00\r |
792 | #define ATA_MODE_CATEGORY_FLOW_PIO 0x01\r |
793 | #define ATA_MODE_CATEGORY_MDMA 0x04\r |
794 | #define ATA_MODE_CATEGORY_UDMA 0x08\r |
795 | \r |
796 | #pragma pack(1)\r |
797 | \r |
798 | typedef struct {\r |
799 | UINT8 ModeNumber : 3;\r |
800 | UINT8 ModeCategory : 5;\r |
801 | } ATA_TRANSFER_MODE;\r |
802 | \r |
803 | typedef struct {\r |
804 | UINT8 Sector;\r |
805 | UINT8 Heads;\r |
806 | UINT8 MultipleSector;\r |
807 | } ATA_DRIVE_PARMS;\r |
808 | \r |
809 | #pragma pack()\r |
810 | //\r |
811 | // IORDY Sample Point field value\r |
812 | //\r |
813 | #define ISP_5_CLK 0\r |
814 | #define ISP_4_CLK 1\r |
815 | #define ISP_3_CLK 2\r |
816 | #define ISP_2_CLK 3\r |
817 | \r |
818 | //\r |
819 | // Recovery Time field value\r |
820 | //\r |
821 | #define RECVY_4_CLK 0\r |
822 | #define RECVY_3_CLK 1\r |
823 | #define RECVY_2_CLK 2\r |
824 | #define RECVY_1_CLK 3\r |
825 | \r |
826 | //\r |
827 | // Slave IDE Timing Register Enable\r |
828 | //\r |
829 | #define SITRE bit14\r |
830 | \r |
831 | //\r |
832 | // DMA Timing Enable Only Select 1\r |
833 | //\r |
834 | #define DTE1 bit7\r |
835 | \r |
836 | //\r |
837 | // Pre-fetch and Posting Enable Select 1\r |
838 | //\r |
839 | #define PPE1 bit6\r |
840 | \r |
841 | //\r |
842 | // IORDY Sample Point Enable Select 1\r |
843 | //\r |
844 | #define IE1 bit5\r |
845 | \r |
846 | //\r |
847 | // Fast Timing Bank Drive Select 1\r |
848 | //\r |
849 | #define TIME1 bit4\r |
850 | \r |
851 | //\r |
852 | // DMA Timing Enable Only Select 0\r |
853 | //\r |
854 | #define DTE0 bit3\r |
855 | \r |
856 | //\r |
857 | // Pre-fetch and Posting Enable Select 0\r |
858 | //\r |
859 | #define PPE0 bit2\r |
860 | \r |
861 | //\r |
862 | // IOREY Sample Point Enable Select 0\r |
863 | //\r |
864 | #define IE0 bit1\r |
865 | \r |
866 | //\r |
867 | // Fast Timing Bank Drive Select 0\r |
868 | //\r |
869 | #define TIME0 bit0\r |
870 | \r |
871 | #endif\r |