[mirror_edk2.git] / EmbeddedPkg / Drivers / DwEmmcDxe / DwEmmc.h

/** @file\r
*\r
*  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
\r
#ifndef __DWEMMC_H__\r
#define __DWEMMC_H__\r
\r
#include <Protocol/EmbeddedGpio.h>\r
\r
// DW MMC Registers\r
#define DWEMMC_CTRL             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)\r
#define DWEMMC_PWREN            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)\r
#define DWEMMC_CLKDIV           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)\r
#define DWEMMC_CLKSRC           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)\r
#define DWEMMC_CLKENA           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)\r
#define DWEMMC_TMOUT            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)\r
#define DWEMMC_CTYPE            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)\r
#define DWEMMC_BLKSIZ           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)\r
#define DWEMMC_BYTCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)\r
#define DWEMMC_INTMASK          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)\r
#define DWEMMC_CMDARG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)\r
#define DWEMMC_CMD              ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)\r
#define DWEMMC_RESP0            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)\r
#define DWEMMC_RESP1            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)\r
#define DWEMMC_RESP2            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)\r
#define DWEMMC_RESP3            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)\r
#define DWEMMC_RINTSTS          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)\r
#define DWEMMC_STATUS           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)\r
#define DWEMMC_FIFOTH           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)\r
#define DWEMMC_TCBCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x05c)\r
#define DWEMMC_TBBCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x060)\r
#define DWEMMC_DEBNCE           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)\r
#define DWEMMC_HCON             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x070)\r
#define DWEMMC_UHSREG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)\r
#define DWEMMC_BMOD             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)\r
#define DWEMMC_DBADDR           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)\r
#define DWEMMC_IDSTS            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)\r
#define DWEMMC_IDINTEN          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)\r
#define DWEMMC_DSCADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)\r
#define DWEMMC_BUFADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)\r
#define DWEMMC_CARDTHRCTL       ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)\r
#define DWEMMC_DATA             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X200)\r
\r
#define CMD_UPDATE_CLK                          0x80202000\r
#define CMD_START_BIT                           (1 << 31)\r
\r
#define MMC_8BIT_MODE                           (1 << 16)\r
\r
#define BIT_CMD_RESPONSE_EXPECT                 (1 << 6)\r
#define BIT_CMD_LONG_RESPONSE                   (1 << 7)\r
#define BIT_CMD_CHECK_RESPONSE_CRC              (1 << 8)\r
#define BIT_CMD_DATA_EXPECTED                   (1 << 9)\r
#define BIT_CMD_READ                            (0 << 10)\r
#define BIT_CMD_WRITE                           (1 << 10)\r
#define BIT_CMD_BLOCK_TRANSFER                  (0 << 11)\r
#define BIT_CMD_STREAM_TRANSFER                 (1 << 11)\r
#define BIT_CMD_SEND_AUTO_STOP                  (1 << 12)\r
#define BIT_CMD_WAIT_PRVDATA_COMPLETE           (1 << 13)\r
#define BIT_CMD_STOP_ABORT_CMD                  (1 << 14)\r
#define BIT_CMD_SEND_INIT                       (1 << 15)\r
#define BIT_CMD_UPDATE_CLOCK_ONLY               (1 << 21)\r
#define BIT_CMD_READ_CEATA_DEVICE               (1 << 22)\r
#define BIT_CMD_CCS_EXPECTED                    (1 << 23)\r
#define BIT_CMD_ENABLE_BOOT                     (1 << 24)\r
#define BIT_CMD_EXPECT_BOOT_ACK                 (1 << 25)\r
#define BIT_CMD_DISABLE_BOOT                    (1 << 26)\r
#define BIT_CMD_MANDATORY_BOOT                  (0 << 27)\r
#define BIT_CMD_ALTERNATE_BOOT                  (1 << 27)\r
#define BIT_CMD_VOLT_SWITCH                     (1 << 28)\r
#define BIT_CMD_USE_HOLD_REG                    (1 << 29)\r
#define BIT_CMD_START                           (1 << 31)\r
\r
#define DWEMMC_INT_EBE                          (1 << 15)       /* End-bit Err */\r
#define DWEMMC_INT_SBE                          (1 << 13)       /* Start-bit  Err */\r
#define DWEMMC_INT_HLE                          (1 << 12)       /* Hardware-lock Err */\r
#define DWEMMC_INT_FRUN                         (1 << 11)       /* FIFO UN/OV RUN */\r
#define DWEMMC_INT_DRT                          (1 << 9)        /* Data timeout */\r
#define DWEMMC_INT_RTO                          (1 << 8)        /* Response timeout */\r
#define DWEMMC_INT_DCRC                         (1 << 7)        /* Data CRC err */\r
#define DWEMMC_INT_RCRC                         (1 << 6)        /* Response CRC err */\r
#define DWEMMC_INT_RXDR                         (1 << 5)\r
#define DWEMMC_INT_TXDR                         (1 << 4)\r
#define DWEMMC_INT_DTO                          (1 << 3)        /* Data trans over */\r
#define DWEMMC_INT_CMD_DONE                     (1 << 2)\r
#define DWEMMC_INT_RE                           (1 << 1)\r
\r
#define DWEMMC_IDMAC_DES0_DIC                   (1 << 1)\r
#define DWEMMC_IDMAC_DES0_LD                    (1 << 2)\r
#define DWEMMC_IDMAC_DES0_FS                    (1 << 3)\r
#define DWEMMC_IDMAC_DES0_CH                    (1 << 4)\r
#define DWEMMC_IDMAC_DES0_ER                    (1 << 5)\r
#define DWEMMC_IDMAC_DES0_CES                   (1 << 30)\r
#define DWEMMC_IDMAC_DES0_OWN                   (1 << 31)\r
#define DWEMMC_IDMAC_DES1_BS1(x)                ((x) & 0x1fff)\r
#define DWEMMC_IDMAC_DES2_BS2(x)                (((x) & 0x1fff) << 13)\r
#define DWEMMC_IDMAC_SWRESET                    (1 << 0)\r
#define DWEMMC_IDMAC_FB                         (1 << 1)\r
#define DWEMMC_IDMAC_ENABLE                     (1 << 7)\r
\r
#define EMMC_FIX_RCA                            6\r
\r
/* bits in MMC0_CTRL */\r
#define DWEMMC_CTRL_RESET                       (1 << 0)\r
#define DWEMMC_CTRL_FIFO_RESET                  (1 << 1)\r
#define DWEMMC_CTRL_DMA_RESET                   (1 << 2)\r
#define DWEMMC_CTRL_INT_EN                      (1 << 4)\r
#define DWEMMC_CTRL_DMA_EN                      (1 << 5)\r
#define DWEMMC_CTRL_IDMAC_EN                    (1 << 25)\r
#define DWEMMC_CTRL_RESET_ALL                   (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)\r
\r
#define DWEMMC_STS_DATA_BUSY                    (1 << 9)\r
\r
#define DWEMMC_FIFO_TWMARK(x)                   (x & 0xfff)\r
#define DWEMMC_FIFO_RWMARK(x)                   ((x & 0x1ff) << 16)\r
#define DWEMMC_DMA_BURST_SIZE(x)                ((x & 0x7) << 28)\r
\r
#define DWEMMC_CARD_RD_THR(x)                   ((x & 0xfff) << 16)\r
#define DWEMMC_CARD_RD_THR_EN                   (1 << 0)\r
\r
#define DWEMMC_GET_HDATA_WIDTH(x)               (((x) >> 7) & 0x7)\r
\r
#endif  // __DWEMMC_H__\r
Commit	Line	Data
ee660531 LL	1	/** @file\r
	2	*\r
	3	* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.\r
	4	*\r
	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	*\r
	13	**/\r
	14	\r
	15	\r
	16	#ifndef __DWEMMC_H__\r
	17	#define __DWEMMC_H__\r
	18	\r
	19	#include <Protocol/EmbeddedGpio.h>\r
	20	\r
	21	// DW MMC Registers\r
	22	#define DWEMMC_CTRL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)\r
	23	#define DWEMMC_PWREN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)\r
	24	#define DWEMMC_CLKDIV ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)\r
	25	#define DWEMMC_CLKSRC ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)\r
	26	#define DWEMMC_CLKENA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)\r
	27	#define DWEMMC_TMOUT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)\r
	28	#define DWEMMC_CTYPE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)\r
	29	#define DWEMMC_BLKSIZ ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)\r
	30	#define DWEMMC_BYTCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)\r
	31	#define DWEMMC_INTMASK ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)\r
	32	#define DWEMMC_CMDARG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)\r
	33	#define DWEMMC_CMD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)\r
	34	#define DWEMMC_RESP0 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)\r
	35	#define DWEMMC_RESP1 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)\r
	36	#define DWEMMC_RESP2 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)\r
	37	#define DWEMMC_RESP3 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)\r
	38	#define DWEMMC_RINTSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)\r
	39	#define DWEMMC_STATUS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)\r
	40	#define DWEMMC_FIFOTH ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)\r
a58bfb37 JN	41	#define DWEMMC_TCBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x05c)\r
a58bfb37 JN	42	#define DWEMMC_TBBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x060)\r
ee660531	43	#define DWEMMC_DEBNCE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)\r
a58bfb37	44	#define DWEMMC_HCON ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x070)\r
ee660531 LL	45	#define DWEMMC_UHSREG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)\r
	46	#define DWEMMC_BMOD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)\r
	47	#define DWEMMC_DBADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)\r
	48	#define DWEMMC_IDSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)\r
	49	#define DWEMMC_IDINTEN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)\r
	50	#define DWEMMC_DSCADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)\r
	51	#define DWEMMC_BUFADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)\r
	52	#define DWEMMC_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)\r
a58bfb37	53	#define DWEMMC_DATA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X200)\r
ee660531 LL	54	\r
	55	#define CMD_UPDATE_CLK 0x80202000\r
	56	#define CMD_START_BIT (1 << 31)\r
	57	\r
	58	#define MMC_8BIT_MODE (1 << 16)\r
	59	\r
	60	#define BIT_CMD_RESPONSE_EXPECT (1 << 6)\r
	61	#define BIT_CMD_LONG_RESPONSE (1 << 7)\r
	62	#define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8)\r
	63	#define BIT_CMD_DATA_EXPECTED (1 << 9)\r
	64	#define BIT_CMD_READ (0 << 10)\r
	65	#define BIT_CMD_WRITE (1 << 10)\r
	66	#define BIT_CMD_BLOCK_TRANSFER (0 << 11)\r
	67	#define BIT_CMD_STREAM_TRANSFER (1 << 11)\r
	68	#define BIT_CMD_SEND_AUTO_STOP (1 << 12)\r
	69	#define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13)\r
	70	#define BIT_CMD_STOP_ABORT_CMD (1 << 14)\r
	71	#define BIT_CMD_SEND_INIT (1 << 15)\r
	72	#define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21)\r
	73	#define BIT_CMD_READ_CEATA_DEVICE (1 << 22)\r
	74	#define BIT_CMD_CCS_EXPECTED (1 << 23)\r
	75	#define BIT_CMD_ENABLE_BOOT (1 << 24)\r
	76	#define BIT_CMD_EXPECT_BOOT_ACK (1 << 25)\r
	77	#define BIT_CMD_DISABLE_BOOT (1 << 26)\r
	78	#define BIT_CMD_MANDATORY_BOOT (0 << 27)\r
	79	#define BIT_CMD_ALTERNATE_BOOT (1 << 27)\r
	80	#define BIT_CMD_VOLT_SWITCH (1 << 28)\r
	81	#define BIT_CMD_USE_HOLD_REG (1 << 29)\r
	82	#define BIT_CMD_START (1 << 31)\r
	83	\r
	84	#define DWEMMC_INT_EBE (1 << 15) /* End-bit Err */\r
	85	#define DWEMMC_INT_SBE (1 << 13) /* Start-bit Err */\r
	86	#define DWEMMC_INT_HLE (1 << 12) /* Hardware-lock Err */\r
	87	#define DWEMMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */\r
	88	#define DWEMMC_INT_DRT (1 << 9) /* Data timeout */\r
	89	#define DWEMMC_INT_RTO (1 << 8) /* Response timeout */\r
	90	#define DWEMMC_INT_DCRC (1 << 7) /* Data CRC err */\r
	91	#define DWEMMC_INT_RCRC (1 << 6) /* Response CRC err */\r
	92	#define DWEMMC_INT_RXDR (1 << 5)\r
	93	#define DWEMMC_INT_TXDR (1 << 4)\r
	94	#define DWEMMC_INT_DTO (1 << 3) /* Data trans over */\r
	95	#define DWEMMC_INT_CMD_DONE (1 << 2)\r
	96	#define DWEMMC_INT_RE (1 << 1)\r
	97	\r
	98	#define DWEMMC_IDMAC_DES0_DIC (1 << 1)\r
	99	#define DWEMMC_IDMAC_DES0_LD (1 << 2)\r
	100	#define DWEMMC_IDMAC_DES0_FS (1 << 3)\r
	101	#define DWEMMC_IDMAC_DES0_CH (1 << 4)\r
	102	#define DWEMMC_IDMAC_DES0_ER (1 << 5)\r
	103	#define DWEMMC_IDMAC_DES0_CES (1 << 30)\r
	104	#define DWEMMC_IDMAC_DES0_OWN (1 << 31)\r
	105	#define DWEMMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff)\r
	106	#define DWEMMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)\r
	107	#define DWEMMC_IDMAC_SWRESET (1 << 0)\r
	108	#define DWEMMC_IDMAC_FB (1 << 1)\r
	109	#define DWEMMC_IDMAC_ENABLE (1 << 7)\r
	110	\r
	111	#define EMMC_FIX_RCA 6\r
	112	\r
	113	/* bits in MMC0_CTRL */\r
	114	#define DWEMMC_CTRL_RESET (1 << 0)\r
	115	#define DWEMMC_CTRL_FIFO_RESET (1 << 1)\r
	116	#define DWEMMC_CTRL_DMA_RESET (1 << 2)\r
	117	#define DWEMMC_CTRL_INT_EN (1 << 4)\r
118	#define DWEMMC_CTRL_DMA_EN (1 << 5)\r
119	#define DWEMMC_CTRL_IDMAC_EN (1 << 25)\r
120	#define DWEMMC_CTRL_RESET_ALL (DWEMMC_CTRL_RESET \| DWEMMC_CTRL_FIFO_RESET \| DWEMMC_CTRL_DMA_RESET)\r
121	\r
122	#define DWEMMC_STS_DATA_BUSY (1 << 9)\r
123	\r
124	#define DWEMMC_FIFO_TWMARK(x) (x & 0xfff)\r
125	#define DWEMMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16)\r
126	#define DWEMMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28)\r
127	\r
128	#define DWEMMC_CARD_RD_THR(x) ((x & 0xfff) << 16)\r
129	#define DWEMMC_CARD_RD_THR_EN (1 << 0)\r
130	\r
a58bfb37 JN	131	#define DWEMMC_GET_HDATA_WIDTH(x) (((x) >> 7) & 0x7)\r
a58bfb37 JN	132	\r
ee660531	133	#endif // __DWEMMC_H__\r