[mirror_edk2.git] / EmbeddedPkg / Drivers / Lan9118Dxe / Lan9118DxeHw.h

/** @file\r
*\r
*  Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
*\r
*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#ifndef __LAN9118_DXE_HW_H__\r
#define __LAN9118_DXE_HW_H__\r
\r
/*------------------------------------------------------------------------------\r
  LAN9118 SMCS Registers\r
------------------------------------------------------------------------------*/\r
\r
// Base address as on the VE board\r
#define LAN9118_BA                            ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress))\r
\r
/* ------------- Tx and Rx Data and Status Memory Locations ------------------*/\r
#define LAN9118_RX_DATA                       (0x00000000 + LAN9118_BA)\r
#define LAN9118_RX_STATUS                     (0x00000040 + LAN9118_BA)\r
#define LAN9118_RX_STATUS_PEEK                (0x00000044 + LAN9118_BA)\r
#define LAN9118_TX_DATA                       (0x00000020 + LAN9118_BA)\r
#define LAN9118_TX_STATUS                     (0x00000048 + LAN9118_BA)\r
#define LAN9118_TX_STATUS_PEEK                (0x0000004C + LAN9118_BA)\r
\r
/* ------------- System Control and Status Registers -------------------------*/\r
#define LAN9118_ID_REV                        (0x00000050 + LAN9118_BA)    // Chip ID and Revision\r
#define LAN9118_IRQ_CFG                       (0x00000054 + LAN9118_BA)    // Interrupt Configuration\r
#define LAN9118_INT_STS                       (0x00000058 + LAN9118_BA)    // Interrupt Status\r
#define LAN9118_INT_EN                        (0x0000005C + LAN9118_BA)    // Interrupt Enable\r
//#define LAN9118_RESERVED                    (0x00000060)\r
#define LAN9118_BYTE_TEST                     (0x00000064 + LAN9118_BA)    // Byte Order Test\r
#define LAN9118_FIFO_INT                      (0x00000068 + LAN9118_BA)    // FIFO Level Interrupts\r
#define LAN9118_RX_CFG                        (0x0000006C + LAN9118_BA)    // Receive Configuration\r
#define LAN9118_TX_CFG                        (0x00000070 + LAN9118_BA)    // Transmit Configuration\r
#define LAN9118_HW_CFG                        (0x00000074 + LAN9118_BA)    // Hardware Configuration\r
#define LAN9118_RX_DP_CTL                     (0x00000078 + LAN9118_BA)    // Receive Data-Path Configuration\r
#define LAN9118_RX_FIFO_INF                   (0x0000007C + LAN9118_BA)    // Receive FIFO Information\r
#define LAN9118_TX_FIFO_INF                   (0x00000080 + LAN9118_BA)    // Transmit FIFO Information\r
#define LAN9118_PMT_CTRL                      (0x00000084 + LAN9118_BA)    // Power Management Control\r
#define LAN9118_GPIO_CFG                      (0x00000088 + LAN9118_BA)    // General Purpose IO Configuration\r
#define LAN9118_GPT_CFG                       (0x0000008C + LAN9118_BA)    // General Purpose Timer Configuration\r
#define LAN9118_GPT_CNT                       (0x00000090 + LAN9118_BA)    // General Purpose Timer Current Count\r
#define LAN9118_WORD_SWAP                     (0x00000098 + LAN9118_BA)    // Word Swap Control\r
#define LAN9118_FREE_RUN                      (0x0000009C + LAN9118_BA)    // Free-Run 25MHz Counter\r
#define LAN9118_RX_DROP                       (0x000000A0 + LAN9118_BA)    // Receiver Dropped Frames Counter\r
#define LAN9118_MAC_CSR_CMD                   (0x000000A4 + LAN9118_BA)    // MAC CSR Synchronizer Command\r
#define LAN9118_MAC_CSR_DATA                  (0x000000A8 + LAN9118_BA)    // MAC CSR Synchronizer Data\r
#define LAN9118_AFC_CFG                       (0x000000AC + LAN9118_BA)    // Automatic Flow Control Configuration\r
#define LAN9118_E2P_CMD                       (0x000000B0 + LAN9118_BA)    // EEPROM Command\r
#define LAN9118_E2P_DATA                      (0x000000B4 + LAN9118_BA)    // EEPROM Data\r
\r
/*\r
 * Required delays following write cycles (number of BYTE_TEST reads)\r
 * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
 * Where no delay listed, 0 has been assumed.\r
 */\r
#define LAN9118_RX_DATA_WR_DELAY              0\r
#define LAN9118_RX_STATUS_WR_DELAY            0\r
#define LAN9118_RX_STATUS_PEEK_WR_DELAY       0\r
#define LAN9118_TX_DATA_WR_DELAY              0\r
#define LAN9118_TX_STATUS_WR_DELAY            0\r
#define LAN9118_TX_STATUS_PEEK_WR_DELAY       0\r
#define LAN9118_ID_REV_WR_DELAY               0\r
#define LAN9118_IRQ_CFG_WR_DELAY              3\r
#define LAN9118_INT_STS_WR_DELAY              2\r
#define LAN9118_INT_EN_WR_DELAY               1\r
#define LAN9118_BYTE_TEST_WR_DELAY            0\r
#define LAN9118_FIFO_INT_WR_DELAY             1\r
#define LAN9118_RX_CFG_WR_DELAY               1\r
#define LAN9118_TX_CFG_WR_DELAY               1\r
#define LAN9118_HW_CFG_WR_DELAY               1\r
#define LAN9118_RX_DP_CTL_WR_DELAY            1\r
#define LAN9118_RX_FIFO_INF_WR_DELAY          0\r
#define LAN9118_TX_FIFO_INF_WR_DELAY          3\r
#define LAN9118_PMT_CTRL_WR_DELAY             7\r
#define LAN9118_GPIO_CFG_WR_DELAY             1\r
#define LAN9118_GPT_CFG_WR_DELAY              1\r
#define LAN9118_GPT_CNT_WR_DELAY              3\r
#define LAN9118_WORD_SWAP_WR_DELAY            1\r
#define LAN9118_FREE_RUN_WR_DELAY             4\r
#define LAN9118_RX_DROP_WR_DELAY              0\r
#define LAN9118_MAC_CSR_CMD_WR_DELAY          1\r
#define LAN9118_MAC_CSR_DATA_WR_DELAY         1\r
#define LAN9118_AFC_CFG_WR_DELAY              1\r
#define LAN9118_E2P_CMD_WR_DELAY              1\r
#define LAN9118_E2P_DATA_WR_DELAY             1\r
\r
/*\r
 * Required delays following read cycles (number of BYTE_TEST reads)\r
 * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
 * Where no delay listed, 0 has been assumed.\r
 */\r
#define LAN9118_RX_DATA_RD_DELAY              3\r
#define LAN9118_RX_STATUS_RD_DELAY            3\r
#define LAN9118_RX_STATUS_PEEK_RD_DELAY       0\r
#define LAN9118_TX_DATA_RD_DELAY              0\r
#define LAN9118_TX_STATUS_RD_DELAY            3\r
#define LAN9118_TX_STATUS_PEEK_RD_DELAY       0\r
#define LAN9118_ID_REV_RD_DELAY               0\r
#define LAN9118_IRQ_CFG_RD_DELAY              0\r
#define LAN9118_INT_STS_RD_DELAY              0\r
#define LAN9118_INT_EN_RD_DELAY               0\r
#define LAN9118_BYTE_TEST_RD_DELAY            0\r
#define LAN9118_FIFO_INT_RD_DELAY             0\r
#define LAN9118_RX_CFG_RD_DELAY               0\r
#define LAN9118_TX_CFG_RD_DELAY               0\r
#define LAN9118_HW_CFG_RD_DELAY               0\r
#define LAN9118_RX_DP_CTL_RD_DELAY            0\r
#define LAN9118_RX_FIFO_INF_RD_DELAY          0\r
#define LAN9118_TX_FIFO_INF_RD_DELAY          0\r
#define LAN9118_PMT_CTRL_RD_DELAY             0\r
#define LAN9118_GPIO_CFG_RD_DELAY             0\r
#define LAN9118_GPT_CFG_RD_DELAY              0\r
#define LAN9118_GPT_CNT_RD_DELAY              0\r
#define LAN9118_WORD_SWAP_RD_DELAY            0\r
#define LAN9118_FREE_RUN_RD_DELAY             0\r
#define LAN9118_RX_DROP_RD_DELAY              4\r
#define LAN9118_MAC_CSR_CMD_RD_DELAY          0\r
#define LAN9118_MAC_CSR_DATA_RD_DELAY         0\r
#define LAN9118_AFC_CFG_RD_DELAY              0\r
#define LAN9118_E2P_CMD_RD_DELAY              0\r
#define LAN9118_E2P_DATA_RD_DELAY             0\r
\r
// Receiver Status bits\r
#define RXSTATUS_CRC_ERROR                    BIT1                      // Cyclic Redundancy Check Error\r
#define RXSTATUS_DB                           BIT2                      // Dribbling bit: Frame had non-integer multiple of 8bits\r
#define RXSTATUS_MII_ERROR                    BIT3                      // Receive error during interception\r
#define RXSTATUS_RXW_TO                       BIT4                      // Incomming frame larger than 2kb\r
#define RXSTATUS_FT                           BIT5                      // 1: Ether type / 0: 802.3 type frame\r
#define RXSTATUS_LCOLL                        BIT6                      // Late collision detected\r
#define RXSTATUS_FTL                          BIT7                      // Frame longer than Ether type\r
#define RXSTATUS_MCF                          BIT10                     // Frame has Multicast Address\r
#define RXSTATUS_RUNT                         BIT11                     // Bad frame\r
#define RXSTATUS_LE                           BIT12                     // Actual length of frame different than it claims\r
#define RXSTATUS_BCF                          BIT13                     // Frame has Broadcast Address\r
#define RXSTATUS_ES                           BIT15                     // Reports any error from bits 1,6,7 and 11\r
#define RXSTATUS_PL_MASK                      (0x3FFF0000)              // Packet length bit mask\r
#define GET_RXSTATUS_PACKET_LENGTH(RxStatus)  (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask\r
#define RXSTATUS_FILT_FAIL                    BIT30                     // The frame failed filtering test\r
\r
// Transmitter Status bits\r
#define TXSTATUS_DEF                          BIT0                      // Packet tx was deferred\r
#define TXSTATUS_EDEF                         BIT2                      // Tx ended because of excessive deferral (> 24288 bit times)\r
#define TXSTATUS_CC_MASK                      (0x00000078)              // Collision Count (before Tx) bit mask\r
#define TXSTATUS_ECOLL                        BIT8                      // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions)\r
#define TXSTATUS_LCOLL                        BIT9                      // Packet Tx aborted after coll window of 64 bytes\r
#define TXSTATUS_NO_CA                        BIT10                     // Carrier signal not present during Tx (bad?)\r
#define TXSTATUS_LOST_CA                      BIT11                     // Lost carrier during Tx\r
#define TXSTATUS_ES                           BIT15                     // Reports any errors from bits 1,2,8,9,10 and 11\r
#define TXSTATUS_PTAG_MASK                    (0xFFFF0000)              // Mask for Unique ID of packets (So we know who the packets are for)\r
\r
// ID_REV register bits\r
#define IDREV_ID                              ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)\r
#define IDREV_REV                             (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)\r
\r
// Interrupt Config Register bits\r
#define IRQCFG_IRQ_TYPE                       BIT0                    // IRQ Buffer type\r
#define IRQCFG_IRQ_POL                        BIT4                    // IRQ Polarity\r
#define IRQCFG_IRQ_EN                         BIT8                    // Enable external interrupt\r
#define IRQCFG_IRQ_INT                        BIT12                   // State of internal interrupts line\r
#define IRQCFG_INT_DEAS_STS                   BIT13                   // State of deassertion interval\r
#define IRQCFG_INT_DEAS_CLR                   BIT14                   // Clear the deassertion counter\r
#define IRQCFG_INT_DEAS_MASK                  (0xFF000000)            // Interrupt deassertion interval value mask\r
\r
// Interrupt Status Register bits\r
#define INSTS_GPIO_MASK                       (0x7)                   // GPIO interrupts mask\r
#define INSTS_RSFL                            (0x8)                   // Rx Status FIFO Level reached\r
#define INSTS_RSFF                            BIT4                    // Rx Status FIFO full\r
#define INSTS_RXDF_INT                        BIT6                    // Rx Frame dropped\r
#define INSTS_TSFL                            BIT7                    // Tx Status FIFO Level reached\r
#define INSTS_TSFF                            BIT8                    // Tx Status FIFO full\r
#define INSTS_TDFA                            BIT9                    // Tx Data FIFO Level exceeded\r
#define INSTS_TDFO                            BIT10                   // Tx Data FIFO full\r
#define INSTS_TXE                             BIT13                   // Transmitter Error\r
#define INSTS_RXE                             BIT14                   // Receiver Error\r
#define INSTS_RWT                             BIT15                   // Packet > 2048 bytes received\r
#define INSTS_TXSO                            BIT16                   // Tx Status FIFO Overflow\r
#define INSTS_PME_INT                         BIT17                   // PME Signal detected\r
#define INSTS_PHY_INT                         BIT18                   // Indicates PHY Interrupt\r
#define INSTS_GPT_INT                         BIT19                   // GP Timer wrapped past 0xFFFF\r
#define INSTS_RXD_INT                         BIT20                   // Indicates that amount of data written to RX_CFG was cleared\r
#define INSTS_TX_IOC                          BIT21                   // Finished loading IOC flagged buffer to Tx FIFO\r
#define INSTS_RXDFH_INT                       BIT23                   // Rx Dropped frames went past 0x7FFFFFFF\r
#define INSTS_RXSTOP_INT                      BIT24                   // Rx was stopped\r
#define INSTS_TXSTOP_INT                      BIT25                   // Tx was stopped\r
#define INSTS_SW_INT                          BIT31                   // Software Interrupt occurred\r
\r
// Interrupt Enable Register bits\r
\r
\r
// Hardware Config Register bits\r
#define HWCFG_SRST                            BIT0                       // Software Reset bit         (SC)\r
#define HWCFG_SRST_TO                         BIT1                       // Software Reset Timeout bit (RO)\r
#define HWCFG_BMODE                           BIT2                       // 32/16 bit Mode bit         (RO)\r
#define HWCFG_TX_FIFO_SIZE_MASK               (~ (UINT32)0xF0000)        // Mask to Clear FIFO Size\r
#define HWCFG_MBO                             BIT20                      // Must Be One bit\r
\r
// Power Management Control Register\r
#define MPTCTRL_READY                         BIT0                // Device ready indicator\r
#define MPTCTRL_PME_EN                        BIT1                // Enable external PME signals\r
#define MPTCTRL_PME_POL                       BIT2                // Set polarity of PME signals\r
#define MPTCTRL_PME_IND                       BIT3                // Signal type of PME (refer to Spec)\r
#define MPTCTRL_WUPS_MASK                     (0x18)              // Wake up status indicator mask\r
#define MPTCTRL_PME_TYPE                      BIT6                // PME Buffer type (Open Drain or Push-Pull)\r
#define MPTCTRL_ED_EN                         BIT8                // Energy-detect enable\r
#define MPTCTRL_WOL_EN                        BIT9                // Enable wake-on-lan\r
#define MPTCTRL_PHY_RST                       BIT10               // Reset the PHY\r
#define MPTCTRL_PM_MODE_MASK                  (BIT12 | BIT13)     // Set the power mode\r
\r
// PHY control register bits\r
#define PHYCR_COLL_TEST                       BIT7                  // Collision test enable\r
#define PHYCR_DUPLEX_MODE                     BIT8                  // Set Duplex Mode\r
#define PHYCR_RST_AUTO                        BIT9                  // Restart Auto-Negotiation of Link abilities\r
#define PHYCR_PD                              BIT11                 // Power-Down switch\r
#define PHYCR_AUTO_EN                         BIT12                 // Auto-Negotiation Enable\r
#define PHYCR_SPEED_SEL                       BIT13                 // Link Speed Selection\r
#define PHYCR_LOOPBK                          BIT14                 // Set loopback mode\r
#define PHYCR_RESET                           BIT15                 // Do a PHY reset\r
\r
// PHY status register bits\r
#define PHYSTS_EXT_CAP                        BIT0                  // Extended Capabilities Register capability\r
#define PHYSTS_JABBER                         BIT1                  // Jabber condition detected\r
#define PHYSTS_LINK_STS                       BIT2                  // Link Status\r
#define PHYSTS_AUTO_CAP                       BIT3                  // Auto-Negotiation Capability\r
#define PHYSTS_REMOTE_FAULT                   BIT4                  // Remote fault detected\r
#define PHYSTS_AUTO_COMP                      BIT5                  // Auto-Negotiation Completed\r
#define PHYSTS_10BASET_HDPLX                  BIT11                 // 10Mbps Half-Duplex ability\r
#define PHYSTS_10BASET_FDPLX                  BIT12                 // 10Mbps Full-Duplex ability\r
#define PHYSTS_100BASETX_HDPLX                BIT13                 // 100Mbps Half-Duplex ability\r
#define PHYSTS_100BASETX_FDPLX                BIT14                 // 100Mbps Full-Duplex ability\r
#define PHYSTS_100BASE_T4                     BIT15                 // Base T4 ability\r
\r
// PHY Auto-Negotiation advertisement\r
#define PHYANA_SEL_MASK                       ((UINT32)0x1F)        // Link type selector\r
#define PHYANA_10BASET                        BIT5                  // Advertise 10BASET capability\r
#define PHYANA_10BASETFD                      BIT6                  // Advertise 10BASET Full duplex capability\r
#define PHYANA_100BASETX                      BIT7                  // Advertise 100BASETX capability\r
#define PHYANA_100BASETXFD                    BIT8                  // Advertise 100 BASETX Full duplex capability\r
#define PHYANA_PAUSE_OP_MASK                  (3 << 10)             // Advertise PAUSE frame capability\r
#define PHYANA_REMOTE_FAULT                   BIT13                 // Remote fault detected\r
\r
\r
// PHY Auto-Negotiation Link Partner Ability\r
\r
// PHY Auto-Negotiation Expansion\r
\r
// PHY Mode control/status\r
\r
// PHY Special Modes\r
\r
// PHY Special control/status\r
\r
// PHY Interrupt Source Flags\r
\r
// PHY Interrupt Mask\r
\r
// PHY Super Special control/status\r
#define PHYSSCS_HCDSPEED_MASK                 (7 << 2)              // Speed indication\r
#define PHYSSCS_AUTODONE                      BIT12                 // Auto-Negotiation Done\r
\r
\r
// MAC control register bits\r
#define MACCR_RX_EN                       BIT2                     // Enable Receiver bit\r
#define MACCR_TX_EN                       BIT3                     // Enable Transmitter bit\r
#define MACCR_DFCHK                       BIT5                     // Deferral Check bit\r
#define MACCR_PADSTR                      BIT8                     // Automatic Pad Stripping bit\r
#define MACCR_BOLMT_MASK                  (0xC0)                   // Back-Off limit mask\r
#define MACCR_DISRTY                      BIT10                    // Disable Transmit Retry bit\r
#define MACCR_BCAST                       BIT11                    // Disable Broadcast Frames bit\r
#define MACCR_LCOLL                       BIT12                    // Late Collision Control bit\r
#define MACCR_HPFILT                      BIT13                    // Hash/Perfect Filtering Mode bit\r
#define MACCR_HO                          BIT15                    // Hash Only Filtering Mode\r
#define MACCR_PASSBAD                     BIT16                    // Receive all frames that passed filter bit\r
#define MACCR_INVFILT                     BIT17                    // Enable Inverse Filtering bit\r
#define MACCR_PRMS                        BIT18                    // Promiscuous Mode bit\r
#define MACCR_MCPAS                       BIT19                    // Pass all Multicast packets bit\r
#define MACCR_FDPX                        BIT20                    // Full Duplex Mode bit\r
#define MACCR_LOOPBK                      BIT21                    // Loopback operation mode bit\r
#define MACCR_RCVOWN                      BIT23                    // Disable Receive Own frames bit\r
#define MACCR_RX_ALL                      BIT31                    // Receive all Packets and route to Filter\r
\r
// Wake-Up Control and Status Register\r
#define WUCSR_MPEN                        BIT1                     // Magic Packet enable (allow wake from Magic P)\r
#define WUCSR_WUEN                        BIT2                     // Allow remote wake up using Wake-Up Frames\r
#define WUCSR_MPR_MASK                    (0x10)                   // Received Magic Packet\r
#define WUCSR_WUFR_MASK                   (0x20)                   // Received Wake-Up Frame\r
#define WUCSR_GUE                         BIT9                     // Enable wake on global unicast frames\r
\r
// RX Configuration Register bits\r
#define RXCFG_RXDOFF_MASK                 (0x1F00)                 // Rx Data Offset in Bytes\r
#define RXCFG_RX_DUMP                     BIT15                    // Clear Rx data and status FIFOs\r
#define RXCFG_RX_DMA_CNT_MASK             (0x0FFF0000)             // Amount of data to be read from Rx FIFO\r
#define RXCFG_RX_DMA_CNT(cnt)             (((cnt) & 0xFFF) << 16)  // Amount of data to be read from Rx FIFO\r
#define RXCFG_RX_END_ALIGN_MASK           (0xC0000000)             // Alignment to preserve\r
\r
// TX Configuration Register bits\r
#define TXCFG_STOP_TX                     BIT0                     // Stop the transmitter\r
#define TXCFG_TX_ON                       BIT1                     // Start the transmitter\r
#define TXCFG_TXSAO                       BIT2                     // Tx Status FIFO full\r
#define TXCFG_TXD_DUMP                    BIT14                    // Clear Tx Data FIFO\r
#define TXCFG_TXS_DUMP                    BIT15                    // Clear Tx Status FIFO\r
\r
// Rx FIFO Information Register bits\r
#define RXFIFOINF_RXDUSED_MASK            (0xFFFF)                 // Rx Data FIFO Used Space\r
#define RXFIFOINF_RXSUSED_MASK            (0xFF0000)               // Rx Status FIFO Used Space\r
\r
// Tx FIFO Information Register bits\r
#define TXFIFOINF_TDFREE_MASK             (0xFFFF)                 // Tx Data FIFO Free Space\r
#define TXFIFOINF_TXSUSED_MASK            (0xFF0000)               // Tx Status FIFO Used Space\r
\r
// E2P Register\r
#define E2P_EPC_BUSY                BIT31\r
#define E2P_EPC_CMD_READ            (0)\r
#define E2P_EPC_TIMEOUT             BIT9\r
#define E2P_EPC_MAC_ADDRESS_LOADED  BIT8\r
#define E2P_EPC_ADDRESS(address)    ((address) & 0xFFFF)\r
\r
// GPIO Configuration register\r
#define GPIO_GPIO0_PUSH_PULL        BIT16\r
#define GPIO_GPIO1_PUSH_PULL        BIT17\r
#define GPIO_GPIO2_PUSH_PULL        BIT18\r
#define GPIO_LED1_ENABLE            BIT28\r
#define GPIO_LED2_ENABLE            BIT29\r
#define GPIO_LED3_ENABLE            BIT30\r
\r
// MII_ACC bits\r
#define MII_ACC_MII_BUSY        BIT0\r
#define MII_ACC_MII_WRITE       BIT1\r
#define MII_ACC_MII_READ        0\r
\r
#define MII_ACC_PHY_VALUE             BIT11\r
#define MII_ACC_MII_REG_INDEX(index)  (((index) & 0x1F) << 6)\r
\r
//\r
// PHY Control Indexes\r
//\r
#define PHY_INDEX_BASIC_CTRL              0\r
#define PHY_INDEX_BASIC_STATUS            1\r
#define PHY_INDEX_ID1                     2\r
#define PHY_INDEX_ID2                     3\r
#define PHY_INDEX_AUTO_NEG_ADVERT         4\r
#define PHY_INDEX_AUTO_NEG_LINK_ABILITY   5\r
#define PHY_INDEX_AUTO_NEG_EXP            6\r
#define PHY_INDEX_MODE                    17\r
#define PHY_INDEX_SPECIAL_MODES           18\r
#define PHY_INDEX_SPECIAL_CTLR            27\r
#define PHY_INDEX_INT_SRC                 29\r
#define PHY_INDEX_INT_MASK                30\r
#define PHY_INDEX_SPECIAL_PHY_CTLR        31\r
\r
// Indirect MAC Indexes\r
#define INDIRECT_MAC_INDEX_CR         1\r
#define INDIRECT_MAC_INDEX_ADDRH      2\r
#define INDIRECT_MAC_INDEX_ADDRL      3\r
#define INDIRECT_MAC_INDEX_HASHH      4\r
#define INDIRECT_MAC_INDEX_HASHL      5\r
#define INDIRECT_MAC_INDEX_MII_ACC    6\r
#define INDIRECT_MAC_INDEX_MII_DATA   7\r
\r
//\r
// MAC CSR Synchronizer Command register\r
//\r
#define MAC_CSR_BUSY            BIT31\r
#define MAC_CSR_READ            BIT30\r
#define MAC_CSR_WRITE           0\r
#define MAC_CSR_ADDR(Addr)      ((Addr) & 0xFF)\r
\r
//\r
// TX Packet Format\r
//\r
#define TX_CMD_A_COMPLETION_INT             BIT31\r
#define TX_CMD_A_FIRST_SEGMENT              BIT13\r
#define TX_CMD_A_LAST_SEGMENT               BIT12\r
#define TX_CMD_A_BUFF_SIZE(size)            ((size) & 0x000003FF)\r
#define TX_CMD_A_DATA_START_OFFSET(offset)  (((offset) & 0x1F) << 16)\r
#define TX_CMD_B_PACKET_LENGTH(size)        ((size) & 0x000003FF)\r
#define TX_CMD_B_PACKET_TAG(tag)            (((tag) & 0x3FF) << 16)\r
\r
// Hardware Configuration Register\r
#define HW_CFG_TX_FIFO_SIZE_MASK        (0xF << 16)\r
#define HW_CFG_TX_FIFO_SIZE(size)       (((size) & 0xF) << 16)\r
\r
// EEPROM Definition\r
#define EEPROM_EXTERNAL_SERIAL_EEPROM   0xA5\r
\r
//\r
// Conditional compilation flags\r
//\r
//#define EVAL_PERFORMANCE\r
\r
\r
#endif /* __LAN9118_DXE_HDR_H__ */\r
Commit	Line	Data
46f2c53b OM	1	/** @file\r
	2	*\r
	3	* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
	4	*\r
878b807a	5	* SPDX-License-Identifier: BSD-2-Clause-Patent\r
46f2c53b OM	6	*\r
	7	**/\r
	8	\r
	9	#ifndef __LAN9118_DXE_HW_H__\r
	10	#define __LAN9118_DXE_HW_H__\r
	11	\r
	12	/*------------------------------------------------------------------------------\r
	13	LAN9118 SMCS Registers\r
	14	------------------------------------------------------------------------------*/\r
	15	\r
	16	// Base address as on the VE board\r
	17	#define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress))\r
	18	\r
	19	/* ------------- Tx and Rx Data and Status Memory Locations ------------------*/\r
	20	#define LAN9118_RX_DATA (0x00000000 + LAN9118_BA)\r
	21	#define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA)\r
	22	#define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA)\r
	23	#define LAN9118_TX_DATA (0x00000020 + LAN9118_BA)\r
	24	#define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA)\r
	25	#define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA)\r
	26	\r
	27	/* ------------- System Control and Status Registers -------------------------*/\r
	28	#define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision\r
	29	#define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration\r
	30	#define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status\r
	31	#define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable\r
	32	//#define LAN9118_RESERVED (0x00000060)\r
	33	#define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test\r
	34	#define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts\r
	35	#define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration\r
	36	#define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration\r
	37	#define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration\r
	38	#define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration\r
	39	#define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information\r
	40	#define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information\r
	41	#define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control\r
	42	#define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration\r
	43	#define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration\r
	44	#define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count\r
	45	#define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control\r
	46	#define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter\r
	47	#define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter\r
	48	#define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command\r
	49	#define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data\r
	50	#define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration\r
	51	#define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command\r
	52	#define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data\r
	53	\r
73683a24 MR	54	/*\r
	55	* Required delays following write cycles (number of BYTE_TEST reads)\r
	56	* Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
	57	* Where no delay listed, 0 has been assumed.\r
	58	*/\r
	59	#define LAN9118_RX_DATA_WR_DELAY 0\r
	60	#define LAN9118_RX_STATUS_WR_DELAY 0\r
	61	#define LAN9118_RX_STATUS_PEEK_WR_DELAY 0\r
	62	#define LAN9118_TX_DATA_WR_DELAY 0\r
	63	#define LAN9118_TX_STATUS_WR_DELAY 0\r
	64	#define LAN9118_TX_STATUS_PEEK_WR_DELAY 0\r
	65	#define LAN9118_ID_REV_WR_DELAY 0\r
	66	#define LAN9118_IRQ_CFG_WR_DELAY 3\r
	67	#define LAN9118_INT_STS_WR_DELAY 2\r
	68	#define LAN9118_INT_EN_WR_DELAY 1\r
	69	#define LAN9118_BYTE_TEST_WR_DELAY 0\r
	70	#define LAN9118_FIFO_INT_WR_DELAY 1\r
	71	#define LAN9118_RX_CFG_WR_DELAY 1\r
	72	#define LAN9118_TX_CFG_WR_DELAY 1\r
	73	#define LAN9118_HW_CFG_WR_DELAY 1\r
	74	#define LAN9118_RX_DP_CTL_WR_DELAY 1\r
	75	#define LAN9118_RX_FIFO_INF_WR_DELAY 0\r
	76	#define LAN9118_TX_FIFO_INF_WR_DELAY 3\r
	77	#define LAN9118_PMT_CTRL_WR_DELAY 7\r
	78	#define LAN9118_GPIO_CFG_WR_DELAY 1\r
	79	#define LAN9118_GPT_CFG_WR_DELAY 1\r
	80	#define LAN9118_GPT_CNT_WR_DELAY 3\r
	81	#define LAN9118_WORD_SWAP_WR_DELAY 1\r
	82	#define LAN9118_FREE_RUN_WR_DELAY 4\r
	83	#define LAN9118_RX_DROP_WR_DELAY 0\r
	84	#define LAN9118_MAC_CSR_CMD_WR_DELAY 1\r
	85	#define LAN9118_MAC_CSR_DATA_WR_DELAY 1\r
	86	#define LAN9118_AFC_CFG_WR_DELAY 1\r
	87	#define LAN9118_E2P_CMD_WR_DELAY 1\r
	88	#define LAN9118_E2P_DATA_WR_DELAY 1\r
	89	\r
	90	/*\r
	91	* Required delays following read cycles (number of BYTE_TEST reads)\r
	92	* Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
	93	* Where no delay listed, 0 has been assumed.\r
	94	*/\r
	95	#define LAN9118_RX_DATA_RD_DELAY 3\r
	96	#define LAN9118_RX_STATUS_RD_DELAY 3\r
	97	#define LAN9118_RX_STATUS_PEEK_RD_DELAY 0\r
	98	#define LAN9118_TX_DATA_RD_DELAY 0\r
	99	#define LAN9118_TX_STATUS_RD_DELAY 3\r
	100	#define LAN9118_TX_STATUS_PEEK_RD_DELAY 0\r
	101	#define LAN9118_ID_REV_RD_DELAY 0\r
	102	#define LAN9118_IRQ_CFG_RD_DELAY 0\r
	103	#define LAN9118_INT_STS_RD_DELAY 0\r
	104	#define LAN9118_INT_EN_RD_DELAY 0\r
	105	#define LAN9118_BYTE_TEST_RD_DELAY 0\r
	106	#define LAN9118_FIFO_INT_RD_DELAY 0\r
	107	#define LAN9118_RX_CFG_RD_DELAY 0\r
	108	#define LAN9118_TX_CFG_RD_DELAY 0\r
	109	#define LAN9118_HW_CFG_RD_DELAY 0\r
	110	#define LAN9118_RX_DP_CTL_RD_DELAY 0\r
	111	#define LAN9118_RX_FIFO_INF_RD_DELAY 0\r
	112	#define LAN9118_TX_FIFO_INF_RD_DELAY 0\r
	113	#define LAN9118_PMT_CTRL_RD_DELAY 0\r
	114	#define LAN9118_GPIO_CFG_RD_DELAY 0\r
	115	#define LAN9118_GPT_CFG_RD_DELAY 0\r
	116	#define LAN9118_GPT_CNT_RD_DELAY 0\r
	117	#define LAN9118_WORD_SWAP_RD_DELAY 0\r
118	#define LAN9118_FREE_RUN_RD_DELAY 0\r
119	#define LAN9118_RX_DROP_RD_DELAY 4\r
120	#define LAN9118_MAC_CSR_CMD_RD_DELAY 0\r
121	#define LAN9118_MAC_CSR_DATA_RD_DELAY 0\r
122	#define LAN9118_AFC_CFG_RD_DELAY 0\r
123	#define LAN9118_E2P_CMD_RD_DELAY 0\r
124	#define LAN9118_E2P_DATA_RD_DELAY 0\r
46f2c53b OM	125	\r
	126	// Receiver Status bits\r
	127	#define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error\r
	128	#define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits\r
	129	#define RXSTATUS_MII_ERROR BIT3 // Receive error during interception\r
	130	#define RXSTATUS_RXW_TO BIT4 // Incomming frame larger than 2kb\r
	131	#define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame\r
	132	#define RXSTATUS_LCOLL BIT6 // Late collision detected\r
	133	#define RXSTATUS_FTL BIT7 // Frame longer than Ether type\r
	134	#define RXSTATUS_MCF BIT10 // Frame has Multicast Address\r
	135	#define RXSTATUS_RUNT BIT11 // Bad frame\r
	136	#define RXSTATUS_LE BIT12 // Actual length of frame different than it claims\r
	137	#define RXSTATUS_BCF BIT13 // Frame has Broadcast Address\r
	138	#define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11\r
	139	#define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask\r
	140	#define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask\r
	141	#define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test\r
	142	\r
	143	// Transmitter Status bits\r
	144	#define TXSTATUS_DEF BIT0 // Packet tx was deferred\r
	145	#define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times)\r
	146	#define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask\r
	147	#define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions)\r
	148	#define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes\r
	149	#define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?)\r
	150	#define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx\r
	151	#define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11\r
	152	#define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for)\r
	153	\r
	154	// ID_REV register bits\r
e68449c9 MR	155	#define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)\r
e68449c9 MR	156	#define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)\r
46f2c53b OM	157	\r
	158	// Interrupt Config Register bits\r
	159	#define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type\r
	160	#define IRQCFG_IRQ_POL BIT4 // IRQ Polarity\r
	161	#define IRQCFG_IRQ_EN BIT8 // Enable external interrupt\r
	162	#define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line\r
	163	#define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval\r
	164	#define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter\r
	165	#define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask\r
	166	\r
	167	// Interrupt Status Register bits\r
	168	#define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask\r
	169	#define INSTS_RSFL (0x8) // Rx Status FIFO Level reached\r
	170	#define INSTS_RSFF BIT4 // Rx Status FIFO full\r
	171	#define INSTS_RXDF_INT BIT6 // Rx Frame dropped\r
	172	#define INSTS_TSFL BIT7 // Tx Status FIFO Level reached\r
	173	#define INSTS_TSFF BIT8 // Tx Status FIFO full\r
	174	#define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded\r
	175	#define INSTS_TDFO BIT10 // Tx Data FIFO full\r
	176	#define INSTS_TXE BIT13 // Transmitter Error\r
	177	#define INSTS_RXE BIT14 // Receiver Error\r
	178	#define INSTS_RWT BIT15 // Packet > 2048 bytes received\r
	179	#define INSTS_TXSO BIT16 // Tx Status FIFO Overflow\r
	180	#define INSTS_PME_INT BIT17 // PME Signal detected\r
	181	#define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt\r
	182	#define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF\r
	183	#define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared\r
	184	#define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO\r
	185	#define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF\r
	186	#define INSTS_RXSTOP_INT BIT24 // Rx was stopped\r
	187	#define INSTS_TXSTOP_INT BIT25 // Tx was stopped\r
	188	#define INSTS_SW_INT BIT31 // Software Interrupt occurred\r
	189	\r
	190	// Interrupt Enable Register bits\r
	191	\r
	192	\r
	193	// Hardware Config Register bits\r
	194	#define HWCFG_SRST BIT0 // Software Reset bit (SC)\r
	195	#define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO)\r
	196	#define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO)\r
	197	#define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size\r
	198	#define HWCFG_MBO BIT20 // Must Be One bit\r
	199	\r
	200	// Power Management Control Register\r
	201	#define MPTCTRL_READY BIT0 // Device ready indicator\r
	202	#define MPTCTRL_PME_EN BIT1 // Enable external PME signals\r
	203	#define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals\r
	204	#define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec)\r
	205	#define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask\r
	206	#define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull)\r
	207	#define MPTCTRL_ED_EN BIT8 // Energy-detect enable\r
	208	#define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan\r
	209	#define MPTCTRL_PHY_RST BIT10 // Reset the PHY\r
	210	#define MPTCTRL_PM_MODE_MASK (BIT12 \| BIT13) // Set the power mode\r
	211	\r
	212	// PHY control register bits\r
	213	#define PHYCR_COLL_TEST BIT7 // Collision test enable\r
	214	#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode\r
	215	#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities\r
	216	#define PHYCR_PD BIT11 // Power-Down switch\r
	217	#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable\r
	218	#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection\r
	219	#define PHYCR_LOOPBK BIT14 // Set loopback mode\r
	220	#define PHYCR_RESET BIT15 // Do a PHY reset\r
221	\r
222	// PHY status register bits\r
223	#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability\r
224	#define PHYSTS_JABBER BIT1 // Jabber condition detected\r
225	#define PHYSTS_LINK_STS BIT2 // Link Status\r
226	#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability\r
227	#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected\r
228	#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed\r
229	#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability\r
230	#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability\r
231	#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability\r
232	#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability\r
233	#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability\r
234	\r
235	// PHY Auto-Negotiation advertisement\r
236	#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector\r
237	#define PHYANA_10BASET BIT5 // Advertise 10BASET capability\r
238	#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability\r
239	#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability\r
240	#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability\r
241	#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability\r
242	#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected\r
243	\r
244	\r
245	// PHY Auto-Negotiation Link Partner Ability\r
246	\r
247	// PHY Auto-Negotiation Expansion\r
248	\r
249	// PHY Mode control/status\r
250	\r
251	// PHY Special Modes\r
252	\r
253	// PHY Special control/status\r
254	\r
255	// PHY Interrupt Source Flags\r
256	\r
257	// PHY Interrupt Mask\r
258	\r
259	// PHY Super Special control/status\r
260	#define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication\r
261	#define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done\r
262	\r
263	\r
264	// MAC control register bits\r
265	#define MACCR_RX_EN BIT2 // Enable Receiver bit\r
266	#define MACCR_TX_EN BIT3 // Enable Transmitter bit\r
267	#define MACCR_DFCHK BIT5 // Deferral Check bit\r
268	#define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit\r
269	#define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask\r
270	#define MACCR_DISRTY BIT10 // Disable Transmit Retry bit\r
271	#define MACCR_BCAST BIT11 // Disable Broadcast Frames bit\r
272	#define MACCR_LCOLL BIT12 // Late Collision Control bit\r
273	#define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit\r
274	#define MACCR_HO BIT15 // Hash Only Filtering Mode\r
275	#define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit\r
276	#define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit\r
277	#define MACCR_PRMS BIT18 // Promiscuous Mode bit\r
278	#define MACCR_MCPAS BIT19 // Pass all Multicast packets bit\r
279	#define MACCR_FDPX BIT20 // Full Duplex Mode bit\r
280	#define MACCR_LOOPBK BIT21 // Loopback operation mode bit\r
281	#define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit\r
282	#define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter\r
283	\r
284	// Wake-Up Control and Status Register\r
285	#define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P)\r
286	#define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames\r
287	#define WUCSR_MPR_MASK (0x10) // Received Magic Packet\r
288	#define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame\r
289	#define WUCSR_GUE BIT9 // Enable wake on global unicast frames\r
290	\r
291	// RX Configuration Register bits\r
292	#define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes\r
293	#define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs\r
294	#define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO\r
295	#define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO\r
296	#define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve\r
297	\r
298	// TX Configuration Register bits\r
299	#define TXCFG_STOP_TX BIT0 // Stop the transmitter\r
300	#define TXCFG_TX_ON BIT1 // Start the transmitter\r
301	#define TXCFG_TXSAO BIT2 // Tx Status FIFO full\r
302	#define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO\r
303	#define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO\r
304	\r
305	// Rx FIFO Information Register bits\r
306	#define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space\r
307	#define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space\r
308	\r
309	// Tx FIFO Information Register bits\r
310	#define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space\r
311	#define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space\r
312	\r
313	// E2P Register\r
314	#define E2P_EPC_BUSY BIT31\r
315	#define E2P_EPC_CMD_READ (0)\r
316	#define E2P_EPC_TIMEOUT BIT9\r
317	#define E2P_EPC_MAC_ADDRESS_LOADED BIT8\r
318	#define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF)\r
319	\r
320	// GPIO Configuration register\r
321	#define GPIO_GPIO0_PUSH_PULL BIT16\r
322	#define GPIO_GPIO1_PUSH_PULL BIT17\r
323	#define GPIO_GPIO2_PUSH_PULL BIT18\r
324	#define GPIO_LED1_ENABLE BIT28\r
325	#define GPIO_LED2_ENABLE BIT29\r
326	#define GPIO_LED3_ENABLE BIT30\r
327	\r
328	// MII_ACC bits\r
329	#define MII_ACC_MII_BUSY BIT0\r
330	#define MII_ACC_MII_WRITE BIT1\r
331	#define MII_ACC_MII_READ 0\r
332	\r
333	#define MII_ACC_PHY_VALUE BIT11\r
334	#define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6)\r
335	\r
336	//\r
337	// PHY Control Indexes\r
338	//\r
339	#define PHY_INDEX_BASIC_CTRL 0\r
340	#define PHY_INDEX_BASIC_STATUS 1\r
341	#define PHY_INDEX_ID1 2\r
342	#define PHY_INDEX_ID2 3\r
343	#define PHY_INDEX_AUTO_NEG_ADVERT 4\r
344	#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5\r
345	#define PHY_INDEX_AUTO_NEG_EXP 6\r
346	#define PHY_INDEX_MODE 17\r
347	#define PHY_INDEX_SPECIAL_MODES 18\r
348	#define PHY_INDEX_SPECIAL_CTLR 27\r
349	#define PHY_INDEX_INT_SRC 29\r
350	#define PHY_INDEX_INT_MASK 30\r
351	#define PHY_INDEX_SPECIAL_PHY_CTLR 31\r
352	\r
353	// Indirect MAC Indexes\r
354	#define INDIRECT_MAC_INDEX_CR 1\r
355	#define INDIRECT_MAC_INDEX_ADDRH 2\r
356	#define INDIRECT_MAC_INDEX_ADDRL 3\r
357	#define INDIRECT_MAC_INDEX_HASHH 4\r
358	#define INDIRECT_MAC_INDEX_HASHL 5\r
359	#define INDIRECT_MAC_INDEX_MII_ACC 6\r
360	#define INDIRECT_MAC_INDEX_MII_DATA 7\r
361	\r
362	//\r
363	// MAC CSR Synchronizer Command register\r
364	//\r
365	#define MAC_CSR_BUSY BIT31\r
366	#define MAC_CSR_READ BIT30\r
367	#define MAC_CSR_WRITE 0\r
368	#define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF)\r
369	\r
370	//\r
371	// TX Packet Format\r
372	//\r
373	#define TX_CMD_A_COMPLETION_INT BIT31\r
374	#define TX_CMD_A_FIRST_SEGMENT BIT13\r
375	#define TX_CMD_A_LAST_SEGMENT BIT12\r
376	#define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF)\r
377	#define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16)\r
378	#define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF)\r
379	#define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16)\r
380	\r
381	// Hardware Configuration Register\r
382	#define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16)\r
383	#define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16)\r
384	\r
385	// EEPROM Definition\r
386	#define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5\r
387	\r
388	//\r
389	// Conditional compilation flags\r
390	//\r
391	//#define EVAL_PERFORMANCE\r
392	\r
393	\r
394	#endif /* __LAN9118_DXE_HDR_H__ */\r