]> git.proxmox.com Git - mirror_edk2.git/blame - EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h
EmbeddedPkg: import Lan91x Ethernet controller driver
[mirror_edk2.git] / EmbeddedPkg / Drivers / Lan9118Dxe / Lan9118DxeUtil.h
CommitLineData
46f2c53b
OM
1/** @file\r
2*\r
3* Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r
4*\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12*\r
13**/\r
14\r
15#ifndef __LAN9118_DXE_UTIL_H__\r
16#define __LAN9118_DXE_UTIL_H__\r
17\r
18// Most common CRC32 Polynomial for little endian machines\r
19#define CRC_POLYNOMIAL 0xEDB88320\r
20\r
21/**\r
22 This internal function reverses bits for 32bit data.\r
23\r
24 @param Value The data to be reversed.\r
25\r
26 @return Data reversed.\r
27\r
28**/\r
29UINT32\r
30ReverseBits (\r
31 UINT32 Value\r
32 );\r
33\r
34// Create an Ethernet CRC\r
35UINT32\r
36GenEtherCrc32 (\r
37 IN EFI_MAC_ADDRESS *Mac,\r
38 IN UINT32 AddrLen\r
39 );\r
40\r
73683a24
MR
41UINT32\r
42Lan9118RawMmioRead32(\r
43 UINTN Address,\r
44 UINTN Delay\r
45 );\r
46#define Lan9118MmioRead32(a) \\r
47 Lan9118RawMmioRead32(a, a ## _RD_DELAY)\r
48\r
49UINT32\r
50Lan9118RawMmioWrite32(\r
51 UINTN Address,\r
52 UINT32 Value,\r
53 UINTN Delay\r
54 );\r
55#define Lan9118MmioWrite32(a, v) \\r
56 Lan9118RawMmioWrite32(a, v, a ## _WR_DELAY)\r
57\r
46f2c53b
OM
58/* ------------------ MAC CSR Access ------------------- */\r
59\r
60// Read from MAC indirect registers\r
61UINT32\r
62IndirectMACRead32 (\r
63 UINT32 Index\r
64 );\r
65\r
66\r
67// Write to indirect registers\r
68UINT32\r
69IndirectMACWrite32 (\r
70 UINT32 Index,\r
71 UINT32 Value\r
72 );\r
73\r
74\r
75/* --------------- PHY Registers Access ---------------- */\r
76\r
77// Read from MII register (PHY Access)\r
78UINT32\r
79IndirectPHYRead32(\r
80 UINT32 Index\r
81 );\r
82\r
83\r
84// Write to the MII register (PHY Access)\r
85UINT32\r
86IndirectPHYWrite32(\r
87 UINT32 Index,\r
88 UINT32 Value\r
89 );\r
90\r
91/* ---------------- EEPROM Operations ------------------ */\r
92\r
93// Read from EEPROM memory\r
94UINT32\r
95IndirectEEPROMRead32 (\r
96 UINT32 Index\r
97 );\r
98\r
99// Write to EEPROM memory\r
100UINT32\r
101IndirectEEPROMWrite32 (\r
102 UINT32 Index,\r
103 UINT32 Value\r
104 );\r
105\r
106/* ---------------- General Operations ----------------- */\r
107\r
108VOID\r
109Lan9118SetMacAddress (\r
110 EFI_MAC_ADDRESS *Mac,\r
111 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
112 );\r
113\r
114// Initialise the LAN9118\r
115EFI_STATUS\r
116Lan9118Initialize (\r
117 IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
118 );\r
119\r
120// Flags for software reset\r
121#define SOFT_RESET_CHECK_MAC_ADDR_LOAD BIT0\r
122#define SOFT_RESET_CLEAR_INT BIT1\r
123#define SOFT_RESET_SELF_TEST BIT2\r
124\r
125// Perform software reset on the LAN9118\r
126EFI_STATUS\r
127SoftReset (\r
128 UINT32 Flags,\r
129 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
130 );\r
131\r
132// Flags for PHY reset\r
133#define PHY_RESET_PMT BIT0\r
134#define PHY_RESET_BCR BIT1\r
6382e5df 135#define PHY_SOFT_RESET_CLEAR_INT BIT2\r
46f2c53b
OM
136\r
137// Perform PHY software reset\r
42589b9a 138EFI_STATUS\r
46f2c53b
OM
139PhySoftReset (\r
140 UINT32 Flags,\r
141 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
142 );\r
143\r
144// Flags for Hardware configuration\r
145#define HW_CONF_USE_LEDS BIT0\r
146\r
147// Configure hardware for LAN9118\r
148EFI_STATUS\r
149ConfigureHardware (\r
150 UINT32 Flags,\r
151 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
152 );\r
153\r
154// Configure flow control\r
155EFI_STATUS\r
156ConfigureFlow (\r
157 UINT32 Flags,\r
158 UINT32 HighTrig,\r
159 UINT32 LowTrig,\r
160 UINT32 BPDuration,\r
161 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
162 );\r
163\r
164// Flags for auto negotiation\r
165#define AUTO_NEGOTIATE_COLLISION_TEST BIT0\r
166#define AUTO_NEGOTIATE_ADVERTISE_ALL BIT1\r
167\r
168// Do auto-negotiation\r
169EFI_STATUS\r
170AutoNegotiate (\r
171 UINT32 Flags,\r
172 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
173 );\r
174\r
175// Check the Link Status and take appropriate action\r
176EFI_STATUS\r
177CheckLinkStatus (\r
178 UINT32 Flags,\r
179 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
180 );\r
181\r
182// Stop transmitter flags\r
183#define STOP_TX_MAC BIT0\r
184#define STOP_TX_CFG BIT1\r
185#define STOP_TX_CLEAR BIT2\r
186\r
187// Stop the transmitter\r
188EFI_STATUS\r
189StopTx (\r
190 UINT32 Flags,\r
191 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
192 );\r
193\r
194// Stop receiver flags\r
195#define STOP_RX_CLEAR BIT0\r
196\r
197// Stop the receiver\r
198EFI_STATUS\r
199StopRx (\r
200 UINT32 Flags,\r
201 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
202 );\r
203\r
204// Start transmitter flags\r
205#define START_TX_MAC BIT0\r
206#define START_TX_CFG BIT1\r
207#define START_TX_CLEAR BIT2\r
208\r
209// Start the transmitter\r
210EFI_STATUS\r
211StartTx (\r
212 UINT32 Flags,\r
213 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
214 );\r
215\r
216// Stop receiver flags\r
217#define START_RX_CLEAR BIT0\r
218\r
219// Start the receiver\r
220EFI_STATUS\r
221StartRx (\r
222 UINT32 Flags,\r
223 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
224 );\r
225\r
226// Check Tx Data available space\r
227UINT32\r
228TxDataFreeSpace (\r
229 UINT32 Flags,\r
230 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
231 );\r
232\r
233// Check Tx Status used space\r
234UINT32\r
235TxStatusUsedSpace (\r
236 UINT32 Flags,\r
237 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
238 );\r
239\r
240// Check Rx Data used space\r
241UINT32\r
242RxDataUsedSpace (\r
243 UINT32 Flags,\r
244 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
245 );\r
246\r
247// Check Rx Status used space\r
248UINT32\r
249RxStatusUsedSpace (\r
250 UINT32 Flags,\r
251 EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
252 );\r
253\r
254\r
255// Flags for FIFO allocation\r
256#define ALLOC_USE_DEFAULT BIT0\r
257#define ALLOC_USE_FIFOS BIT1\r
258#define ALLOC_USE_DMA BIT2\r
259\r
260// FIFO min and max sizes\r
261#define TX_FIFO_MIN_SIZE 0x00000600\r
262#define TX_FIFO_MAX_SIZE 0x00003600\r
263//#define RX_FIFO_MIN_SIZE\r
264//#define RX_FIFO_MAX_SIZE\r
265\r
266// Change the allocation of FIFOs\r
267EFI_STATUS\r
268ChangeFifoAllocation (\r
269 IN UINT32 Flags,\r
270 IN OUT UINTN *TxDataSize OPTIONAL,\r
271 IN OUT UINTN *RxDataSize OPTIONAL,\r
272 IN OUT UINT32 *TxStatusSize OPTIONAL,\r
273 IN OUT UINT32 *RxStatusSize OPTIONAL,\r
274 IN OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r
275 );\r
276\r
277VOID\r
278Lan9118ReadMacAddress (\r
279 OUT EFI_MAC_ADDRESS *Mac\r
280 );\r
281\r
282#endif // __LAN9118_DXE_UTIL_H__\r