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[mirror_edk2.git] / EmbeddedPkg / Drivers / Lan91xDxe / Lan91xDxeHw.h
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1/** @file\r
2* SMSC LAN91x series Network Controller Driver.\r
3*\r
4* Copyright (c) 2013-2017 Linaro.org\r
5*\r
6* This program and the accompanying materials are licensed and\r
7* made available under the terms and conditions of the BSD License\r
8* which accompanies this distribution. The full text of the license\r
9* may be found at: http://opensource.org/licenses/bsd-license.php\r
10*\r
11* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13*\r
14**/\r
15\r
16#ifndef __LAN91XDXEHW_H__\r
17#define __LAN91XDXEHW_H__\r
18\r
19#include <Base.h>\r
20\r
21#define MakeRegister(Bank, Offset) (((Bank) << 8) | (Offset))\r
22#define RegisterToBank(Register) (((Register) >> 8) & 0x07)\r
23#define RegisterToOffset(Register) ((Register) & 0x0f)\r
24\r
25/*---------------------------------------------------------------------------------------------------------------------\r
26\r
27 SMSC LAN91x Registers\r
28\r
29---------------------------------------------------------------------------------------------------------------------*/\r
30#define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks)\r
31\r
32#define LAN91X_TCR MakeRegister (0, 0x0) // Transmit Control Register\r
33#define LAN91X_EPHSR MakeRegister (0, 0x2) // EPH Status Register\r
34#define LAN91X_RCR MakeRegister (0, 0x4) // Receive Control Register\r
35#define LAN91X_ECR MakeRegister (0, 0x6) // Counter Register\r
36#define LAN91X_MIR MakeRegister (0, 0x8) // Memory Information Register\r
37#define LAN91X_RPCR MakeRegister (0, 0xa) // Receive/Phy Control Register\r
38\r
39#define LAN91X_CR MakeRegister (1, 0x0) // Configuration Register\r
40#define LAN91X_BAR MakeRegister (1, 0x2) // Base Address Register\r
41#define LAN91X_IAR0 MakeRegister (1, 0x4) // Individual Address Register 0\r
42#define LAN91X_IAR1 MakeRegister (1, 0x5) // Individual Address Register 1\r
43#define LAN91X_IAR2 MakeRegister (1, 0x6) // Individual Address Register 2\r
44#define LAN91X_IAR3 MakeRegister (1, 0x7) // Individual Address Register 3\r
45#define LAN91X_IAR4 MakeRegister (1, 0x8) // Individual Address Register 4\r
46#define LAN91X_IAR5 MakeRegister (1, 0x9) // Individual Address Register 5\r
47#define LAN91X_GPR MakeRegister (1, 0xa) // General Purpose Register\r
48#define LAN91X_CTR MakeRegister (1, 0xc) // Control Register\r
49\r
50#define LAN91X_MMUCR MakeRegister (2, 0x0) // MMU Command Register\r
51#define LAN91X_PNR MakeRegister (2, 0x2) // Packet Number Register\r
52#define LAN91X_ARR MakeRegister (2, 0x3) // Allocation Result Register\r
53#define LAN91X_FIFO MakeRegister (2, 0x4) // FIFO Ports Register\r
54#define LAN91X_PTR MakeRegister (2, 0x6) // Pointer Register\r
55#define LAN91X_DATA0 MakeRegister (2, 0x8) // Data Register 0\r
56#define LAN91X_DATA1 MakeRegister (2, 0x9) // Data Register 1\r
57#define LAN91X_DATA2 MakeRegister (2, 0xa) // Data Register 2\r
58#define LAN91X_DATA3 MakeRegister (2, 0xb) // Data Register 3\r
59#define LAN91X_IST MakeRegister (2, 0xc) // Interrupt Status Register\r
60#define LAN91X_MSK MakeRegister (2, 0xd) // Interrupt Mask Register\r
61\r
62#define LAN91X_MT0 MakeRegister (3, 0x0) // Multicast Table Register 0\r
63#define LAN91X_MT1 MakeRegister (3, 0x1) // Multicast Table Register 1\r
64#define LAN91X_MT2 MakeRegister (3, 0x2) // Multicast Table Register 2\r
65#define LAN91X_MT3 MakeRegister (3, 0x3) // Multicast Table Register 3\r
66#define LAN91X_MT4 MakeRegister (3, 0x4) // Multicast Table Register 4\r
67#define LAN91X_MT5 MakeRegister (3, 0x5) // Multicast Table Register 5\r
68#define LAN91X_MT6 MakeRegister (3, 0x6) // Multicast Table Register 6\r
69#define LAN91X_MT7 MakeRegister (3, 0x7) // Multicast Table Register 7\r
70#define LAN91X_MGMT MakeRegister (3, 0x8) // Management Interface Register\r
71#define LAN91X_REV MakeRegister (3, 0xa) // Revision Register\r
72#define LAN91X_RCV MakeRegister (3, 0xc) // RCV Register\r
73\r
74// Transmit Control Register Bits\r
75#define TCR_TXENA BIT0\r
76#define TCR_LOOP BIT1\r
77#define TCR_FORCOL BIT2\r
78#define TCR_PAD_EN BIT7\r
79#define TCR_NOCRC BIT8\r
80#define TCR_MON_CSN BIT10\r
81#define TCR_FDUPLX BIT11\r
82#define TCR_STP_SQET BIT12\r
83#define TCR_EPH_LOOP BIT13\r
84#define TCR_SWFDUP BIT15\r
85\r
86#define TCR_DEFAULT (TCR_TXENA | TCR_PAD_EN)\r
87#define TCR_CLEAR 0x0\r
88\r
89// EPH Status Register Bits\r
90#define EPHSR_TX_SUC BIT0\r
91#define EPHSR_SNGLCOL BIT1\r
92#define EPHSR_MULCOL BIT2\r
93#define EPHSR_LTX_MULT BIT3\r
94#define EPHSR_16COL BIT4\r
95#define EPHSR_SQET BIT5\r
96#define EPHSR_LTX_BRD BIT6\r
97#define EPHSR_TX_DEFR BIT7\r
98#define EPHSR_LATCOL BIT9\r
99#define EPHSR_LOST_CARR BIT10\r
100#define EPHSR_EXC_DEF BIT11\r
101#define EPHSR_CTR_ROL BIT12\r
102#define EPHSR_LINK_OK BIT14\r
103\r
104// Receive Control Register Bits\r
105#define RCR_RX_ABORT BIT0\r
106#define RCR_PRMS BIT1\r
107#define RCR_ALMUL BIT2\r
108#define RCR_RXEN BIT8\r
109#define RCR_STRIP_CRC BIT9\r
110#define RCR_ABORT_ENB BIT13\r
111#define RCR_FILT_CAR BIT14\r
112#define RCR_SOFT_RST BIT15\r
113\r
114#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)\r
115#define RCR_CLEAR 0x0\r
116\r
117// Receive/Phy Control Register Bits\r
118#define RPCR_LS0B BIT2\r
119#define RPCR_LS1B BIT3\r
120#define RPCR_LS2B BIT4\r
121#define RPCR_LS0A BIT5\r
122#define RPCR_LS1A BIT6\r
123#define RPCR_LS2A BIT7\r
124#define RPCR_ANEG BIT11\r
125#define RPCR_DPLX BIT12\r
126#define RPCR_SPEED BIT13\r
127\r
128// Configuration Register Bits\r
129#define CR_EXT_PHY BIT9\r
130#define CR_GPCNTRL BIT10\r
131#define CR_NO_WAIT BIT12\r
132#define CR_EPH_POWER_EN BIT15\r
133\r
134#define CR_DEFAULT (CR_EPH_POWER_EN | CR_NO_WAIT)\r
135\r
136// Control Register Bits\r
137#define CTR_STORE BIT0\r
138#define CTR_RELOAD BIT1\r
139#define CTR_EEPROM_SEL BIT2\r
140#define CTR_TE_ENABLE BIT5\r
141#define CTR_CR_ENABLE BIT6\r
142#define CTR_LE_ENABLE BIT7\r
143#define CTR_AUTO_REL BIT11\r
144#define CTR_RCV_BAD BIT14\r
145\r
146#define CTR_RESERVED (BIT12 | BIT9 | BIT4)\r
147#define CTR_DEFAULT (CTR_RESERVED | CTR_AUTO_REL)\r
148\r
149// MMU Command Register Bits\r
150#define MMUCR_BUSY BIT0\r
151\r
152// MMU Command Register Operaction Codes\r
153#define MMUCR_OP_NOOP (0 << 5) // No operation\r
154#define MMUCR_OP_TX_ALLOC (1 << 5) // Allocate memory for TX\r
155#define MMUCR_OP_RESET_MMU (2 << 5) // Reset MMU to initial state\r
156#define MMUCR_OP_RX_POP (3 << 5) // Remove frame from top of RX FIFO\r
157#define MMUCR_OP_RX_POP_REL (4 << 5) // Remove and release frame from top of RX FIFO\r
158#define MMUCR_OP_RX_REL (5 << 5) // Release specific RX frame\r
159#define MMUCR_OP_TX_PUSH (6 << 5) // Enqueue packet number into TX FIFO\r
160#define MMUCR_OP_TX_RESET (7 << 5) // Reset TX FIFOs\r
161\r
162// Packet Number Register Bits\r
163#define PNR_PACKET (0x3f)\r
164\r
165// Allocation Result Register Bits\r
166#define ARR_PACKET (0x3f)\r
167#define ARR_FAILED BIT7\r
168\r
169// FIFO Ports Register Bits\r
170#define FIFO_TX_PACKET (0x003f)\r
171#define FIFO_TEMPTY BIT7\r
172#define FIFO_RX_PACKET (0x3f00)\r
173#define FIFO_REMPTY BIT15\r
174\r
175// Pointer Register Bits\r
176#define PTR_POINTER (0x07ff)\r
177#define PTR_NOT_EMPTY BIT11\r
178#define PTR_READ BIT13\r
179#define PTR_AUTO_INCR BIT14\r
180#define PTR_RCV BIT15\r
181\r
182// Interupt Status and Mask Register Bits\r
183#define IST_RCV BIT0\r
184#define IST_TX BIT1\r
185#define IST_TX_EMPTY BIT2\r
186#define IST_ALLOC BIT3\r
187#define IST_RX_OVRN BIT4\r
188#define IST_EPH BIT5\r
189#define IST_MD BIT7\r
190\r
191// Management Interface\r
192#define MGMT_MDO BIT0\r
193#define MGMT_MDI BIT1\r
194#define MGMT_MCLK BIT2\r
195#define MGMT_MDOE BIT3\r
196#define MGMT_MSK_CRS100 BIT14\r
197\r
198// RCV Register\r
199#define RCV_MBO (0x1f)\r
200#define RCV_RCV_DISCRD BIT7\r
201\r
202// Packet RX Status word bits\r
203#define RX_MULTICAST BIT0\r
204#define RX_HASH (0x7e)\r
205#define RX_TOO_SHORT BIT10\r
206#define RX_TOO_LONG BIT11\r
207#define RX_ODD_FRAME BIT12\r
208#define RX_BAD_CRC BIT13\r
209#define RX_BROADCAST BIT14\r
210#define RX_ALGN_ERR BIT15\r
211\r
212// Packet Byte Count word bits\r
213#define BCW_COUNT (0x7fe)\r
214\r
215// Packet Control Word bits\r
216#define PCW_ODD_BYTE (0x00ff)\r
217#define PCW_CRC BIT12\r
218#define PCW_ODD BIT13\r
219\r
220/*---------------------------------------------------------------------------------------------------------------------\r
221\r
222 SMSC PHY Registers\r
223\r
224 Most of these should be common, as there is\r
225 documented STANDARD for PHY registers!\r
226\r
227---------------------------------------------------------------------------------------------------------------------*/\r
228//\r
229// PHY Register Numbers\r
230//\r
231#define PHY_INDEX_BASIC_CTRL 0\r
232#define PHY_INDEX_BASIC_STATUS 1\r
233#define PHY_INDEX_ID1 2\r
234#define PHY_INDEX_ID2 3\r
235#define PHY_INDEX_AUTO_NEG_ADVERT 4\r
236#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5\r
237\r
238#define PHY_INDEX_CONFIG1 16\r
239#define PHY_INDEX_CONFIG2 17\r
240#define PHY_INDEX_STATUS_OUTPUT 18\r
241#define PHY_INDEX_MASK 19\r
242\r
243\r
244// PHY control register bits\r
245#define PHYCR_COLL_TEST BIT7 // Collision test enable\r
246#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode\r
247#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities\r
248#define PHYCR_PD BIT11 // Power-Down switch\r
249#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable\r
250#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection\r
251#define PHYCR_LOOPBK BIT14 // Set loopback mode\r
252#define PHYCR_RESET BIT15 // Do a PHY reset\r
253\r
254// PHY status register bits\r
255#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability\r
256#define PHYSTS_JABBER BIT1 // Jabber condition detected\r
257#define PHYSTS_LINK_STS BIT2 // Link Status\r
258#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability\r
259#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected\r
260#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed\r
261#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability\r
262#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability\r
263#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability\r
264#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability\r
265#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability\r
266\r
267// PHY Auto-Negotiation advertisement\r
268#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector\r
269#define PHYANA_CSMA BIT0 // Advertise CSMA capability\r
270#define PHYANA_10BASET BIT5 // Advertise 10BASET capability\r
271#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability\r
272#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability\r
273#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability\r
274#define PHYANA_100BASET4 BIT9 // Advertise 100 BASETX Full duplex capability\r
275#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability\r
276#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected\r
277\r
278#endif /* __LAN91XDXEHW_H__ */\r