[mirror_edk2.git] / EmbeddedPkg / Drivers / Lan91xDxe / Lan91xDxeHw.h

/** @file\r
*  SMSC LAN91x series Network Controller Driver.\r
*\r
*  Copyright (c) 2013-2017 Linaro.org\r
*\r
*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#ifndef __LAN91XDXEHW_H__\r
#define __LAN91XDXEHW_H__\r
\r
#include <Base.h>\r
\r
#define MakeRegister(Bank, Offset)  (((Bank) << 8) | (Offset))\r
#define RegisterToBank(Register)    (((Register) >> 8) & 0x07)\r
#define RegisterToOffset(Register)  ((Register) & 0x0f)\r
\r
/*---------------------------------------------------------------------------------------------------------------------\r
\r
        SMSC LAN91x Registers\r
\r
---------------------------------------------------------------------------------------------------------------------*/\r
#define LAN91X_BANK_OFFSET      0xe                     // Bank Select Register (all banks)\r
\r
#define LAN91X_TCR      MakeRegister (0, 0x0)           // Transmit Control Register\r
#define LAN91X_EPHSR    MakeRegister (0, 0x2)           // EPH Status Register\r
#define LAN91X_RCR      MakeRegister (0, 0x4)           // Receive Control Register\r
#define LAN91X_ECR      MakeRegister (0, 0x6)           // Counter Register\r
#define LAN91X_MIR      MakeRegister (0, 0x8)           // Memory Information Register\r
#define LAN91X_RPCR     MakeRegister (0, 0xa)           // Receive/Phy Control Register\r
\r
#define LAN91X_CR       MakeRegister (1, 0x0)           // Configuration Register\r
#define LAN91X_BAR      MakeRegister (1, 0x2)           // Base Address Register\r
#define LAN91X_IAR0     MakeRegister (1, 0x4)           // Individual Address Register 0\r
#define LAN91X_IAR1     MakeRegister (1, 0x5)           // Individual Address Register 1\r
#define LAN91X_IAR2     MakeRegister (1, 0x6)           // Individual Address Register 2\r
#define LAN91X_IAR3     MakeRegister (1, 0x7)           // Individual Address Register 3\r
#define LAN91X_IAR4     MakeRegister (1, 0x8)           // Individual Address Register 4\r
#define LAN91X_IAR5     MakeRegister (1, 0x9)           // Individual Address Register 5\r
#define LAN91X_GPR      MakeRegister (1, 0xa)           // General Purpose Register\r
#define LAN91X_CTR      MakeRegister (1, 0xc)           // Control Register\r
\r
#define LAN91X_MMUCR    MakeRegister (2, 0x0)           // MMU Command Register\r
#define LAN91X_PNR      MakeRegister (2, 0x2)           // Packet Number Register\r
#define LAN91X_ARR      MakeRegister (2, 0x3)           // Allocation Result Register\r
#define LAN91X_FIFO     MakeRegister (2, 0x4)           // FIFO Ports Register\r
#define LAN91X_PTR      MakeRegister (2, 0x6)           // Pointer Register\r
#define LAN91X_DATA0    MakeRegister (2, 0x8)           // Data Register 0\r
#define LAN91X_DATA1    MakeRegister (2, 0x9)           // Data Register 1\r
#define LAN91X_DATA2    MakeRegister (2, 0xa)           // Data Register 2\r
#define LAN91X_DATA3    MakeRegister (2, 0xb)           // Data Register 3\r
#define LAN91X_IST      MakeRegister (2, 0xc)           // Interrupt Status Register\r
#define LAN91X_MSK      MakeRegister (2, 0xd)           // Interrupt Mask Register\r
\r
#define LAN91X_MT0      MakeRegister (3, 0x0)           // Multicast Table Register 0\r
#define LAN91X_MT1      MakeRegister (3, 0x1)           // Multicast Table Register 1\r
#define LAN91X_MT2      MakeRegister (3, 0x2)           // Multicast Table Register 2\r
#define LAN91X_MT3      MakeRegister (3, 0x3)           // Multicast Table Register 3\r
#define LAN91X_MT4      MakeRegister (3, 0x4)           // Multicast Table Register 4\r
#define LAN91X_MT5      MakeRegister (3, 0x5)           // Multicast Table Register 5\r
#define LAN91X_MT6      MakeRegister (3, 0x6)           // Multicast Table Register 6\r
#define LAN91X_MT7      MakeRegister (3, 0x7)           // Multicast Table Register 7\r
#define LAN91X_MGMT     MakeRegister (3, 0x8)           // Management Interface Register\r
#define LAN91X_REV      MakeRegister (3, 0xa)           // Revision Register\r
#define LAN91X_RCV      MakeRegister (3, 0xc)           // RCV Register\r
\r
// Transmit Control Register Bits\r
#define TCR_TXENA       BIT0\r
#define TCR_LOOP        BIT1\r
#define TCR_FORCOL      BIT2\r
#define TCR_PAD_EN      BIT7\r
#define TCR_NOCRC       BIT8\r
#define TCR_MON_CSN     BIT10\r
#define TCR_FDUPLX      BIT11\r
#define TCR_STP_SQET    BIT12\r
#define TCR_EPH_LOOP    BIT13\r
#define TCR_SWFDUP      BIT15\r
\r
#define TCR_DEFAULT     (TCR_TXENA | TCR_PAD_EN)\r
#define TCR_CLEAR       0x0\r
\r
// EPH Status Register Bits\r
#define EPHSR_TX_SUC    BIT0\r
#define EPHSR_SNGLCOL   BIT1\r
#define EPHSR_MULCOL    BIT2\r
#define EPHSR_LTX_MULT  BIT3\r
#define EPHSR_16COL     BIT4\r
#define EPHSR_SQET      BIT5\r
#define EPHSR_LTX_BRD   BIT6\r
#define EPHSR_TX_DEFR   BIT7\r
#define EPHSR_LATCOL    BIT9\r
#define EPHSR_LOST_CARR BIT10\r
#define EPHSR_EXC_DEF   BIT11\r
#define EPHSR_CTR_ROL   BIT12\r
#define EPHSR_LINK_OK   BIT14\r
\r
// Receive Control Register Bits\r
#define RCR_RX_ABORT    BIT0\r
#define RCR_PRMS        BIT1\r
#define RCR_ALMUL       BIT2\r
#define RCR_RXEN        BIT8\r
#define RCR_STRIP_CRC   BIT9\r
#define RCR_ABORT_ENB   BIT13\r
#define RCR_FILT_CAR    BIT14\r
#define RCR_SOFT_RST    BIT15\r
\r
#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)\r
#define RCR_CLEAR       0x0\r
\r
// Receive/Phy Control Register Bits\r
#define RPCR_LS0B       BIT2\r
#define RPCR_LS1B       BIT3\r
#define RPCR_LS2B       BIT4\r
#define RPCR_LS0A       BIT5\r
#define RPCR_LS1A       BIT6\r
#define RPCR_LS2A       BIT7\r
#define RPCR_ANEG       BIT11\r
#define RPCR_DPLX       BIT12\r
#define RPCR_SPEED      BIT13\r
\r
// Configuration Register Bits\r
#define CR_EXT_PHY      BIT9\r
#define CR_GPCNTRL      BIT10\r
#define CR_NO_WAIT      BIT12\r
#define CR_EPH_POWER_EN BIT15\r
\r
#define CR_DEFAULT      (CR_EPH_POWER_EN | CR_NO_WAIT)\r
\r
// Control Register Bits\r
#define CTR_STORE       BIT0\r
#define CTR_RELOAD      BIT1\r
#define CTR_EEPROM_SEL  BIT2\r
#define CTR_TE_ENABLE   BIT5\r
#define CTR_CR_ENABLE   BIT6\r
#define CTR_LE_ENABLE   BIT7\r
#define CTR_AUTO_REL    BIT11\r
#define CTR_RCV_BAD     BIT14\r
\r
#define CTR_RESERVED    (BIT12 | BIT9 | BIT4)\r
#define CTR_DEFAULT     (CTR_RESERVED | CTR_AUTO_REL)\r
\r
// MMU Command Register Bits\r
#define MMUCR_BUSY      BIT0\r
\r
// MMU Command Register Operaction Codes\r
#define MMUCR_OP_NOOP           (0 << 5)        // No operation\r
#define MMUCR_OP_TX_ALLOC       (1 << 5)        // Allocate memory for TX\r
#define MMUCR_OP_RESET_MMU      (2 << 5)        // Reset MMU to initial state\r
#define MMUCR_OP_RX_POP         (3 << 5)        // Remove frame from top of RX FIFO\r
#define MMUCR_OP_RX_POP_REL     (4 << 5)        // Remove and release frame from top of RX FIFO\r
#define MMUCR_OP_RX_REL         (5 << 5)        // Release specific RX frame\r
#define MMUCR_OP_TX_PUSH        (6 << 5)        // Enqueue packet number into TX FIFO\r
#define MMUCR_OP_TX_RESET       (7 << 5)        // Reset TX FIFOs\r
\r
// Packet Number Register Bits\r
#define PNR_PACKET      (0x3f)\r
\r
// Allocation Result Register Bits\r
#define ARR_PACKET      (0x3f)\r
#define ARR_FAILED      BIT7\r
\r
// FIFO Ports Register Bits\r
#define FIFO_TX_PACKET  (0x003f)\r
#define FIFO_TEMPTY     BIT7\r
#define FIFO_RX_PACKET  (0x3f00)\r
#define FIFO_REMPTY     BIT15\r
\r
// Pointer Register Bits\r
#define PTR_POINTER     (0x07ff)\r
#define PTR_NOT_EMPTY   BIT11\r
#define PTR_READ        BIT13\r
#define PTR_AUTO_INCR   BIT14\r
#define PTR_RCV         BIT15\r
\r
// Interrupt Status and Mask Register Bits\r
#define IST_RCV         BIT0\r
#define IST_TX          BIT1\r
#define IST_TX_EMPTY    BIT2\r
#define IST_ALLOC       BIT3\r
#define IST_RX_OVRN     BIT4\r
#define IST_EPH         BIT5\r
#define IST_MD          BIT7\r
\r
// Management Interface\r
#define MGMT_MDO        BIT0\r
#define MGMT_MDI        BIT1\r
#define MGMT_MCLK       BIT2\r
#define MGMT_MDOE       BIT3\r
#define MGMT_MSK_CRS100 BIT14\r
\r
// RCV Register\r
#define RCV_MBO         (0x1f)\r
#define RCV_RCV_DISCRD  BIT7\r
\r
// Packet RX Status word bits\r
#define RX_MULTICAST    BIT0\r
#define RX_HASH         (0x7e)\r
#define RX_TOO_SHORT    BIT10\r
#define RX_TOO_LONG     BIT11\r
#define RX_ODD_FRAME    BIT12\r
#define RX_BAD_CRC      BIT13\r
#define RX_BROADCAST    BIT14\r
#define RX_ALGN_ERR     BIT15\r
\r
// Packet Byte Count word bits\r
#define BCW_COUNT       (0x7fe)\r
\r
// Packet Control Word bits\r
#define PCW_ODD_BYTE    (0x00ff)\r
#define PCW_CRC         BIT12\r
#define PCW_ODD         BIT13\r
\r
/*---------------------------------------------------------------------------------------------------------------------\r
\r
        SMSC PHY Registers\r
\r
        Most of these should be common, as there is\r
        documented STANDARD for PHY registers!\r
\r
---------------------------------------------------------------------------------------------------------------------*/\r
//\r
// PHY Register Numbers\r
//\r
#define PHY_INDEX_BASIC_CTRL              0\r
#define PHY_INDEX_BASIC_STATUS            1\r
#define PHY_INDEX_ID1                     2\r
#define PHY_INDEX_ID2                     3\r
#define PHY_INDEX_AUTO_NEG_ADVERT         4\r
#define PHY_INDEX_AUTO_NEG_LINK_ABILITY   5\r
\r
#define PHY_INDEX_CONFIG1                 16\r
#define PHY_INDEX_CONFIG2                 17\r
#define PHY_INDEX_STATUS_OUTPUT           18\r
#define PHY_INDEX_MASK                    19\r
\r
\r
// PHY control register bits\r
#define PHYCR_COLL_TEST                       BIT7                  // Collision test enable\r
#define PHYCR_DUPLEX_MODE                     BIT8                  // Set Duplex Mode\r
#define PHYCR_RST_AUTO                        BIT9                  // Restart Auto-Negotiation of Link abilities\r
#define PHYCR_PD                              BIT11                 // Power-Down switch\r
#define PHYCR_AUTO_EN                         BIT12                 // Auto-Negotiation Enable\r
#define PHYCR_SPEED_SEL                       BIT13                 // Link Speed Selection\r
#define PHYCR_LOOPBK                          BIT14                 // Set loopback mode\r
#define PHYCR_RESET                           BIT15                 // Do a PHY reset\r
\r
// PHY status register bits\r
#define PHYSTS_EXT_CAP                        BIT0                  // Extended Capabilities Register capability\r
#define PHYSTS_JABBER                         BIT1                  // Jabber condition detected\r
#define PHYSTS_LINK_STS                       BIT2                  // Link Status\r
#define PHYSTS_AUTO_CAP                       BIT3                  // Auto-Negotiation Capability\r
#define PHYSTS_REMOTE_FAULT                   BIT4                  // Remote fault detected\r
#define PHYSTS_AUTO_COMP                      BIT5                  // Auto-Negotiation Completed\r
#define PHYSTS_10BASET_HDPLX                  BIT11                 // 10Mbps Half-Duplex ability\r
#define PHYSTS_10BASET_FDPLX                  BIT12                 // 10Mbps Full-Duplex ability\r
#define PHYSTS_100BASETX_HDPLX                BIT13                 // 100Mbps Half-Duplex ability\r
#define PHYSTS_100BASETX_FDPLX                BIT14                 // 100Mbps Full-Duplex ability\r
#define PHYSTS_100BASE_T4                     BIT15                 // Base T4 ability\r
\r
// PHY Auto-Negotiation advertisement\r
#define PHYANA_SEL_MASK                       ((UINT32)0x1F)        // Link type selector\r
#define PHYANA_CSMA                           BIT0                  // Advertise CSMA capability\r
#define PHYANA_10BASET                        BIT5                  // Advertise 10BASET capability\r
#define PHYANA_10BASETFD                      BIT6                  // Advertise 10BASET Full duplex capability\r
#define PHYANA_100BASETX                      BIT7                  // Advertise 100BASETX capability\r
#define PHYANA_100BASETXFD                    BIT8                  // Advertise 100 BASETX Full duplex capability\r
#define PHYANA_100BASET4                      BIT9                  // Advertise 100 BASETX Full duplex capability\r
#define PHYANA_PAUSE_OP_MASK                  (3 << 10)             // Advertise PAUSE frame capability\r
#define PHYANA_REMOTE_FAULT                   BIT13                 // Remote fault detected\r
\r
#endif /* __LAN91XDXEHW_H__ */\r
Commit	Line	Data
4395f82e LL	1	/** @file\r
	2	* SMSC LAN91x series Network Controller Driver.\r
	3	*\r
	4	* Copyright (c) 2013-2017 Linaro.org\r
	5	*\r
878b807a	6	* SPDX-License-Identifier: BSD-2-Clause-Patent\r
4395f82e LL	7	*\r
	8	**/\r
	9	\r
	10	#ifndef __LAN91XDXEHW_H__\r
	11	#define __LAN91XDXEHW_H__\r
	12	\r
	13	#include <Base.h>\r
	14	\r
	15	#define MakeRegister(Bank, Offset) (((Bank) << 8) \| (Offset))\r
	16	#define RegisterToBank(Register) (((Register) >> 8) & 0x07)\r
	17	#define RegisterToOffset(Register) ((Register) & 0x0f)\r
	18	\r
	19	/*---------------------------------------------------------------------------------------------------------------------\r
	20	\r
	21	SMSC LAN91x Registers\r
	22	\r
	23	---------------------------------------------------------------------------------------------------------------------*/\r
	24	#define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks)\r
	25	\r
	26	#define LAN91X_TCR MakeRegister (0, 0x0) // Transmit Control Register\r
	27	#define LAN91X_EPHSR MakeRegister (0, 0x2) // EPH Status Register\r
	28	#define LAN91X_RCR MakeRegister (0, 0x4) // Receive Control Register\r
	29	#define LAN91X_ECR MakeRegister (0, 0x6) // Counter Register\r
	30	#define LAN91X_MIR MakeRegister (0, 0x8) // Memory Information Register\r
	31	#define LAN91X_RPCR MakeRegister (0, 0xa) // Receive/Phy Control Register\r
	32	\r
	33	#define LAN91X_CR MakeRegister (1, 0x0) // Configuration Register\r
	34	#define LAN91X_BAR MakeRegister (1, 0x2) // Base Address Register\r
	35	#define LAN91X_IAR0 MakeRegister (1, 0x4) // Individual Address Register 0\r
	36	#define LAN91X_IAR1 MakeRegister (1, 0x5) // Individual Address Register 1\r
	37	#define LAN91X_IAR2 MakeRegister (1, 0x6) // Individual Address Register 2\r
	38	#define LAN91X_IAR3 MakeRegister (1, 0x7) // Individual Address Register 3\r
	39	#define LAN91X_IAR4 MakeRegister (1, 0x8) // Individual Address Register 4\r
	40	#define LAN91X_IAR5 MakeRegister (1, 0x9) // Individual Address Register 5\r
	41	#define LAN91X_GPR MakeRegister (1, 0xa) // General Purpose Register\r
	42	#define LAN91X_CTR MakeRegister (1, 0xc) // Control Register\r
	43	\r
	44	#define LAN91X_MMUCR MakeRegister (2, 0x0) // MMU Command Register\r
	45	#define LAN91X_PNR MakeRegister (2, 0x2) // Packet Number Register\r
	46	#define LAN91X_ARR MakeRegister (2, 0x3) // Allocation Result Register\r
	47	#define LAN91X_FIFO MakeRegister (2, 0x4) // FIFO Ports Register\r
	48	#define LAN91X_PTR MakeRegister (2, 0x6) // Pointer Register\r
	49	#define LAN91X_DATA0 MakeRegister (2, 0x8) // Data Register 0\r
	50	#define LAN91X_DATA1 MakeRegister (2, 0x9) // Data Register 1\r
	51	#define LAN91X_DATA2 MakeRegister (2, 0xa) // Data Register 2\r
	52	#define LAN91X_DATA3 MakeRegister (2, 0xb) // Data Register 3\r
	53	#define LAN91X_IST MakeRegister (2, 0xc) // Interrupt Status Register\r
	54	#define LAN91X_MSK MakeRegister (2, 0xd) // Interrupt Mask Register\r
	55	\r
	56	#define LAN91X_MT0 MakeRegister (3, 0x0) // Multicast Table Register 0\r
	57	#define LAN91X_MT1 MakeRegister (3, 0x1) // Multicast Table Register 1\r
	58	#define LAN91X_MT2 MakeRegister (3, 0x2) // Multicast Table Register 2\r
	59	#define LAN91X_MT3 MakeRegister (3, 0x3) // Multicast Table Register 3\r
	60	#define LAN91X_MT4 MakeRegister (3, 0x4) // Multicast Table Register 4\r
	61	#define LAN91X_MT5 MakeRegister (3, 0x5) // Multicast Table Register 5\r
	62	#define LAN91X_MT6 MakeRegister (3, 0x6) // Multicast Table Register 6\r
	63	#define LAN91X_MT7 MakeRegister (3, 0x7) // Multicast Table Register 7\r
	64	#define LAN91X_MGMT MakeRegister (3, 0x8) // Management Interface Register\r
	65	#define LAN91X_REV MakeRegister (3, 0xa) // Revision Register\r
	66	#define LAN91X_RCV MakeRegister (3, 0xc) // RCV Register\r
	67	\r
	68	// Transmit Control Register Bits\r
	69	#define TCR_TXENA BIT0\r
	70	#define TCR_LOOP BIT1\r
71	#define TCR_FORCOL BIT2\r
72	#define TCR_PAD_EN BIT7\r
73	#define TCR_NOCRC BIT8\r
74	#define TCR_MON_CSN BIT10\r
75	#define TCR_FDUPLX BIT11\r
76	#define TCR_STP_SQET BIT12\r
77	#define TCR_EPH_LOOP BIT13\r
78	#define TCR_SWFDUP BIT15\r
79	\r
80	#define TCR_DEFAULT (TCR_TXENA \| TCR_PAD_EN)\r
81	#define TCR_CLEAR 0x0\r
82	\r
83	// EPH Status Register Bits\r
84	#define EPHSR_TX_SUC BIT0\r
85	#define EPHSR_SNGLCOL BIT1\r
86	#define EPHSR_MULCOL BIT2\r
87	#define EPHSR_LTX_MULT BIT3\r
88	#define EPHSR_16COL BIT4\r
89	#define EPHSR_SQET BIT5\r
90	#define EPHSR_LTX_BRD BIT6\r
91	#define EPHSR_TX_DEFR BIT7\r
92	#define EPHSR_LATCOL BIT9\r
93	#define EPHSR_LOST_CARR BIT10\r
94	#define EPHSR_EXC_DEF BIT11\r
95	#define EPHSR_CTR_ROL BIT12\r
96	#define EPHSR_LINK_OK BIT14\r
97	\r
98	// Receive Control Register Bits\r
99	#define RCR_RX_ABORT BIT0\r
100	#define RCR_PRMS BIT1\r
101	#define RCR_ALMUL BIT2\r
102	#define RCR_RXEN BIT8\r
103	#define RCR_STRIP_CRC BIT9\r
104	#define RCR_ABORT_ENB BIT13\r
105	#define RCR_FILT_CAR BIT14\r
106	#define RCR_SOFT_RST BIT15\r
107	\r
108	#define RCR_DEFAULT (RCR_STRIP_CRC \| RCR_RXEN)\r
109	#define RCR_CLEAR 0x0\r
110	\r
111	// Receive/Phy Control Register Bits\r
112	#define RPCR_LS0B BIT2\r
113	#define RPCR_LS1B BIT3\r
114	#define RPCR_LS2B BIT4\r
115	#define RPCR_LS0A BIT5\r
116	#define RPCR_LS1A BIT6\r
117	#define RPCR_LS2A BIT7\r
118	#define RPCR_ANEG BIT11\r
119	#define RPCR_DPLX BIT12\r
120	#define RPCR_SPEED BIT13\r
121	\r
122	// Configuration Register Bits\r
123	#define CR_EXT_PHY BIT9\r
124	#define CR_GPCNTRL BIT10\r
125	#define CR_NO_WAIT BIT12\r
126	#define CR_EPH_POWER_EN BIT15\r
127	\r
128	#define CR_DEFAULT (CR_EPH_POWER_EN \| CR_NO_WAIT)\r
129	\r
130	// Control Register Bits\r
131	#define CTR_STORE BIT0\r
132	#define CTR_RELOAD BIT1\r
133	#define CTR_EEPROM_SEL BIT2\r
134	#define CTR_TE_ENABLE BIT5\r
135	#define CTR_CR_ENABLE BIT6\r
136	#define CTR_LE_ENABLE BIT7\r
137	#define CTR_AUTO_REL BIT11\r
138	#define CTR_RCV_BAD BIT14\r
139	\r
140	#define CTR_RESERVED (BIT12 \| BIT9 \| BIT4)\r
141	#define CTR_DEFAULT (CTR_RESERVED \| CTR_AUTO_REL)\r
142	\r
143	// MMU Command Register Bits\r
144	#define MMUCR_BUSY BIT0\r
145	\r
146	// MMU Command Register Operaction Codes\r
147	#define MMUCR_OP_NOOP (0 << 5) // No operation\r
148	#define MMUCR_OP_TX_ALLOC (1 << 5) // Allocate memory for TX\r
149	#define MMUCR_OP_RESET_MMU (2 << 5) // Reset MMU to initial state\r
150	#define MMUCR_OP_RX_POP (3 << 5) // Remove frame from top of RX FIFO\r
151	#define MMUCR_OP_RX_POP_REL (4 << 5) // Remove and release frame from top of RX FIFO\r
152	#define MMUCR_OP_RX_REL (5 << 5) // Release specific RX frame\r
153	#define MMUCR_OP_TX_PUSH (6 << 5) // Enqueue packet number into TX FIFO\r
154	#define MMUCR_OP_TX_RESET (7 << 5) // Reset TX FIFOs\r
155	\r
156	// Packet Number Register Bits\r
157	#define PNR_PACKET (0x3f)\r
158	\r
159	// Allocation Result Register Bits\r
160	#define ARR_PACKET (0x3f)\r
161	#define ARR_FAILED BIT7\r
162	\r
163	// FIFO Ports Register Bits\r
164	#define FIFO_TX_PACKET (0x003f)\r
165	#define FIFO_TEMPTY BIT7\r
166	#define FIFO_RX_PACKET (0x3f00)\r
167	#define FIFO_REMPTY BIT15\r
168	\r
169	// Pointer Register Bits\r
170	#define PTR_POINTER (0x07ff)\r
171	#define PTR_NOT_EMPTY BIT11\r
172	#define PTR_READ BIT13\r
173	#define PTR_AUTO_INCR BIT14\r
174	#define PTR_RCV BIT15\r
175	\r
c6a72cd7	176	// Interrupt Status and Mask Register Bits\r
4395f82e LL	177	#define IST_RCV BIT0\r
	178	#define IST_TX BIT1\r
	179	#define IST_TX_EMPTY BIT2\r
	180	#define IST_ALLOC BIT3\r
	181	#define IST_RX_OVRN BIT4\r
	182	#define IST_EPH BIT5\r
	183	#define IST_MD BIT7\r
	184	\r
	185	// Management Interface\r
	186	#define MGMT_MDO BIT0\r
	187	#define MGMT_MDI BIT1\r
	188	#define MGMT_MCLK BIT2\r
	189	#define MGMT_MDOE BIT3\r
	190	#define MGMT_MSK_CRS100 BIT14\r
	191	\r
	192	// RCV Register\r
	193	#define RCV_MBO (0x1f)\r
	194	#define RCV_RCV_DISCRD BIT7\r
	195	\r
	196	// Packet RX Status word bits\r
	197	#define RX_MULTICAST BIT0\r
	198	#define RX_HASH (0x7e)\r
	199	#define RX_TOO_SHORT BIT10\r
	200	#define RX_TOO_LONG BIT11\r
	201	#define RX_ODD_FRAME BIT12\r
	202	#define RX_BAD_CRC BIT13\r
	203	#define RX_BROADCAST BIT14\r
	204	#define RX_ALGN_ERR BIT15\r
	205	\r
	206	// Packet Byte Count word bits\r
	207	#define BCW_COUNT (0x7fe)\r
	208	\r
	209	// Packet Control Word bits\r
	210	#define PCW_ODD_BYTE (0x00ff)\r
	211	#define PCW_CRC BIT12\r
	212	#define PCW_ODD BIT13\r
	213	\r
	214	/*---------------------------------------------------------------------------------------------------------------------\r
	215	\r
	216	SMSC PHY Registers\r
	217	\r
	218	Most of these should be common, as there is\r
	219	documented STANDARD for PHY registers!\r
	220	\r
	221	---------------------------------------------------------------------------------------------------------------------*/\r
	222	//\r
	223	// PHY Register Numbers\r
	224	//\r
	225	#define PHY_INDEX_BASIC_CTRL 0\r
	226	#define PHY_INDEX_BASIC_STATUS 1\r
	227	#define PHY_INDEX_ID1 2\r
	228	#define PHY_INDEX_ID2 3\r
	229	#define PHY_INDEX_AUTO_NEG_ADVERT 4\r
	230	#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5\r
	231	\r
	232	#define PHY_INDEX_CONFIG1 16\r
	233	#define PHY_INDEX_CONFIG2 17\r
	234	#define PHY_INDEX_STATUS_OUTPUT 18\r
	235	#define PHY_INDEX_MASK 19\r
	236	\r
	237	\r
	238	// PHY control register bits\r
	239	#define PHYCR_COLL_TEST BIT7 // Collision test enable\r
	240	#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode\r
241	#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities\r
242	#define PHYCR_PD BIT11 // Power-Down switch\r
243	#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable\r
244	#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection\r
245	#define PHYCR_LOOPBK BIT14 // Set loopback mode\r
246	#define PHYCR_RESET BIT15 // Do a PHY reset\r
247	\r
248	// PHY status register bits\r
249	#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability\r
250	#define PHYSTS_JABBER BIT1 // Jabber condition detected\r
251	#define PHYSTS_LINK_STS BIT2 // Link Status\r
252	#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability\r
253	#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected\r
254	#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed\r
255	#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability\r
256	#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability\r
257	#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability\r
258	#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability\r
259	#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability\r
260	\r
261	// PHY Auto-Negotiation advertisement\r
262	#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector\r
263	#define PHYANA_CSMA BIT0 // Advertise CSMA capability\r
264	#define PHYANA_10BASET BIT5 // Advertise 10BASET capability\r
265	#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability\r
266	#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability\r
267	#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability\r
268	#define PHYANA_100BASET4 BIT9 // Advertise 100 BASETX Full duplex capability\r
269	#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability\r
270	#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected\r
271	\r
272	#endif /* __LAN91XDXEHW_H__ */\r