ArmPkg: only attempt buildin MmCommunicationDxe for AArch64
[mirror_edk2.git] / EmbeddedPkg / Include / Protocol / MmcHost.h
CommitLineData
1bfda055 1/** @file\r
2 Definition of the MMC Host Protocol\r
3\r
b4fdedc2 4 Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
3402aac7 5\r
878b807a 6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
1bfda055 7\r
8**/\r
9\r
10#ifndef __MMC_HOST_H__\r
11#define __MMC_HOST_H__\r
12\r
13///\r
14/// Global ID for the MMC Host Protocol\r
15///\r
2a7a1223 16#define EMBEDDED_MMC_HOST_PROTOCOL_GUID \\r
1bfda055 17 { 0x3e591c00, 0x9e4a, 0x11df, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xD5, 0xC5, 0x1B } }\r
18\r
19#define MMC_RESPONSE_TYPE_R1 0\r
20#define MMC_RESPONSE_TYPE_R1b 0\r
21#define MMC_RESPONSE_TYPE_R2 1\r
22#define MMC_RESPONSE_TYPE_R3 0\r
23#define MMC_RESPONSE_TYPE_R6 0\r
24#define MMC_RESPONSE_TYPE_R7 0\r
25#define MMC_RESPONSE_TYPE_OCR 0\r
26#define MMC_RESPONSE_TYPE_CID 1\r
27#define MMC_RESPONSE_TYPE_CSD 1\r
28#define MMC_RESPONSE_TYPE_RCA 0\r
29\r
30typedef UINT32 MMC_RESPONSE_TYPE;\r
31\r
32typedef UINT32 MMC_CMD;\r
33\r
34#define MMC_CMD_WAIT_RESPONSE (1 << 16)\r
35#define MMC_CMD_LONG_RESPONSE (1 << 17)\r
2b826e73 36#define MMC_CMD_NO_CRC_RESPONSE (1 << 18)\r
1bfda055 37\r
2b826e73 38#define MMC_INDX(Index) ((Index) & 0xFFFF)\r
39#define MMC_GET_INDX(MmcCmd) ((MmcCmd) & 0xFFFF)\r
1bfda055 40\r
2b826e73 41#define MMC_CMD0 (MMC_INDX(0) | MMC_CMD_NO_CRC_RESPONSE)\r
42#define MMC_CMD1 (MMC_INDX(1) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)\r
1bfda055 43#define MMC_CMD2 (MMC_INDX(2) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)\r
44#define MMC_CMD3 (MMC_INDX(3) | MMC_CMD_WAIT_RESPONSE)\r
2b826e73 45#define MMC_CMD5 (MMC_INDX(5) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)\r
a28b9aef 46#define MMC_CMD6 (MMC_INDX(6) | MMC_CMD_WAIT_RESPONSE)\r
1bfda055 47#define MMC_CMD7 (MMC_INDX(7) | MMC_CMD_WAIT_RESPONSE)\r
48#define MMC_CMD8 (MMC_INDX(8) | MMC_CMD_WAIT_RESPONSE)\r
49#define MMC_CMD9 (MMC_INDX(9) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)\r
50#define MMC_CMD11 (MMC_INDX(11) | MMC_CMD_WAIT_RESPONSE)\r
51#define MMC_CMD12 (MMC_INDX(12) | MMC_CMD_WAIT_RESPONSE)\r
52#define MMC_CMD13 (MMC_INDX(13) | MMC_CMD_WAIT_RESPONSE)\r
53#define MMC_CMD16 (MMC_INDX(16) | MMC_CMD_WAIT_RESPONSE)\r
54#define MMC_CMD17 (MMC_INDX(17) | MMC_CMD_WAIT_RESPONSE)\r
55#define MMC_CMD18 (MMC_INDX(18) | MMC_CMD_WAIT_RESPONSE)\r
56#define MMC_CMD20 (MMC_INDX(20) | MMC_CMD_WAIT_RESPONSE)\r
57#define MMC_CMD23 (MMC_INDX(23) | MMC_CMD_WAIT_RESPONSE)\r
58#define MMC_CMD24 (MMC_INDX(24) | MMC_CMD_WAIT_RESPONSE)\r
a28b9aef 59#define MMC_CMD25 (MMC_INDX(25) | MMC_CMD_WAIT_RESPONSE)\r
1bfda055 60#define MMC_CMD55 (MMC_INDX(55) | MMC_CMD_WAIT_RESPONSE)\r
2b826e73 61#define MMC_ACMD41 (MMC_INDX(41) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)\r
a28b9aef 62#define MMC_ACMD51 (MMC_INDX(51) | MMC_CMD_WAIT_RESPONSE)\r
1bfda055 63\r
b4fdedc2
OM
64// Valid responses for CMD1 in eMMC\r
65#define EMMC_CMD1_CAPACITY_LESS_THAN_2GB 0x00FF8080 // Capacity <= 2GB, byte addressing used\r
66#define EMMC_CMD1_CAPACITY_GREATER_THAN_2GB 0x40FF8080 // Capacity > 2GB, 512-byte sector addressing used\r
67\r
a28b9aef
HZ
68#define MMC_STATUS_APP_CMD (1 << 5)\r
69\r
1bfda055 70typedef enum _MMC_STATE {\r
71 MmcInvalidState = 0,\r
72 MmcHwInitializationState,\r
73 MmcIdleState,\r
74 MmcReadyState,\r
75 MmcIdentificationState,\r
76 MmcStandByState,\r
77 MmcTransferState,\r
78 MmcSendingDataState,\r
79 MmcReceiveDataState,\r
80 MmcProgrammingState,\r
81 MmcDisconnectState,\r
82} MMC_STATE;\r
83\r
a28b9aef
HZ
84#define EMMCBACKWARD (0)\r
85#define EMMCHS26 (1 << 0) // High-Speed @26MHz at rated device voltages\r
86#define EMMCHS52 (1 << 1) // High-Speed @52MHz at rated device voltages\r
87#define EMMCHS52DDR1V8 (1 << 2) // High-Speed Dual Data Rate @52MHz 1.8V or 3V I/O\r
88#define EMMCHS52DDR1V2 (1 << 3) // High-Speed Dual Data Rate @52MHz 1.2V I/O\r
89#define EMMCHS200SDR1V8 (1 << 4) // HS200 Single Data Rate @200MHz 1.8V I/O\r
90#define EMMCHS200SDR1V2 (1 << 5) // HS200 Single Data Rate @200MHz 1.2V I/O\r
91#define EMMCHS400DDR1V8 (1 << 6) // HS400 Dual Data Rate @400MHz 1.8V I/O\r
92#define EMMCHS400DDR1V2 (1 << 7) // HS400 Dual Data Rate @400MHz 1.2V I/O\r
93\r
16d88c2d 94///\r
95/// Forward declaration for EFI_MMC_HOST_PROTOCOL\r
96///\r
97typedef struct _EFI_MMC_HOST_PROTOCOL EFI_MMC_HOST_PROTOCOL;\r
98\r
99typedef BOOLEAN (EFIAPI *MMC_ISCARDPRESENT) (\r
100 IN EFI_MMC_HOST_PROTOCOL *This\r
101 );\r
102\r
103typedef BOOLEAN (EFIAPI *MMC_ISREADONLY) (\r
104 IN EFI_MMC_HOST_PROTOCOL *This\r
105 );\r
106\r
107typedef EFI_STATUS (EFIAPI *MMC_BUILDDEVICEPATH) (\r
108 IN EFI_MMC_HOST_PROTOCOL *This,\r
109 OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
110 );\r
111\r
112typedef EFI_STATUS (EFIAPI *MMC_NOTIFYSTATE) (\r
113 IN EFI_MMC_HOST_PROTOCOL *This,\r
114 IN MMC_STATE State\r
115 );\r
116\r
117typedef EFI_STATUS (EFIAPI *MMC_SENDCOMMAND) (\r
118 IN EFI_MMC_HOST_PROTOCOL *This,\r
119 IN MMC_CMD Cmd,\r
120 IN UINT32 Argument\r
121 );\r
122\r
123typedef EFI_STATUS (EFIAPI *MMC_RECEIVERESPONSE) (\r
124 IN EFI_MMC_HOST_PROTOCOL *This,\r
125 IN MMC_RESPONSE_TYPE Type,\r
126 IN UINT32 *Buffer\r
127 );\r
128\r
129typedef EFI_STATUS (EFIAPI *MMC_READBLOCKDATA) (\r
130 IN EFI_MMC_HOST_PROTOCOL *This,\r
131 IN EFI_LBA Lba,\r
132 IN UINTN Length,\r
133 OUT UINT32 *Buffer\r
134 );\r
135\r
136typedef EFI_STATUS (EFIAPI *MMC_WRITEBLOCKDATA) (\r
137 IN EFI_MMC_HOST_PROTOCOL *This,\r
138 IN EFI_LBA Lba,\r
139 IN UINTN Length,\r
140 IN UINT32 *Buffer\r
141 );\r
1bfda055 142\r
a28b9aef
HZ
143typedef EFI_STATUS (EFIAPI *MMC_SETIOS) (\r
144 IN EFI_MMC_HOST_PROTOCOL *This,\r
145 IN UINT32 BusClockFreq,\r
146 IN UINT32 BusWidth,\r
147 IN UINT32 TimingMode\r
148 );\r
149\r
150typedef BOOLEAN (EFIAPI *MMC_ISMULTIBLOCK) (\r
151 IN EFI_MMC_HOST_PROTOCOL *This\r
152 );\r
1bfda055 153\r
6b062a86 154struct _EFI_MMC_HOST_PROTOCOL {\r
1bfda055 155\r
16d88c2d 156 UINT32 Revision;\r
157 MMC_ISCARDPRESENT IsCardPresent;\r
158 MMC_ISREADONLY IsReadOnly;\r
159 MMC_BUILDDEVICEPATH BuildDevicePath;\r
1bfda055 160\r
16d88c2d 161 MMC_NOTIFYSTATE NotifyState;\r
1bfda055 162\r
16d88c2d 163 MMC_SENDCOMMAND SendCommand;\r
164 MMC_RECEIVERESPONSE ReceiveResponse;\r
1bfda055 165\r
16d88c2d 166 MMC_READBLOCKDATA ReadBlockData;\r
167 MMC_WRITEBLOCKDATA WriteBlockData;\r
1bfda055 168\r
a28b9aef
HZ
169 MMC_SETIOS SetIos;\r
170 MMC_ISMULTIBLOCK IsMultiBlock;\r
171\r
6b062a86 172};\r
1bfda055 173\r
a28b9aef
HZ
174#define MMC_HOST_PROTOCOL_REVISION 0x00010002 // 1.2\r
175\r
176#define MMC_HOST_HAS_SETIOS(Host) (Host->Revision >= MMC_HOST_PROTOCOL_REVISION && \\r
177 Host->SetIos != NULL)\r
178#define MMC_HOST_HAS_ISMULTIBLOCK(Host) (Host->Revision >= MMC_HOST_PROTOCOL_REVISION && \\r
179 Host->IsMultiBlock != NULL)\r
16d88c2d 180\r
2a7a1223 181extern EFI_GUID gEmbeddedMmcHostProtocolGuid;\r
1bfda055 182\r
183#endif\r
184\r