[mirror_edk2.git] / EmbeddedPkg / Library / GdbDebugAgent / Arm / ExceptionSupport.ARMv6.S

#------------------------------------------------------------------------------ \r
#\r
# Use ARMv6 instruction to operate on a single stack\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#------------------------------------------------------------------------------\r
\r
/*\r
\r
This is the stack constructed by the exception handler (low address to high address)\r
                # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
  Reg   Offset\r
  ===   ======              \r
  R0    0x00    # stmfd     SP!,{R0-R12}\r
  R1    0x04\r
  R2    0x08\r
  R3    0x0c\r
  R4    0x10\r
  R5    0x14\r
  R6    0x18\r
  R7    0x1c\r
  R8    0x20\r
  R9    0x24\r
  R10   0x28\r
  R11   0x2c\r
  R12   0x30\r
  SP    0x34    # reserved via adding 0x20 (32) to the SP\r
  LR    0x38\r
  PC    0x3c\r
  CPSR  0x40\r
  DFSR  0x44\r
  DFAR  0x48\r
  IFSR  0x4c\r
  IFAR  0x50\r
  \r
  LR    0x54    # SVC Link register (we need to restore it)\r
  \r
  LR    0x58    # pushed by srsfd    \r
  CPSR  0x5c    \r
\r
 */\r
 \r
\r
GCC_ASM_EXPORT(ExceptionHandlersStart)\r
GCC_ASM_EXPORT(ExceptionHandlersEnd)\r
GCC_ASM_EXPORT(CommonExceptionEntry)\r
GCC_ASM_EXPORT(AsmCommonExceptionEntry)\r
GCC_ASM_EXPORT(GdbExceptionHandler)\r
\r
.text\r
.align 3\r
\r
\r
//\r
// This code gets copied to the ARM vector table\r
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r
//\r
ASM_PFX(ExceptionHandlersStart):\r
\r
ASM_PFX(Reset):\r
  b ASM_PFX(Reset)\r
\r
ASM_PFX(UndefinedInstruction):\r
  b ASM_PFX(UndefinedInstructionEntry)\r
\r
ASM_PFX(SoftwareInterrupt):\r
  b ASM_PFX(SoftwareInterruptEntry)\r
\r
ASM_PFX(PrefetchAbort):\r
  b ASM_PFX(PrefetchAbortEntry)\r
\r
ASM_PFX(DataAbort):\r
  b ASM_PFX(DataAbortEntry)\r
\r
ASM_PFX(ReservedException):\r
  b ASM_PFX(ReservedExceptionEntry)\r
\r
ASM_PFX(Irq):\r
  b ASM_PFX(Irq)\r
\r
ASM_PFX(Fiq):\r
  b ASM_PFX(FiqEntry)\r
\r
\r
ASM_PFX(UndefinedInstructionEntry):\r
  sub       LR, LR, #4                @ Only -2 for Thumb, adjust in CommonExceptionEntry\r
  srsdb     #0x13!                    @ Store return state on SVC stack\r
  cpsid     f,#0x13                   @ Switch to SVC for common stack\r
  stmfd     SP!,{LR}                  @ Store the link register for the current mode\r
  sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR\r
  stmfd     SP!,{R0-R12}              @ Store the register state\r
\r
  mov       R0,#1                     @ ExceptionType\r
  ldr       R1,ASM_PFX(CommonExceptionEntry)\r
  bx        R1\r
\r
ASM_PFX(SoftwareInterruptEntry):\r
  sub       LR, LR, #4                @ Only -2 for Thumb, adjust in CommonExceptionEntry\r
  srsdb     #0x13!                    @ Store return state on SVC stack\r
  cpsid     f                         @ We are already in SVC mode\r
  stmfd     SP!,{LR}                  @ Store the link register for the current mode\r
  sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR\r
  stmfd     SP!,{R0-R12}              @ Store the register state\r
\r
  mov       R0,#2                     @ ExceptionType\r
  ldr       R1,ASM_PFX(CommonExceptionEntry)\r
  bx        R1\r
\r
ASM_PFX(PrefetchAbortEntry):\r
  sub       LR,LR,#4\r
  srsdb     #0x13!                    @ Store return state on SVC stack\r
  cpsid     f,#0x13                   @ Switch to SVC for common stack\r
  stmfd     SP!,{LR}                  @ Store the link register for the current mode\r
  sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR\r
  stmfd     SP!,{R0-R12}              @ Store the register state\r
\r
  mov       R0,#3                     @ ExceptionType\r
  ldr       R1,ASM_PFX(CommonExceptionEntry)\r
  bx        R1\r
\r
ASM_PFX(DataAbortEntry):\r
  sub       LR,LR,#8\r
  srsdb     #0x13!                    @ Store return state on SVC stack\r
  cpsid     f,#0x13                   @ Switch to SVC for common stack\r
  stmfd     SP!,{LR}                  @ Store the link register for the current mode\r
  sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR\r
  stmfd     SP!,{R0-R12}              @ Store the register state\r
\r
  mov       R0,#4\r
  ldr       R1,ASM_PFX(CommonExceptionEntry)\r
  bx        R1\r
\r
ASM_PFX(ReservedExceptionEntry):\r
  srsdb     #0x13!                    @ Store return state on SVC stack\r
  cpsid     f,#0x13                   @ Switch to SVC for common stack\r
  stmfd     SP!,{LR}                  @ Store the link register for the current mode\r
  sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR\r
  stmfd     SP!,{R0-R12}              @ Store the register state\r
\r
  mov       R0,#5\r
  ldr       R1,ASM_PFX(CommonExceptionEntry)\r
  bx        R1\r
\r
ASM_PFX(FiqEntry):\r
  sub       LR,LR,#4\r
  srsdb     #0x13!                    @ Store return state on SVC stack\r
  cps       #0x13                     @ Switch to SVC for common stack\r
  stmfd     SP!,{LR}                  @ Store the link register for the current mode\r
  sub       SP,SP,#0x20               @ Save space for SP, LR, PC, IFAR - CPSR\r
  stmfd     SP!,{R0-R12}              @ Store the register state\r
                                      @ Since we have already switch to SVC R8_fiq - R12_fiq\r
                                      @ never get used or saved\r
  mov       R0,#7                     @ ExceptionType\r
  ldr       R1,ASM_PFX(CommonExceptionEntry)\r
  bx        R1\r
\r
//\r
// This gets patched by the C code that patches in the vector table\r
//\r
ASM_PFX(CommonExceptionEntry):\r
  .byte       0x12\r
  .byte       0x34\r
  .byte       0x56\r
  .byte       0x78\r
\r
ASM_PFX(ExceptionHandlersEnd):\r
\r
//\r
// This code runs from CpuDxe driver loaded address. It is patched into \r
// CommonExceptionEntry.\r
//\r
ASM_PFX(AsmCommonExceptionEntry):\r
  mrc       p15, 0, R1, c6, c0, 2   @ Read IFAR\r
  str       R1, [SP, #0x50]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
  \r
  mrc       p15, 0, R1, c5, c0, 1   @ Read IFSR\r
  str       R1, [SP, #0x4c]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
  \r
  mrc       p15, 0, R1, c6, c0, 0   @ Read DFAR\r
  str       R1, [SP, #0x48]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
  \r
  mrc       p15, 0, R1, c5, c0, 0   @ Read DFSR\r
  str       R1, [SP, #0x44]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
  \r
  ldr       R1, [SP, #0x5c]         @ srsdb saved pre-exception CPSR on the stack \r
  str       R1, [SP, #0x40]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
\r
  add       R2, SP, #0x38           @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
  and       R3, R1, #0x1f           @ Check CPSR to see if User or System Mode\r
  cmp       R3, #0x1f               @ if ((CPSR == 0x10) || (CPSR == 0x1df))\r
  cmpne     R3, #0x10               @   \r
  stmeqed   R2, {lr}^               @   save unbanked lr\r
                                    @ else \r
  stmneed   R2, {lr}                @   save SVC lr\r
\r
\r
  ldr       R5, [SP, #0x58]         @ PC is the LR pushed by srsfd \r
                                    @ Check to see if we have to adjust for Thumb entry\r
  sub       r4, r0, #1              @ if (ExceptionType == 1 || ExceptionType ==2)) {\r
  cmp       r4, #1                  @   // UND & SVC have differnt LR adjust for Thumb \r
  bhi       NoAdjustNeeded\r
  \r
  tst       r1, #0x20               @   if ((CPSR & T)) == T) {  // Thumb Mode on entry \r
  addne     R5, R5, #2              @     PC += 2@\r
  str       R5,[SP,#0x58]           @ Update LR value pused by srsfd \r
  \r
NoAdjustNeeded:\r
\r
  str       R5, [SP, #0x3c]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
  \r
  sub       R1, SP, #0x60           @ We pused 0x60 bytes on the stack \r
  str       R1, [SP, #0x34]         @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
  \r
                                    @ R0 is ExceptionType \r
  mov       R1,SP                   @ R1 is SystemContext \r
\r
/* \r
VOID\r
EFIAPI\r
GdbExceptionHandler (\r
  IN     EFI_EXCEPTION_TYPE           ExceptionType,   R0\r
  IN OUT EFI_SYSTEM_CONTEXT           SystemContext    R1\r
  )\r
\r
*/  \r
  blx       ASM_PFX(GdbExceptionHandler)  @ Call exception handler\r
  \r
  ldr       R1,[SP,#0x3c]           @ EFI_SYSTEM_CONTEXT_ARM.PC\r
  str       R1,[SP,#0x58]           @ Store it back to srsfd stack slot so it can be restored \r
\r
  ldr       R1,[SP,#0x40]           @ EFI_SYSTEM_CONTEXT_ARM.CPSR\r
  str       R1,[SP,#0x5c]           @ Store it back to srsfd stack slot so it can be restored \r
  \r
  add       R3, SP, #0x54           @ Make R3 point to SVC LR saved on entry\r
  add       R2, SP, #0x38           @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
  and       R1, R1, #0x1f           @ Check to see if User or System Mode\r
  cmp       R1, #0x1f               @ if ((CPSR == 0x10) || (CPSR == 0x1f))\r
  cmpne     R1, #0x10               @   \r
  ldmeqed   R2, {lr}^               @   restore unbanked lr\r
                                    @ else\r
  ldmneed   R3, {lr}                @   restore SVC lr, via ldmfd SP!, {LR}\r
  \r
  ldmfd     SP!,{R0-R12}            @ Restore general purpose registers\r
                                    @ Exception handler can not change SP\r
                                    \r
  add       SP,SP,#0x20             @ Clear out the remaining stack space\r
  ldmfd     SP!,{LR}                @ restore the link register for this context\r
  rfefd     SP!                     @ return from exception via srsfd stack slot\r
  \r
Commit	Line	Data
1e57a462	1	#------------------------------------------------------------------------------ \r
	2	#\r
	3	# Use ARMv6 instruction to operate on a single stack\r
	4	#\r
	5	# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
	6	#\r
	7	# This program and the accompanying materials\r
	8	# are licensed and made available under the terms and conditions of the BSD License\r
	9	# which accompanies this distribution. The full text of the license may be found at\r
	10	# http://opensource.org/licenses/bsd-license.php\r
	11	#\r
	12	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	#\r
	15	#------------------------------------------------------------------------------\r
	16	\r
	17	/*\r
	18	\r
	19	This is the stack constructed by the exception handler (low address to high address)\r
	20	# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
	21	Reg Offset\r
	22	=== ====== \r
	23	R0 0x00 # stmfd SP!,{R0-R12}\r
	24	R1 0x04\r
	25	R2 0x08\r
	26	R3 0x0c\r
	27	R4 0x10\r
	28	R5 0x14\r
	29	R6 0x18\r
	30	R7 0x1c\r
	31	R8 0x20\r
	32	R9 0x24\r
	33	R10 0x28\r
	34	R11 0x2c\r
	35	R12 0x30\r
	36	SP 0x34 # reserved via adding 0x20 (32) to the SP\r
	37	LR 0x38\r
	38	PC 0x3c\r
	39	CPSR 0x40\r
	40	DFSR 0x44\r
	41	DFAR 0x48\r
	42	IFSR 0x4c\r
	43	IFAR 0x50\r
	44	\r
	45	LR 0x54 # SVC Link register (we need to restore it)\r
	46	\r
	47	LR 0x58 # pushed by srsfd \r
	48	CPSR 0x5c \r
	49	\r
	50	*/\r
	51	\r
	52	\r
	53	GCC_ASM_EXPORT(ExceptionHandlersStart)\r
	54	GCC_ASM_EXPORT(ExceptionHandlersEnd)\r
	55	GCC_ASM_EXPORT(CommonExceptionEntry)\r
	56	GCC_ASM_EXPORT(AsmCommonExceptionEntry)\r
	57	GCC_ASM_EXPORT(GdbExceptionHandler)\r
	58	\r
	59	.text\r
	60	.align 3\r
	61	\r
	62	\r
	63	//\r
	64	// This code gets copied to the ARM vector table\r
65	// ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r
66	//\r
67	ASM_PFX(ExceptionHandlersStart):\r
68	\r
69	ASM_PFX(Reset):\r
70	b ASM_PFX(Reset)\r
71	\r
72	ASM_PFX(UndefinedInstruction):\r
73	b ASM_PFX(UndefinedInstructionEntry)\r
74	\r
75	ASM_PFX(SoftwareInterrupt):\r
76	b ASM_PFX(SoftwareInterruptEntry)\r
77	\r
78	ASM_PFX(PrefetchAbort):\r
79	b ASM_PFX(PrefetchAbortEntry)\r
80	\r
81	ASM_PFX(DataAbort):\r
82	b ASM_PFX(DataAbortEntry)\r
83	\r
84	ASM_PFX(ReservedException):\r
85	b ASM_PFX(ReservedExceptionEntry)\r
86	\r
87	ASM_PFX(Irq):\r
88	b ASM_PFX(Irq)\r
89	\r
90	ASM_PFX(Fiq):\r
91	b ASM_PFX(FiqEntry)\r
92	\r
93	\r
94	ASM_PFX(UndefinedInstructionEntry):\r
95	sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry\r
96	srsdb #0x13! @ Store return state on SVC stack\r
97	cpsid f,#0x13 @ Switch to SVC for common stack\r
98	stmfd SP!,{LR} @ Store the link register for the current mode\r
99	sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
100	stmfd SP!,{R0-R12} @ Store the register state\r
101	\r
102	mov R0,#1 @ ExceptionType\r
103	ldr R1,ASM_PFX(CommonExceptionEntry)\r
104	bx R1\r
105	\r
106	ASM_PFX(SoftwareInterruptEntry):\r
107	sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry\r
108	srsdb #0x13! @ Store return state on SVC stack\r
109	cpsid f @ We are already in SVC mode\r
110	stmfd SP!,{LR} @ Store the link register for the current mode\r
111	sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
112	stmfd SP!,{R0-R12} @ Store the register state\r
113	\r
114	mov R0,#2 @ ExceptionType\r
115	ldr R1,ASM_PFX(CommonExceptionEntry)\r
116	bx R1\r
117	\r
118	ASM_PFX(PrefetchAbortEntry):\r
119	sub LR,LR,#4\r
120	srsdb #0x13! @ Store return state on SVC stack\r
121	cpsid f,#0x13 @ Switch to SVC for common stack\r
122	stmfd SP!,{LR} @ Store the link register for the current mode\r
123	sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
124	stmfd SP!,{R0-R12} @ Store the register state\r
125	\r
126	mov R0,#3 @ ExceptionType\r
127	ldr R1,ASM_PFX(CommonExceptionEntry)\r
128	bx R1\r
129	\r
130	ASM_PFX(DataAbortEntry):\r
131	sub LR,LR,#8\r
132	srsdb #0x13! @ Store return state on SVC stack\r
133	cpsid f,#0x13 @ Switch to SVC for common stack\r
134	stmfd SP!,{LR} @ Store the link register for the current mode\r
135	sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
136	stmfd SP!,{R0-R12} @ Store the register state\r
137	\r
138	mov R0,#4\r
139	ldr R1,ASM_PFX(CommonExceptionEntry)\r
140	bx R1\r
141	\r
142	ASM_PFX(ReservedExceptionEntry):\r
143	srsdb #0x13! @ Store return state on SVC stack\r
144	cpsid f,#0x13 @ Switch to SVC for common stack\r
145	stmfd SP!,{LR} @ Store the link register for the current mode\r
146	sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
147	stmfd SP!,{R0-R12} @ Store the register state\r
148	\r
149	mov R0,#5\r
150	ldr R1,ASM_PFX(CommonExceptionEntry)\r
151	bx R1\r
152	\r
153	ASM_PFX(FiqEntry):\r
154	sub LR,LR,#4\r
155	srsdb #0x13! @ Store return state on SVC stack\r
156	cps #0x13 @ Switch to SVC for common stack\r
157	stmfd SP!,{LR} @ Store the link register for the current mode\r
158	sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
159	stmfd SP!,{R0-R12} @ Store the register state\r
160	@ Since we have already switch to SVC R8_fiq - R12_fiq\r
161	@ never get used or saved\r
162	mov R0,#7 @ ExceptionType\r
163	ldr R1,ASM_PFX(CommonExceptionEntry)\r
164	bx R1\r
165	\r
166	//\r
167	// This gets patched by the C code that patches in the vector table\r
168	//\r
169	ASM_PFX(CommonExceptionEntry):\r
170	.byte 0x12\r
171	.byte 0x34\r
172	.byte 0x56\r
173	.byte 0x78\r
174	\r
175	ASM_PFX(ExceptionHandlersEnd):\r
176	\r
177	//\r
178	// This code runs from CpuDxe driver loaded address. It is patched into \r
179	// CommonExceptionEntry.\r
180	//\r
181	ASM_PFX(AsmCommonExceptionEntry):\r
182	mrc p15, 0, R1, c6, c0, 2 @ Read IFAR\r
183	str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
184	\r
185	mrc p15, 0, R1, c5, c0, 1 @ Read IFSR\r
186	str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
187	\r
188	mrc p15, 0, R1, c6, c0, 0 @ Read DFAR\r
189	str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
190	\r
191	mrc p15, 0, R1, c5, c0, 0 @ Read DFSR\r
192	str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
193	\r
194	ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack \r
195	str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
196	\r
197	add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
198	and R3, R1, #0x1f @ Check CPSR to see if User or System Mode\r
199	cmp R3, #0x1f @ if ((CPSR == 0x10) \|\| (CPSR == 0x1df))\r
200	cmpne R3, #0x10 @ \r
201	stmeqed R2, {lr}^ @ save unbanked lr\r
202	@ else \r
203	stmneed R2, {lr} @ save SVC lr\r
204	\r
205	\r
206	ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd \r
207	@ Check to see if we have to adjust for Thumb entry\r
208	sub r4, r0, #1 @ if (ExceptionType == 1 \|\| ExceptionType ==2)) {\r
209	cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb \r
210	bhi NoAdjustNeeded\r
211	\r
212	tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry \r
213	addne R5, R5, #2 @ PC += 2@\r
214	str R5,[SP,#0x58] @ Update LR value pused by srsfd \r
215	\r
216	NoAdjustNeeded:\r
217	\r
218	str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
219	\r
220	sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack \r
221	str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
222	\r
223	@ R0 is ExceptionType \r
224	mov R1,SP @ R1 is SystemContext \r
225	\r
226	/* \r
227	VOID\r
228	EFIAPI\r
229	GdbExceptionHandler (\r
230	IN EFI_EXCEPTION_TYPE ExceptionType, R0\r
231	IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r
232	)\r
233	\r
234	*/ \r
235	blx ASM_PFX(GdbExceptionHandler) @ Call exception handler\r
236	\r
237	ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC\r
238	str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored \r
239	\r
240	ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR\r
241	str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored \r
242	\r
243	add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry\r
244	add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
245	and R1, R1, #0x1f @ Check to see if User or System Mode\r
246	cmp R1, #0x1f @ if ((CPSR == 0x10) \|\| (CPSR == 0x1f))\r
247	cmpne R1, #0x10 @ \r
248	ldmeqed R2, {lr}^ @ restore unbanked lr\r
249	@ else\r
250	ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}\r
251	\r
252	ldmfd SP!,{R0-R12} @ Restore general purpose registers\r
253	@ Exception handler can not change SP\r
254	\r
255	add SP,SP,#0x20 @ Clear out the remaining stack space\r
256	ldmfd SP!,{LR} @ restore the link register for this context\r
257	rfefd SP! @ return from exception via srsfd stack slot\r
258	\r