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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r | |
4 | \r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <CpuDxe.h>\r | |
16 | #include <Library/CacheMaintenanceLib.h>\r | |
17 | \r | |
18 | VOID\r | |
19 | ExceptionHandlersStart (\r | |
20 | VOID\r | |
21 | );\r | |
22 | \r | |
23 | VOID\r | |
24 | ExceptionHandlersEnd (\r | |
25 | VOID\r | |
26 | );\r | |
27 | \r | |
28 | VOID\r | |
29 | CommonExceptionEntry (\r | |
30 | VOID\r | |
31 | );\r | |
32 | \r | |
33 | VOID\r | |
34 | AsmCommonExceptionEntry (\r | |
35 | VOID\r | |
36 | );\r | |
37 | \r | |
38 | \r | |
39 | EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1];\r | |
40 | \r | |
41 | \r | |
42 | /**\r | |
43 | This function registers and enables the handler specified by InterruptHandler for a processor \r | |
44 | interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r | |
45 | handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r | |
46 | The installed handler is called once for each processor interrupt or exception.\r | |
47 | \r | |
48 | @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r | |
49 | are enabled and FALSE if interrupts are disabled.\r | |
50 | @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r | |
51 | when a processor interrupt occurs. If this parameter is NULL, then the handler\r | |
52 | will be uninstalled.\r | |
53 | \r | |
54 | @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.\r | |
55 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was\r | |
56 | previously installed.\r | |
57 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r | |
58 | previously installed.\r | |
59 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.\r | |
60 | \r | |
61 | **/\r | |
62 | EFI_STATUS\r | |
63 | RegisterInterruptHandler (\r | |
64 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
65 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
66 | )\r | |
67 | {\r | |
68 | if (InterruptType > MAX_ARM_EXCEPTION) {\r | |
69 | return EFI_UNSUPPORTED;\r | |
70 | }\r | |
71 | \r | |
72 | if ((InterruptHandler == NULL) && (gExceptionHandlers[InterruptType] == NULL)) {\r | |
73 | return EFI_INVALID_PARAMETER;\r | |
74 | }\r | |
75 | \r | |
76 | if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) {\r | |
77 | return EFI_ALREADY_STARTED;\r | |
78 | }\r | |
79 | \r | |
80 | gExceptionHandlers[InterruptType] = InterruptHandler;\r | |
81 | \r | |
82 | return EFI_SUCCESS;\r | |
83 | }\r | |
84 | \r | |
85 | \r | |
86 | \r | |
87 | \r | |
88 | VOID\r | |
89 | EFIAPI\r | |
90 | DefaultSWIExceptionHandler(\r | |
91 | IN EFI_EXCEPTION_TYPE ExceptionType,\r | |
92 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r | |
93 | )\r | |
94 | {\r | |
95 | return;\r | |
96 | }\r | |
97 | \r | |
98 | \r | |
99 | VOID\r | |
100 | EFIAPI\r | |
101 | DefaultExceptionHandler(\r | |
102 | IN EFI_EXCEPTION_TYPE ExceptionType,\r | |
103 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r | |
104 | )\r | |
105 | {\r | |
106 | DEBUG ((EFI_D_ERROR, "Exception %d from %x\n", ExceptionType, SystemContext.SystemContextArm->PC));\r | |
107 | ASSERT (FALSE);\r | |
108 | \r | |
109 | return;\r | |
110 | }\r | |
111 | \r | |
112 | \r | |
113 | \r | |
114 | EFI_STATUS\r | |
115 | InitializeExceptions (\r | |
116 | IN EFI_CPU_ARCH_PROTOCOL *Cpu\r | |
117 | )\r | |
118 | {\r | |
119 | EFI_STATUS Status = EFI_SUCCESS;\r | |
120 | UINTN Offset;\r | |
121 | UINTN Length;\r | |
122 | UINTN Index;\r | |
123 | BOOLEAN Enabled;\r | |
124 | \r | |
125 | //\r | |
126 | // Disable interrupts\r | |
127 | //\r | |
128 | Cpu->GetInterruptState (Cpu, &Enabled);\r | |
129 | Cpu->DisableInterrupt (Cpu);\r | |
130 | \r | |
131 | //\r | |
132 | // Initialize the C entry points for interrupts\r | |
133 | //\r | |
134 | for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {\r | |
135 | if (Index == EXCEPT_ARM_SOFTWARE_INTERRUPT) {\r | |
136 | Status = Cpu->RegisterInterruptHandler (Cpu, Index, DefaultSWIExceptionHandler);\r | |
137 | } else {\r | |
138 | Status = Cpu->RegisterInterruptHandler (Cpu, Index, DefaultExceptionHandler);\r | |
139 | }\r | |
140 | ASSERT_EFI_ERROR (Status);\r | |
141 | }\r | |
142 | \r | |
143 | //\r | |
144 | // Copy an implementation of the ARM exception vectors to 0x0.\r | |
145 | //\r | |
146 | Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;\r | |
147 | \r | |
148 | CopyMem ((VOID *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress), (VOID *)ExceptionHandlersStart, Length);\r | |
149 | \r | |
150 | //\r | |
151 | // Patch in the common Assembly exception handler\r | |
152 | //\r | |
153 | Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;\r | |
154 | *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;\r | |
155 | \r | |
156 | //\r | |
157 | // Flush Caches since we updated executable stuff\r | |
158 | //\r | |
159 | InvalidateInstructionCache ();\r | |
160 | \r | |
161 | if (Enabled) {\r | |
162 | // \r | |
163 | // Restore interrupt state\r | |
164 | //\r | |
165 | Status = Cpu->EnableInterrupt (Cpu);\r | |
166 | }\r | |
167 | \r | |
168 | return Status;\r | |
169 | }\r | |
170 | \r | |
171 | \r | |
172 | \r | |
173 | /**\r | |
174 | This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r | |
175 | \r | |
176 | @param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter\r | |
177 | must be between 0 and NumberOfTimers-1.\r | |
178 | @param TimerValue Pointer to the returned timer value.\r | |
179 | @param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment\r | |
180 | of TimerValue.\r | |
181 | \r | |
182 | @retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.\r | |
183 | @retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.\r | |
184 | @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r | |
185 | @retval EFI_UNSUPPORTED The processor does not have any readable timers.\r | |
186 | \r | |
187 | **/\r | |
188 | EFI_STATUS\r | |
189 | EFIAPI\r | |
190 | GetTimerValue (\r | |
191 | IN UINT32 TimerIndex,\r | |
192 | OUT UINT64 *TimerValue,\r | |
193 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
194 | )\r | |
195 | {\r | |
196 | return EFI_UNSUPPORTED;\r | |
197 | }\r | |
198 | \r | |
199 | \r | |
200 | /**\r | |
201 | This function flushes the range of addresses from Start to Start+Length \r | |
202 | from the processor's data cache. If Start is not aligned to a cache line \r | |
203 | boundary, then the bytes before Start to the preceding cache line boundary \r | |
204 | are also flushed. If Start+Length is not aligned to a cache line boundary, \r | |
205 | then the bytes past Start+Length to the end of the next cache line boundary \r | |
206 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r | |
207 | supported. If the data cache is fully coherent with all DMA operations, then \r | |
208 | this function can just return EFI_SUCCESS. If the processor does not support \r | |
209 | flushing a range of the data cache, then the entire data cache can be flushed.\r | |
210 | \r | |
211 | @param Start The beginning physical address to flush from the processor's data\r | |
212 | cache.\r | |
213 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
214 | function may flush more bytes than Length specifies depending upon\r | |
215 | the granularity of the flush operation that the processor supports.\r | |
216 | @param FlushType Specifies the type of flush operation to perform.\r | |
217 | \r | |
218 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
219 | the processor's data cache.\r | |
220 | @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r | |
221 | by FlushType.\r | |
222 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
223 | from the processor's data cache.\r | |
224 | \r | |
225 | **/\r | |
226 | EFI_STATUS\r | |
227 | EFIAPI\r | |
228 | FlushCpuDataCache (\r | |
229 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
230 | IN UINT64 Length,\r | |
231 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
232 | )\r | |
233 | {\r | |
234 | if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r | |
235 | WriteBackInvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);\r | |
236 | return EFI_SUCCESS;\r | |
237 | } else if (FlushType == EfiCpuFlushTypeInvalidate) {\r | |
238 | InvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);\r | |
239 | return EFI_SUCCESS;\r | |
240 | } else if (FlushType == EfiCpuFlushTypeWriteBack) {\r | |
241 | WriteBackDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);\r | |
242 | return EFI_SUCCESS;\r | |
243 | } else {\r | |
244 | return EFI_UNSUPPORTED;\r | |
245 | }\r | |
246 | }\r | |
247 | \r | |
248 | \r | |
249 | \r | |
250 | \r |