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1 | //------------------------------------------------------------------------------ |
2 | // | |
3 | // Copyright (c) 2008-2009 Apple Inc. All rights reserved. | |
4 | // | |
5 | // All rights reserved. This program and the accompanying materials | |
6 | // are licensed and made available under the terms and conditions of the BSD License | |
7 | // which accompanies this distribution. The full text of the license may be found at | |
8 | // http://opensource.org/licenses/bsd-license.php | |
9 | // | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | // | |
13 | //------------------------------------------------------------------------------ | |
14 | ||
15 | EXPORT ExceptionHandlersStart | |
16 | EXPORT ExceptionHandlersEnd | |
17 | EXPORT CommonExceptionEntry | |
18 | EXPORT AsmCommonExceptionEntry | |
19 | IMPORT gExceptionHandlers | |
20 | ||
21 | AREA DxeExceptionHandlers, CODE, READONLY | |
22 | ||
23 | ExceptionHandlersStart | |
24 | ||
25 | Reset | |
26 | B ResetEntry | |
27 | ||
28 | UndefinedInstruction | |
29 | B UndefinedInstructionEntry | |
30 | ||
31 | SoftwareInterrupt | |
32 | B SoftwareInterruptEntry | |
33 | ||
34 | PrefetchAbort | |
35 | B PrefetchAbortEntry | |
36 | ||
37 | DataAbort | |
38 | B DataAbortEntry | |
39 | ||
40 | ReservedException | |
41 | B ReservedExceptionEntry | |
42 | ||
43 | Irq | |
44 | B IrqEntry | |
45 | ||
46 | Fiq | |
47 | B FiqEntry | |
48 | ||
49 | ResetEntry | |
50 | STMFD SP!,{R0-R1} | |
51 | MOV R0,#0 | |
52 | LDR R1,CommonExceptionEntry | |
53 | BX R1 | |
54 | ||
55 | UndefinedInstructionEntry | |
56 | STMFD SP!,{R0-R1} | |
57 | MOV R0,#1 | |
58 | LDR R1,CommonExceptionEntry | |
59 | BX R1 | |
60 | ||
61 | SoftwareInterruptEntry | |
62 | STMFD SP!,{R0-R1} | |
63 | MOV R0,#2 | |
64 | LDR R1,CommonExceptionEntry | |
65 | BX R1 | |
66 | ||
67 | PrefetchAbortEntry | |
68 | STMFD SP!,{R0-R1} | |
69 | MOV R0,#3 | |
70 | SUB LR,LR,#4 | |
71 | LDR R1,CommonExceptionEntry | |
72 | BX R1 | |
73 | ||
74 | DataAbortEntry | |
75 | STMFD SP!,{R0-R1} | |
76 | MOV R0,#4 | |
77 | SUB LR,LR,#8 | |
78 | LDR R1,CommonExceptionEntry | |
79 | BX R1 | |
80 | ||
81 | ReservedExceptionEntry | |
82 | STMFD SP!,{R0-R1} | |
83 | MOV R0,#5 | |
84 | LDR R1,CommonExceptionEntry | |
85 | BX R1 | |
86 | ||
87 | IrqEntry | |
88 | STMFD SP!,{R0-R1} | |
89 | MOV R0,#6 | |
90 | SUB LR,LR,#4 | |
91 | LDR R1,CommonExceptionEntry | |
92 | BX R1 | |
93 | ||
94 | FiqEntry | |
95 | STMFD SP!,{R0-R1} | |
96 | MOV R0,#7 | |
97 | SUB LR,LR,#4 | |
98 | LDR R1,CommonExceptionEntry | |
99 | BX R1 | |
100 | ||
101 | CommonExceptionEntry | |
102 | DCD 0x12345678 | |
103 | ||
104 | ExceptionHandlersEnd | |
105 | ||
106 | AsmCommonExceptionEntry | |
107 | MRC p15, 0, r1, c6, c0, 2 ; Read IFAR | |
108 | STMFD SP!,{R1} ; Store the IFAR | |
109 | ||
110 | MRC p15, 0, r1, c5, c0, 1 ; Read IFSR | |
111 | STMFD SP!,{R1} ; Store the IFSR | |
112 | ||
113 | MRC p15, 0, r1, c6, c0, 0 ; Read DFAR | |
114 | STMFD SP!,{R1} ; Store the DFAR | |
115 | ||
116 | MRC p15, 0, r1, c5, c0, 0 ; Read DFSR | |
117 | STMFD SP!,{R1} ; Store the DFSR | |
118 | ||
119 | MRS R1,SPSR ; Read SPSR (which is the pre-exception CPSR) | |
120 | STMFD SP!,{R1} ; Store the SPSR | |
121 | ||
122 | STMFD SP!,{LR} ; Store the link register (which is the pre-exception PC) | |
123 | STMFD SP,{SP,LR}^ ; Store user/system mode stack pointer and link register | |
124 | NOP ; Required by ARM architecture | |
125 | SUB SP,SP,#0x08 ; Adjust stack pointer | |
126 | STMFD SP!,{R2-R12} ; Store general purpose registers | |
127 | ||
128 | LDR R3,[SP,#0x40] ; Read saved R1 from the stack (it was saved by the exception entry routine) | |
129 | LDR R2,[SP,#0x3C] ; Read saved R0 from the stack (it was saved by the exception entry routine) | |
130 | STMFD SP!,{R2-R3} ; Store general purpose registers R0 and R1 | |
131 | ||
132 | MOV R1,SP ; Prepare System Context pointer as an argument for the exception handler | |
133 | ||
134 | LDR R2,=gExceptionHandlers ; Load exception handler table | |
135 | LDR R3,[R2,R0,LSL #2] ; Index to find the handler for this exception | |
136 | ||
137 | BLX R3 ; Call exception handler | |
138 | ||
139 | LDR R2,[SP,#0x40] ; Load CPSR from context, in case it has changed | |
140 | MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler | |
141 | ||
142 | LDMFD SP!,{R0-R12} ; Restore general purpose registers | |
143 | LDM SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register | |
144 | NOP ; Required by ARM architecture | |
145 | ADD SP,SP,#0x08 ; Adjust stack pointer | |
146 | LDMFD SP!,{LR} ; Restore the link register (which is the pre-exception PC) | |
147 | ADD SP,SP,#0x1C ; Clear out the remaining stack space | |
148 | MOVS PC,LR ; Return from exception | |
149 | ||
150 | END | |
151 | ||
152 |