EmbeddedPkg/MmcDxe: set I/O speed and bus width in SD stack
[mirror_edk2.git] / EmbeddedPkg / Universal / MmcDxe / Mmc.h
CommitLineData
1bfda055 1/** @file\r
2 Main Header file for the MMC DXE driver\r
3\r
eff98cf9 4 Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
1bfda055 5\r
3402aac7
RC
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
1bfda055 13\r
14**/\r
15\r
16#ifndef __MMC_H\r
17#define __MMC_H\r
18\r
a1ab9143 19#include <Uefi.h>\r
20\r
1bfda055 21#include <Protocol/DiskIo.h>\r
22#include <Protocol/BlockIo.h>\r
23#include <Protocol/DevicePath.h>\r
24#include <Protocol/MmcHost.h>\r
25\r
26#include <Library/UefiLib.h>\r
4ca3c688 27#include <Library/DebugLib.h>\r
eff98cf9 28#include <Library/UefiBootServicesTableLib.h>\r
1bfda055 29\r
30#define MMC_TRACE(txt) DEBUG((EFI_D_BLKIO, "MMC: " txt "\n"))\r
31\r
32#define MMC_IOBLOCKS_READ 0\r
33#define MMC_IOBLOCKS_WRITE 1\r
34\r
35#define MMC_OCR_POWERUP 0x80000000\r
36\r
bb0f9e9b 37#define MMC_CSD_GET_CCC(Response) (Response[2] >> 20)\r
38#define MMC_CSD_GET_TRANSPEED(Response) (Response[3] & 0xFF)\r
39#define MMC_CSD_GET_READBLLEN(Response) ((Response[2] >> 16) & 0xF)\r
40#define MMC_CSD_GET_WRITEBLLEN(Response) ((Response[0] >> 22) & 0xF)\r
41#define MMC_CSD_GET_FILEFORMAT(Response) ((Response[0] >> 10) & 0x3)\r
42#define MMC_CSD_GET_FILEFORMATGRP(Response) ((Response[0] >> 15) & 0x1)\r
43#define MMC_CSD_GET_DEVICESIZE(csd) (((Response[1] >> 30) & 0x3) | ((Response[2] & 0x3FF) << 2))\r
36aa5611 44#define HC_MMC_CSD_GET_DEVICESIZE(Response) ((Response[1] >> 16) | ((Response[2] & 0x40) << 16));\r
bb0f9e9b 45#define MMC_CSD_GET_DEVICESIZEMULT(csd) ((Response[1] >> 15) & 0x7)\r
1bfda055 46\r
b9d5fe03 47#define MMC_R0_READY_FOR_DATA (1 << 8)\r
48\r
1bfda055 49#define MMC_R0_CURRENTSTATE(Response) ((Response[0] >> 9) & 0xF)\r
50\r
51#define MMC_R0_STATE_IDLE 0\r
52#define MMC_R0_STATE_READY 1\r
53#define MMC_R0_STATE_IDENT 2\r
54#define MMC_R0_STATE_STDBY 3\r
55#define MMC_R0_STATE_TRAN 4\r
56#define MMC_R0_STATE_DATA 5\r
57\r
752ae805
HZ
58#define EMMC_CMD6_ARG_ACCESS(x) (((x) & 0x3) << 24)\r
59#define EMMC_CMD6_ARG_INDEX(x) (((x) & 0xFF) << 16)\r
60#define EMMC_CMD6_ARG_VALUE(x) (((x) & 0xFF) << 8)\r
61#define EMMC_CMD6_ARG_CMD_SET(x) (((x) & 0x7) << 0)\r
62\r
1bfda055 63typedef enum {\r
64 UNKNOWN_CARD,\r
65 MMC_CARD, //MMC card\r
66 MMC_CARD_HIGH, //MMC Card with High capacity\r
b4fdedc2 67 EMMC_CARD, //eMMC 4.41 card\r
1bfda055 68 SD_CARD, //SD 1.1 card\r
69 SD_CARD_2, //SD 2.0 or above standard card\r
70 SD_CARD_2_HIGH //SD 2.0 or above high capacity card\r
71} CARD_TYPE;\r
72\r
73typedef struct {\r
3402aac7 74 UINT32 Reserved0: 7; // 0\r
1bfda055 75 UINT32 V170_V195: 1; // 1.70V - 1.95V\r
76 UINT32 V200_V260: 7; // 2.00V - 2.60V\r
77 UINT32 V270_V360: 9; // 2.70V - 3.60V\r
78 UINT32 RESERVED_1: 5; // Reserved\r
3402aac7 79 UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)\r
492e34a5 80 UINT32 PowerUp: 1; // This bit is set to LOW if the card has not finished the power up routine\r
1bfda055 81} OCR;\r
82\r
e06253ba
HZ
83typedef struct {\r
84 UINT8 SD_SPEC: 4; // SD Memory Card - Spec. Version [59:56]\r
85 UINT8 SCR_STRUCTURE: 4; // SCR Structure [63:60]\r
86 UINT8 SD_BUS_WIDTHS: 4; // DAT Bus widths supported [51:48]\r
87 UINT8 DATA_STAT_AFTER_ERASE: 1; // Data Status after erases [55]\r
88 UINT8 SD_SECURITY: 3; // CPRM Security Support [54:52]\r
89 UINT8 EX_SECURITY_1: 1; // Extended Security Support [43]\r
90 UINT8 SD_SPEC4: 1; // Spec. Version 4.00 or higher [42]\r
91 UINT8 RESERVED_1: 2; // Reserved [41:40]\r
92 UINT8 SD_SPEC3: 1; // Spec. Version 3.00 or higher [47]\r
93 UINT8 EX_SECURITY_2: 3; // Extended Security Support [46:44]\r
94 UINT8 CMD_SUPPORT: 4; // Command Support bits [35:32]\r
95 UINT8 RESERVED_2: 4; // Reserved [39:36]\r
96 UINT32 RESERVED_3; // Manufacturer Usage [31:0]\r
97} SCR;\r
98\r
1bfda055 99typedef struct {\r
100 UINT32 NOT_USED; // 1 [0:0]\r
101 UINT32 CRC; // CRC7 checksum [7:1]\r
102 UINT32 MDT; // Manufacturing date [19:8]\r
103 UINT32 RESERVED_1; // Reserved [23:20]\r
104 UINT32 PSN; // Product serial number [55:24]\r
105 UINT8 PRV; // Product revision [63:56]\r
106 UINT8 PNM[5]; // Product name [64:103]\r
107 UINT16 OID; // OEM/Application ID [119:104]\r
108 UINT8 MID; // Manufacturer ID [127:120]\r
109} CID;\r
110\r
111typedef struct {\r
112 UINT8 NOT_USED: 1; // Not used, always 1 [0:0]\r
113 UINT8 CRC: 7; // CRC [7:1]\r
114\r
115 UINT8 RESERVED_1: 2; // Reserved [9:8]\r
116 UINT8 FILE_FORMAT: 2; // File format [11:10]\r
117 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r
118 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r
119 UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r
120 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r
3402aac7 121\r
1bfda055 122 UINT16 RESERVED_2: 5; // Reserved [20:16]\r
123 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r
124 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r
125 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r
126 UINT16 RESERVED_3: 2; // Reserved [30:29]\r
127 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r
3402aac7 128\r
1bfda055 129 UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]\r
130 UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]\r
131 UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]\r
132 UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]\r
133 UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]\r
134 UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]\r
135 UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]\r
136 UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]\r
137 UINT32 C_SIZELow2: 2; // Device size [63:62]\r
3402aac7 138\r
1bfda055 139 UINT32 C_SIZEHigh10: 10;// Device size [73:64]\r
140 UINT32 RESERVED_4: 2; // Reserved [75:74]\r
141 UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r
142 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r
143 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r
144 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r
145 UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]\r
146 UINT32 CCC: 12;// Card command classes [95:84]\r
147\r
148 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r
149 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
150 UINT8 TAAC ; // Data read access-time 1 [119:112]\r
3402aac7 151\r
653bde54
HZ
152 UINT8 RESERVED_5: 2; // Reserved [121:120]\r
153 UINT8 SPEC_VERS: 4; // System specification version [125:122]\r
1bfda055 154 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r
155} CSD;\r
156\r
e88fcb47
HZ
157typedef struct {\r
158 UINT8 RESERVED_1[16]; // Reserved [15:0]\r
159 UINT8 SECURE_REMOVAL_TYPE; // Secure Removal Type [16:16]\r
160 UINT8 PRODUCT_STATE_AWARENESS_ENABLEMENT; // Product state awareness enablement [17:17]\r
161 UINT8 MAX_PRE_LOADING_DATA_SIZE[4]; // MAX pre loading data size [21:18]\r
162 UINT8 PRE_LOADING_DATA_SIZE[4]; // Pre loading data size [25:22]\r
163 UINT8 FFU_STATUS; // FFU Status [26:26]\r
164 UINT8 RESERVED_2[2]; // Reserved [28:27]\r
165 UINT8 MODE_OPERATION_CODES; // Mode operation codes [29:29]\r
166 UINT8 MODE_CONFIG; // Mode config [30:30]\r
167 UINT8 RESERVED_3; // Reserved [31:31]\r
168 UINT8 FLUSH_CACHE; // Flushing of the cache [32:32]\r
169 UINT8 CACHE_CTRL; // Control to turn the cache ON/OFF [33:33]\r
170 UINT8 POWER_OFF_NOTIFICATION; // Power Off Notification [34:34]\r
171 UINT8 PACKED_FAILURE_INDEX; // Packed command failure index [35:35]\r
172 UINT8 PACKED_COMMAND_STATUS; // Packed command status [36:36]\r
173 UINT8 CONTEXT_CONF[15]; // Context configuration [51:37]\r
174 UINT8 EXT_PARTITIONS_ATTRIBUTE[2]; // Extended partitions attribute [53:52]\r
175 UINT8 EXCEPTION_EVENTS_STATUS[2]; // Exception events status [55:54]\r
176 UINT8 EXCEPTION_EVENTS_CTRL[2]; // Exception events control [57:56]\r
177 UINT8 DYNCAP_NEEDED; // Number of addressed group to be released [58:58]\r
178 UINT8 CLASS_6_CTRL; // Class 6 commands control [59:59]\r
179 UINT8 INI_TIMEOUT_EMU; // 1st initialization after disabling sector size emulation [60:60]\r
180 UINT8 DATA_SECTOR_SIZE; // Sector size [61:61]\r
181 UINT8 USE_NATIVE_SECTOR; // Sector size emulation [62:62]\r
182 UINT8 NATIVE_SECTOR_SIZE; // Native sector size [63:63]\r
183 UINT8 VENDOR_SPECIFIC_FIELD[64]; // Vendor specific fields [127:64]\r
184 UINT8 RESERVED_4[2]; // Reserved [129:128]\r
185 UINT8 PROGRAM_CID_CSD_DDR_SUPPORT; // Program CID/CSD in DDR mode support [130:130]\r
186 UINT8 PERIODIC_WAKEUP; // Periodic wake-up [131:131]\r
187 UINT8 TCASE_SUPPORT; // Package case temperature is controlled [132:132]\r
188 UINT8 PRODUCTION_STATE_AWARENESS; // Production state awareness [133:133]\r
189 UINT8 SECTOR_BAD_BLK_MGMNT; // Bad block management mode [134:134]\r
190 UINT8 RESERVED_5; // Reserved [135:135]\r
191 UINT8 ENH_START_ADDR[4]; // Enhanced user data start address [139:136]\r
192 UINT8 ENH_SIZE_MULT[3]; // Enhanced user data area size [142:140]\r
193 UINT8 GP_SIZE_MULT[12]; // General purpose partition size [154:143]\r
194 UINT8 PARTITION_SETTING_COMPLETED; // Partitioning setting [155:155]\r
195 UINT8 PARTITIONS_ATTRIBUTE; // Partitions attribute [156:156]\r
196 UINT8 MAX_ENH_SIZE_MULT[3]; // Max enhanced area size [159:157]\r
197 UINT8 PARTITIONING_SUPPORT; // Partitioning [160:160]\r
198 UINT8 HPI_MGMT; // HPI management [161:161]\r
199 UINT8 RST_N_FUNCTION; // H/W reset function [162:162]\r
200 UINT8 BKOPS_EN; // Enable background operations handshake [163:163]\r
201 UINT8 BKOPS_START; // Manually start background operations [164:164]\r
202 UINT8 SANITIZE_START; // Start sanitize operation [165:165]\r
203 UINT8 WR_REL_PARAM; // Write reliability parameter register [166:166]\r
204 UINT8 WR_REL_SET; // Write reliability setting register [167:167]\r
205 UINT8 RPMB_SIZE_MULT; // RPMB size [168:168]\r
206 UINT8 FW_CONFIG; // FW configuration [169:169]\r
207 UINT8 RESERVED_6; // Reserved [170:170]\r
208 UINT8 USER_WP; // User area write protection register [171:171]\r
209 UINT8 RESERVED_7; // Reserved [172:172]\r
210 UINT8 BOOT_WP; // Boot area write protection register [173:173]\r
211 UINT8 BOOT_WP_STATUS; // Boot write protection register [174:174]\r
212 UINT8 ERASE_GROUP_DEF; // High-density erase group definition [175:175]\r
213 UINT8 RESERVED_8; // Reserved [176:176]\r
214 UINT8 BOOT_BUS_CONDITIONS; // Boot bus conditions [177:177]\r
215 UINT8 BOOT_CONFIG_PROT; // Boot config protection [178:178]\r
216 UINT8 PARTITION_CONFIG; // Partition config [179:179]\r
217 UINT8 RESERVED_9; // Reserved [180:180]\r
218 UINT8 ERASED_MEM_CONT; // Erased memory content [181:181]\r
219 UINT8 RESERVED_10; // Reserved [182:182]\r
220 UINT8 BUS_WIDTH; // Bus width mode [183:183]\r
221 UINT8 RESERVED_11; // Reserved [184:184]\r
222 UINT8 HS_TIMING; // High-speed interface timing [185:185]\r
223 UINT8 RESERVED_12; // Reserved [186:186]\r
224 UINT8 POWER_CLASS; // Power class [187:187]\r
225 UINT8 RESERVED_13; // Reserved [188:188]\r
226 UINT8 CMD_SET_REV; // Command set revision [189:189]\r
227 UINT8 RESERVED_14; // Reserved [190:190]\r
228 UINT8 CMD_SET; // Command set [191:191]\r
229 UINT8 EXT_CSD_REV; // Extended CSD revision [192:192]\r
230 UINT8 RESERVED_15; // Reserved [193:193]\r
231 UINT8 CSD_STRUCTURE; // CSD Structure [194:194]\r
232 UINT8 RESERVED_16; // Reserved [195:195]\r
233 UINT8 DEVICE_TYPE; // Device type [196:196]\r
234 UINT8 DRIVER_STRENGTH; // I/O Driver strength [197:197]\r
235 UINT8 OUT_OF_INTERRUPT_TIME; // Out-of-interrupt busy timing [198:198]\r
236 UINT8 PARTITION_SWITCH_TIME; // Partition switching timing [199:199]\r
237 UINT8 PWR_CL_52_195; // Power class for 52MHz at 1.95V 1 R [200:200]\r
238 UINT8 PWR_CL_26_195; // Power class for 26MHz at 1.95V 1 R [201:201]\r
239 UINT8 PWR_CL_52_360; // Power class for 52MHz at 3.6V 1 R [202:202]\r
240 UINT8 PWR_CL_26_360; // Power class for 26MHz at 3.6V 1 R [203:203]\r
241 UINT8 RESERVED_17; // Reserved [204:204]\r
242 UINT8 MIN_PERF_R_4_26; // Minimum read performance for 4bit at 26MHz [205:205]\r
243 UINT8 MIN_PERF_W_4_26; // Minimum write performance for 4bit at 26MHz [206:206]\r
244 UINT8 MIN_PERF_R_8_26_4_52; // Minimum read performance for 8bit at 26MHz, for 4bit at 52MHz [207:207]\r
245 UINT8 MIN_PERF_W_8_26_4_52; // Minimum write performance for 8bit at 26MHz, for 4bit at 52MHz [208:208]\r
246 UINT8 MIN_PERF_R_8_52; // Minimum read performance for 8bit at 52MHz [209:209]\r
247 UINT8 MIN_PERF_W_8_52; // Minimum write performance for 8bit at 52MHz [210:210]\r
248 UINT8 RESERVED_18; // Reserved [211:211]\r
249 UINT32 SECTOR_COUNT; // Sector count [215:212]\r
250 UINT8 SLEEP_NOTIFICATION_TIME; // Sleep notification timout [216:216]\r
251 UINT8 S_A_TIMEOUT; // Sleep/awake timeout [217:217]\r
252 UINT8 PRODUCTION_STATE_AWARENESS_TIMEOUT; // Production state awareness timeout [218:218]\r
253 UINT8 S_C_VCCQ; // Sleep current (VCCQ) [219:219]\r
254 UINT8 S_C_VCC; // Sleep current (VCC) [220:220]\r
255 UINT8 HC_WP_GRP_SIZE; // High-capacity write protect group size [221:221]\r
256 UINT8 REL_WR_SECTOR_C; // Reliable write sector count [222:222]\r
257 UINT8 ERASE_TIMEOUT_MULT; // High-capacity erase timeout [223:223]\r
258 UINT8 HC_ERASE_GRP_SIZE; // High-capacity erase unit size [224:224]\r
259 UINT8 ACC_SIZE; // Access size [225:225]\r
260 UINT8 BOOT_SIZE_MULTI; // Boot partition size [226:226]\r
261 UINT8 RESERVED_19; // Reserved [227:227]\r
262 UINT8 BOOT_INFO; // Boot information [228:228]\r
263 UINT8 SECURE_TRIM_MULT; // Secure TRIM Multiplier [229:229]\r
264 UINT8 SECURE_ERASE_MULT; // Secure Erase Multiplier [230:230]\r
265 UINT8 SECURE_FEATURE_SUPPORT; // Secure Feature Support [231:231]\r
266 UINT8 TRIM_MULT; // TRIM Multiplier [232:232]\r
267 UINT8 RESERVED_20; // Reserved [233:233]\r
268 UINT8 MIN_PREF_DDR_R_8_52; // Minimum read performance for 8bit at 52MHz in DDR mode [234:234]\r
269 UINT8 MIN_PREF_DDR_W_8_52; // Minimum write performance for 8bit at 52MHz in DDR mode [235:235]\r
270 UINT8 PWR_CL_200_130; // Power class for 200MHz at VCCQ=1.3V, VCC=3.6V [236:236]\r
271 UINT8 PWR_CL_200_195; // Power class for 200MHz at VCCQ=1.95V, VCC=3.6V [237:237]\r
272 UINT8 PWR_CL_DDR_52_195; // Power class for 52MHz, DDR at 1.95V [238:238]\r
273 UINT8 PWR_CL_DDR_52_360; // Power class for 52Mhz, DDR at 3.6V [239:239]\r
274 UINT8 RESERVED_21; // Reserved [240:240]\r
275 UINT8 INI_TIMEOUT_AP; // 1st initialization time after partitioning [241:241]\r
276 UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // Number of correctly programmed sectors [245:242]\r
277 UINT8 BKOPS_STATUS; // Background operations status [246:246]\r
278 UINT8 POWER_OFF_LONG_TIME; // Power off notification (long) timeout [247:247]\r
279 UINT8 GENERIC_CMD6_TIME; // Generic CMD6 timeout [248:248]\r
280 UINT8 CACHE_SIZE[4]; // Cache size [252:249]\r
281 UINT8 PWR_CL_DDR_200_360; // Power class for 200MHz, DDR at VCC=3.6V [253:253]\r
282 UINT8 FIRMWARE_VERSION[8]; // Firmware version [261:254]\r
283 UINT8 DEVICE_VERSION[2]; // Device version [263:262]\r
284 UINT8 OPTIMAL_TRIM_UNIT_SIZE; // Optimal trim unit size [264:264]\r
285 UINT8 OPTIMAL_WRITE_SIZE; // Optimal write size [265:265]\r
286 UINT8 OPTIMAL_READ_SIZE; // Optimal read size [266:266]\r
287 UINT8 PRE_EOL_INFO; // Pre EOL information [267:267]\r
288 UINT8 DEVICE_LIFE_TIME_EST_TYP_A; // Device life time estimation type A [268:268]\r
289 UINT8 DEVICE_LIFE_TIME_EST_TYP_B; // Device life time estimation type B [269:269]\r
290 UINT8 VENDOR_PROPRIETARY_HEALTH_REPORT[32]; // Vendor proprietary health report [301:270]\r
291 UINT8 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED[4]; // Number of FW sectors correctly programmed [305:302]\r
292 UINT8 RESERVED_22[181]; // Reserved [486:306]\r
293 UINT8 FFU_ARG[4]; // FFU argument [490:487]\r
294 UINT8 OPERATION_CODE_TIMEOUT; // Operation codes timeout [491:491]\r
295 UINT8 FFU_FEATURES; // FFU features [492:492]\r
296 UINT8 SUPPORTED_MODES; // Supported modes [493:493]\r
297 UINT8 EXT_SUPPORT; // Extended partitions attribute support [494:494]\r
298 UINT8 LARGE_UNIT_SIZE_M1; // Large unit size [495:495]\r
299 UINT8 CONTEXT_CAPABILITIES; // Context management capabilities [496:496]\r
300 UINT8 TAG_RES_SIZE; // Tag resource size [497:497]\r
301 UINT8 TAG_UNIT_SIZE; // Tag unit size [498:498]\r
302 UINT8 DATA_TAG_SUPPORT; // Data tag support [499:499]\r
303 UINT8 MAX_PACKED_WRITES; // Max packed write commands [500:500]\r
304 UINT8 MAX_PACKED_READS; // Max packed read commands [501:501]\r
305 UINT8 BKOPS_SUPPORT; // Background operations support [502:502]\r
306 UINT8 HPI_FEATURES; // HPI features [503:503]\r
307 UINT8 S_CMD_SET; // Supported command sets [504:504]\r
308 UINT8 EXT_SECURITY_ERR; // Extended security commands error [505:505]\r
309 UINT8 RESERVED_23[6]; // Reserved [511:506]\r
310} ECSD;\r
311\r
1bfda055 312typedef struct {\r
313 UINT16 RCA;\r
314 CARD_TYPE CardType;\r
315 OCR OCRData;\r
316 CID CIDData;\r
317 CSD CSDData;\r
e88fcb47 318 ECSD ECSDData; // MMC V4 extended card specific\r
1bfda055 319} CARD_INFO;\r
320\r
321typedef struct _MMC_HOST_INSTANCE {\r
322 UINTN Signature;\r
323 LIST_ENTRY Link;\r
324 EFI_HANDLE MmcHandle;\r
325 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
326\r
327 MMC_STATE State;\r
328 EFI_BLOCK_IO_PROTOCOL BlockIo;\r
329 CARD_INFO CardInfo;\r
330 EFI_MMC_HOST_PROTOCOL *MmcHost;\r
3402aac7 331\r
3de99375 332 BOOLEAN Initialized;\r
1bfda055 333} MMC_HOST_INSTANCE;\r
334\r
335#define MMC_HOST_INSTANCE_SIGNATURE SIGNATURE_32('m', 'm', 'c', 'h')\r
336#define MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS(a) CR (a, MMC_HOST_INSTANCE, BlockIo, MMC_HOST_INSTANCE_SIGNATURE)\r
337#define MMC_HOST_INSTANCE_FROM_LINK(a) CR (a, MMC_HOST_INSTANCE, Link, MMC_HOST_INSTANCE_SIGNATURE)\r
338\r
339\r
340EFI_STATUS\r
341EFIAPI\r
342MmcGetDriverName (\r
343 IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
344 IN CHAR8 *Language,\r
345 OUT CHAR16 **DriverName\r
346 );\r
347\r
348EFI_STATUS\r
349EFIAPI\r
350MmcGetControllerName (\r
351 IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
352 IN EFI_HANDLE ControllerHandle,\r
353 IN EFI_HANDLE ChildHandle OPTIONAL,\r
354 IN CHAR8 *Language,\r
355 OUT CHAR16 **ControllerName\r
356 );\r
357\r
358extern EFI_COMPONENT_NAME_PROTOCOL gMmcComponentName;\r
359extern EFI_COMPONENT_NAME2_PROTOCOL gMmcComponentName2;\r
360\r
361extern EFI_DRIVER_DIAGNOSTICS2_PROTOCOL gMmcDriverDiagnostics2;\r
362\r
363extern LIST_ENTRY mMmcHostPool;\r
364\r
365/**\r
366 Reset the block device.\r
367\r
3402aac7 368 This function implements EFI_BLOCK_IO_PROTOCOL.Reset().\r
1bfda055 369 It resets the block device hardware.\r
370 ExtendedVerification is ignored in this implementation.\r
371\r
372 @param This Indicates a pointer to the calling context.\r
373 @param ExtendedVerification Indicates that the driver may perform a more exhaustive\r
374 verification operation of the device during reset.\r
375\r
376 @retval EFI_SUCCESS The block device was reset.\r
377 @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset.\r
378\r
379**/\r
380EFI_STATUS\r
381EFIAPI\r
382MmcReset (\r
383 IN EFI_BLOCK_IO_PROTOCOL *This,\r
384 IN BOOLEAN ExtendedVerification\r
385 );\r
386\r
387/**\r
388 Reads the requested number of blocks from the device.\r
389\r
3402aac7 390 This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks().\r
1bfda055 391 It reads the requested number of blocks from the device.\r
392 All the blocks are read, or an error is returned.\r
393\r
394 @param This Indicates a pointer to the calling context.\r
395 @param MediaId The media ID that the read request is for.\r
396 @param Lba The starting logical block address to read from on the device.\r
397 @param BufferSize The size of the Buffer in bytes.\r
398 This must be a multiple of the intrinsic block size of the device.\r
399 @param Buffer A pointer to the destination buffer for the data. The caller is\r
400 responsible for either having implicit or explicit ownership of the buffer.\r
401\r
402 @retval EFI_SUCCESS The data was read correctly from the device.\r
403 @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation.\r
404 @retval EFI_NO_MEDIA There is no media in the device.\r
405 @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.\r
406 @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the device.\r
407 @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,\r
408 or the buffer is not on proper alignment.\r
409\r
410**/\r
411EFI_STATUS\r
412EFIAPI\r
413MmcReadBlocks (\r
414 IN EFI_BLOCK_IO_PROTOCOL *This,\r
415 IN UINT32 MediaId,\r
416 IN EFI_LBA Lba,\r
417 IN UINTN BufferSize,\r
418 OUT VOID *Buffer\r
419 );\r
420\r
421/**\r
422 Writes a specified number of blocks to the device.\r
423\r
3402aac7 424 This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks().\r
1bfda055 425 It writes a specified number of blocks to the device.\r
426 All blocks are written, or an error is returned.\r
427\r
428 @param This Indicates a pointer to the calling context.\r
429 @param MediaId The media ID that the write request is for.\r
430 @param Lba The starting logical block address to be written.\r
431 @param BufferSize The size of the Buffer in bytes.\r
432 This must be a multiple of the intrinsic block size of the device.\r
433 @param Buffer Pointer to the source buffer for the data.\r
434\r
435 @retval EFI_SUCCESS The data were written correctly to the device.\r
436 @retval EFI_WRITE_PROTECTED The device cannot be written to.\r
437 @retval EFI_NO_MEDIA There is no media in the device.\r
438 @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.\r
439 @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the write operation.\r
440 @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic\r
441 block size of the device.\r
442 @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,\r
443 or the buffer is not on proper alignment.\r
444\r
445**/\r
446EFI_STATUS\r
447EFIAPI\r
448MmcWriteBlocks (\r
449 IN EFI_BLOCK_IO_PROTOCOL *This,\r
450 IN UINT32 MediaId,\r
451 IN EFI_LBA Lba,\r
452 IN UINTN BufferSize,\r
453 IN VOID *Buffer\r
454 );\r
455\r
456/**\r
457 Flushes all modified data to a physical block device.\r
458\r
459 @param This Indicates a pointer to the calling context.\r
460\r
461 @retval EFI_SUCCESS All outstanding data were written correctly to the device.\r
462 @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data.\r
463 @retval EFI_NO_MEDIA There is no media in the device.\r
464\r
465**/\r
466EFI_STATUS\r
467EFIAPI\r
468MmcFlushBlocks (\r
469 IN EFI_BLOCK_IO_PROTOCOL *This\r
470 );\r
471\r
b4fdedc2
OM
472EFI_STATUS\r
473MmcNotifyState (\r
474 IN MMC_HOST_INSTANCE *MmcHostInstance,\r
475 IN MMC_STATE State\r
476 );\r
477\r
478EFI_STATUS\r
479InitializeMmcDevice (\r
480 IN MMC_HOST_INSTANCE *MmcHost\r
40842a5e 481 );\r
482\r
483VOID\r
484EFIAPI\r
485CheckCardsCallback (\r
486 IN EFI_EVENT Event,\r
487 IN VOID *Context\r
488 );\r
489\r
4ca3c688
OM
490VOID\r
491PrintCSD (\r
492 IN UINT32* Csd\r
493 );\r
494\r
495VOID\r
496PrintRCA (\r
497 IN UINT32 Rca\r
498 );\r
499\r
500VOID\r
501PrintOCR (\r
502 IN UINT32 Ocr\r
503 );\r
504\r
505VOID\r
506PrintResponseR1 (\r
507 IN UINT32 Response\r
508 );\r
509\r
510VOID\r
511PrintCID (\r
512 IN UINT32* Cid\r
513 );\r
514\r
1bfda055 515#endif\r