IntelFrameworkModulePkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / IdeBusDxe / IdeData.h

/** @file\r
  Header file for IDE Bus Driver's Data Structures\r
\r
  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _IDE_DATA_H_\r
#define _IDE_DATA_H_\r
\r
#include <IndustryStandard/Atapi.h>\r
\r
//\r
// common constants\r
//\r
#define STALL_1_MILLI_SECOND  1000    // stall 1 ms\r
#define STALL_1_SECOND        1000000 // stall 1 second\r
typedef enum {\r
  IdePrimary    = 0,\r
  IdeSecondary  = 1,\r
  IdeMaxChannel = 2\r
} EFI_IDE_CHANNEL;\r
\r
typedef enum {\r
  IdeMaster     = 0,\r
  IdeSlave      = 1,\r
  IdeMaxDevice  = 2\r
} EFI_IDE_DEVICE;\r
\r
typedef enum {\r
  IdeMagnetic,                        /* ZIP Drive or LS120 Floppy Drive */\r
  IdeCdRom,                           /* ATAPI CDROM */\r
  IdeHardDisk,                        /* Hard Disk */\r
  Ide48bitAddressingHardDisk,         /* Hard Disk larger than 120GB */\r
  IdeUnknown\r
} IDE_DEVICE_TYPE;\r
\r
typedef enum {\r
  SenseNoSenseKey,\r
  SenseDeviceNotReadyNoRetry,\r
  SenseDeviceNotReadyNeedRetry,\r
  SenseNoMedia,\r
  SenseMediaChange,\r
  SenseMediaError,\r
  SenseOtherSense\r
} SENSE_RESULT;\r
\r
typedef enum {\r
  AtaUdmaReadOp,\r
  AtaUdmaReadExtOp,\r
  AtaUdmaWriteOp,\r
  AtaUdmaWriteExtOp\r
} ATA_UDMA_OPERATION;\r
\r
//\r
// IDE Registers\r
//\r
typedef union {\r
  UINT16  Command;        /* when write */\r
  UINT16  Status;         /* when read */\r
} IDE_CMD_OR_STATUS;\r
\r
typedef union {\r
  UINT16  Error;          /* when read */\r
  UINT16  Feature;        /* when write */\r
} IDE_ERROR_OR_FEATURE;\r
\r
typedef union {\r
  UINT16  AltStatus;      /* when read */\r
  UINT16  DeviceControl;  /* when write */\r
} IDE_ALTSTATUS_OR_DEVICECONTROL;\r
\r
//\r
// IDE registers set\r
//\r
typedef struct {\r
  UINT16                          Data;\r
  IDE_ERROR_OR_FEATURE            Reg1;\r
  UINT16                          SectorCount;\r
  UINT16                          SectorNumber;\r
  UINT16                          CylinderLsb;\r
  UINT16                          CylinderMsb;\r
  UINT16                          Head;\r
  IDE_CMD_OR_STATUS               Reg;\r
\r
  IDE_ALTSTATUS_OR_DEVICECONTROL  Alt;\r
  UINT16                          DriveAddress;\r
\r
  UINT16                          MasterSlave;\r
  UINT16                          BusMasterBaseAddr;\r
} IDE_BASE_REGISTERS;\r
\r
//\r
// IDE registers' base addresses\r
//\r
typedef struct {\r
  UINT16  CommandBlockBaseAddr;\r
  UINT16  ControlBlockBaseAddr;\r
  UINT16  BusMasterBaseAddr;\r
} IDE_REGISTERS_BASE_ADDR;\r
\r
//\r
// Bit definitions in Programming Interface byte of the Class Code field\r
// in PCI IDE controller's Configuration Space\r
//\r
#define IDE_PRIMARY_OPERATING_MODE            BIT0\r
#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR    BIT1\r
#define IDE_SECONDARY_OPERATING_MODE          BIT2\r
#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR  BIT3\r
\r
\r
//\r
// Bus Master Reg\r
//\r
#define BMIC_NREAD      BIT3\r
#define BMIC_START      BIT0\r
#define BMIS_INTERRUPT  BIT2\r
#define BMIS_ERROR      BIT1\r
\r
#define BMICP_OFFSET    0x00\r
#define BMISP_OFFSET    0x02\r
#define BMIDP_OFFSET    0x04\r
#define BMICS_OFFSET    0x08\r
#define BMISS_OFFSET    0x0A\r
#define BMIDS_OFFSET    0x0C\r
\r
//\r
// Time Out Value For IDE Device Polling\r
//\r
\r
//\r
// ATATIMEOUT is used for waiting time out for ATA device\r
//\r
\r
//\r
// 1 second\r
//\r
#define ATATIMEOUT  1000\r
\r
//\r
// ATAPITIMEOUT is used for waiting operation\r
// except read and write time out for ATAPI device\r
//\r
\r
//\r
// 1 second\r
//\r
#define ATAPITIMEOUT  1000\r
\r
//\r
// ATAPILONGTIMEOUT is used for waiting read and\r
// write operation timeout for ATAPI device\r
//\r
\r
//\r
// 2 seconds\r
//\r
#define CDROMLONGTIMEOUT  2000\r
\r
//\r
// 5 seconds\r
//\r
#define ATAPILONGTIMEOUT  5000\r
\r
//\r
// 10 seconds\r
//\r
#define ATASMARTTIMEOUT   10000\r
\r
\r
//\r
// ATAPI6 related data structure definition\r
//\r
\r
//\r
// The maximum sectors count in 28 bit addressing mode\r
//\r
#define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
  UINT32  RegionBaseAddr;\r
  UINT16  ByteCount;\r
  UINT16  EndOfTable;\r
} IDE_DMA_PRD;\r
\r
#pragma pack()\r
\r
#define SETFEATURE        TRUE\r
#define CLEARFEATURE      FALSE\r
\r
///\r
/// PIO mode definition\r
///\r
typedef enum _ATA_PIO_MODE_ {\r
  AtaPioModeBelow2,\r
  AtaPioMode2,\r
  AtaPioMode3,\r
  AtaPioMode4\r
} ATA_PIO_MODE;\r
\r
//\r
// Multi word DMA definition\r
//\r
typedef enum _ATA_MDMA_MODE_ {\r
  AtaMdmaMode0,\r
  AtaMdmaMode1,\r
  AtaMdmaMode2\r
} ATA_MDMA_MODE;\r
\r
//\r
// UDMA mode definition\r
//\r
typedef enum _ATA_UDMA_MODE_ {\r
  AtaUdmaMode0,\r
  AtaUdmaMode1,\r
  AtaUdmaMode2,\r
  AtaUdmaMode3,\r
  AtaUdmaMode4,\r
  AtaUdmaMode5\r
} ATA_UDMA_MODE;\r
\r
#define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00\r
#define ATA_MODE_CATEGORY_FLOW_PIO    0x01\r
#define ATA_MODE_CATEGORY_MDMA        0x04\r
#define ATA_MODE_CATEGORY_UDMA        0x08\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
  UINT8 ModeNumber : 3;\r
  UINT8 ModeCategory : 5;\r
} ATA_TRANSFER_MODE;\r
\r
typedef struct {\r
  UINT8 Sector;\r
  UINT8 Heads;\r
  UINT8 MultipleSector;\r
} ATA_DRIVE_PARMS;\r
\r
#pragma pack()\r
//\r
// IORDY Sample Point field value\r
//\r
#define ISP_5_CLK 0\r
#define ISP_4_CLK 1\r
#define ISP_3_CLK 2\r
#define ISP_2_CLK 3\r
\r
//\r
// Recovery Time field value\r
//\r
#define RECVY_4_CLK 0\r
#define RECVY_3_CLK 1\r
#define RECVY_2_CLK 2\r
#define RECVY_1_CLK 3\r
\r
//\r
// Slave IDE Timing Register Enable\r
//\r
#define SITRE BIT14\r
\r
//\r
// DMA Timing Enable Only Select 1\r
//\r
#define DTE1  BIT7\r
\r
//\r
// Pre-fetch and Posting Enable Select 1\r
//\r
#define PPE1  BIT6\r
\r
//\r
// IORDY Sample Point Enable Select 1\r
//\r
#define IE1 BIT5\r
\r
//\r
// Fast Timing Bank Drive Select 1\r
//\r
#define TIME1 BIT4\r
\r
//\r
// DMA Timing Enable Only Select 0\r
//\r
#define DTE0  BIT3\r
\r
//\r
// Pre-fetch and Posting Enable Select 0\r
//\r
#define PPE0  BIT2\r
\r
//\r
// IOREY Sample Point Enable Select 0\r
//\r
#define IE0 BIT1\r
\r
//\r
// Fast Timing Bank Drive Select 0\r
//\r
#define TIME0 BIT0\r
\r
#endif\r