]> git.proxmox.com Git - mirror_edk2.git/blame - IntelFrameworkModulePkg/Bus/Pci/PciBus/Dxe/pcibus.h
Remove all blanks lines to avoid build errors.
[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBus / Dxe / pcibus.h
CommitLineData
ead42efc 1/*++\r
2\r
3Copyright (c) 2006 - 2007, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12Module Name:\r
13\r
14 pcibus.h\r
15\r
16Abstract:\r
17\r
18 PCI Bus Driver\r
19\r
20Revision History\r
21\r
22--*/\r
23\r
24#ifndef _EFI_PCI_BUS_H\r
25#define _EFI_PCI_BUS_H\r
26\r
27//\r
28// The package level header files this module uses\r
29//\r
30#include <PiDxe.h>\r
31#include <Common/FrameworkStatusCode.h>\r
32//\r
33// The protocols, PPI and GUID defintions for this module\r
34//\r
35#include <Protocol/LoadedImage.h>\r
36#include <Protocol/PciHostBridgeResourceAllocation.h>\r
37#include <Protocol/PciIo.h>\r
38#include <Guid/PciHotplugDevice.h>\r
39#include <Protocol/PciRootBridgeIo.h>\r
40#include <Protocol/PciHotPlugRequest.h>\r
41#include <Protocol/DevicePath.h>\r
42#include <Protocol/PciPlatform.h>\r
43#include <Protocol/PciHotPlugInit.h>\r
44#include <Protocol/Decompress.h>\r
45#include <Guid/PciOptionRomTable.h>\r
46#include <Protocol/BusSpecificDriverOverride.h>\r
47#include <Protocol/UgaIo.h>\r
48//\r
49// The Library classes this module consumes\r
50//\r
51#include <Library/DebugLib.h>\r
52#include <Library/UefiDriverEntryPoint.h>\r
53#include <Library/BaseLib.h>\r
54#include <Library/UefiLib.h>\r
55#include <Library/BaseMemoryLib.h>\r
56#include <Library/ReportStatusCodeLib.h>\r
57#include <Library/MemoryAllocationLib.h>\r
58#include <Library/UefiBootServicesTableLib.h>\r
59#include <Library/DevicePathLib.h>\r
60#include <Library/PcdLib.h>\r
61#include <Library/PciIncompatibleDeviceSupportLib.h>\r
62\r
63#include <IndustryStandard/pci22.h>\r
64#include <IndustryStandard/Acpi.h>\r
65#include "ComponentName.h"\r
66\r
67//\r
68// Driver Produced Protocol Prototypes\r
69//\r
70\r
71#define VGABASE1 0x3B0\r
72#define VGALIMIT1 0x3BB\r
73\r
74#define VGABASE2 0x3C0\r
75#define VGALIMIT2 0x3DF\r
76\r
77#define ISABASE 0x100\r
78#define ISALIMIT 0x3FF\r
79\r
80typedef enum {\r
81 PciBarTypeUnknown = 0,\r
82 PciBarTypeIo16,\r
83 PciBarTypeIo32,\r
84 PciBarTypeMem32,\r
85 PciBarTypePMem32,\r
86 PciBarTypeMem64,\r
87 PciBarTypePMem64,\r
88 PciBarTypeIo,\r
89 PciBarTypeMem,\r
90 PciBarTypeMaxType\r
91} PCI_BAR_TYPE;\r
92\r
93typedef struct {\r
94 UINT64 BaseAddress;\r
95 UINT64 Length;\r
96 UINT64 Alignment;\r
97 PCI_BAR_TYPE BarType;\r
98 BOOLEAN Prefetchable;\r
99 UINT8 MemType;\r
100 UINT8 Offset;\r
101} PCI_BAR;\r
102\r
103#define PPB_BAR_0 0\r
104#define PPB_BAR_1 1\r
105#define PPB_IO_RANGE 2\r
106#define PPB_MEM32_RANGE 3\r
107#define PPB_PMEM32_RANGE 4\r
108#define PPB_PMEM64_RANGE 5\r
109#define PPB_MEM64_RANGE 0xFF\r
110\r
111#define P2C_BAR_0 0\r
112#define P2C_MEM_1 1\r
113#define P2C_MEM_2 2\r
114#define P2C_IO_1 3\r
115#define P2C_IO_2 4\r
116\r
117#define PCI_IO_DEVICE_SIGNATURE EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')\r
118\r
119#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
120#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
121#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
122#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
123#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
124#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
125#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
126\r
127#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
128//\r
129// Define resource status constant\r
130//\r
131#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
132#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
133#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
134\r
135//\r
136// Define option for attribute\r
137//\r
138#define EFI_SET_SUPPORTS 0\r
139#define EFI_SET_ATTRIBUTES 1\r
140\r
141typedef struct _PCI_IO_DEVICE {\r
142 UINT32 Signature;\r
143 EFI_HANDLE Handle;\r
144 EFI_PCI_IO_PROTOCOL PciIo;\r
145 LIST_ENTRY Link;\r
146\r
147 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
148 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
149 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
150\r
151 //\r
152 // PCI configuration space header type\r
153 //\r
154 PCI_TYPE00 Pci;\r
155\r
156 //\r
157 // Bus number, Device number, Function number\r
158 //\r
159 UINT8 BusNumber;\r
160 UINT8 DeviceNumber;\r
161 UINT8 FunctionNumber;\r
162\r
163 //\r
164 // BAR for this PCI Device\r
165 //\r
166 PCI_BAR PciBar[PCI_MAX_BAR];\r
167\r
168 //\r
169 // The bridge device this pci device is subject to\r
170 //\r
171 struct _PCI_IO_DEVICE *Parent;\r
172\r
173 //\r
174 // A linked list for children Pci Device if it is bridge device\r
175 //\r
176 LIST_ENTRY ChildList;\r
177\r
178 //\r
179 // TURE if the PCI bus driver creates the handle for this PCI device\r
180 //\r
181 BOOLEAN Registered;\r
182\r
183 //\r
184 // TRUE if the PCI bus driver successfully allocates the resource required by\r
185 // this PCI device\r
186 //\r
187 BOOLEAN Allocated;\r
188\r
189 //\r
190 // The attribute this PCI device currently set\r
191 //\r
192 UINT64 Attributes;\r
193\r
194 //\r
195 // The attributes this PCI device actually supports\r
196 //\r
197 UINT64 Supports;\r
198\r
199 //\r
200 // The resource decode the bridge supports\r
201 //\r
202 UINT32 Decodes;\r
203\r
204 //\r
205 // The OptionRom Size\r
206 //\r
207 UINT64 RomSize;\r
208\r
209 //\r
210 // The OptionRom Size\r
211 //\r
212 UINT64 RomBase;\r
213\r
214 //\r
215 // TRUE if all OpROM (in device or in platform specific position) have been processed\r
216 //\r
217 BOOLEAN AllOpRomProcessed;\r
218\r
219 //\r
220 // TRUE if there is any EFI driver in the OptionRom\r
221 //\r
222 BOOLEAN BusOverride;\r
223\r
224 //\r
225 // A list tracking reserved resource on a bridge device\r
226 //\r
227 LIST_ENTRY ReservedResourceList;\r
228\r
229 //\r
230 // A list tracking image handle of platform specific overriding driver\r
231 //\r
232 LIST_ENTRY OptionRomDriverList;\r
233\r
234 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
235 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
236\r
237 BOOLEAN IsPciExp;\r
238\r
239} PCI_IO_DEVICE;\r
240\r
241\r
242#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
243 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
244\r
245#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
246 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
247\r
248#define PCI_IO_DEVICE_FROM_LINK(a) \\r
249 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
250\r
251//\r
252// Global Variables\r
253//\r
254extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
255extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
256extern LIST_ENTRY gPciDevicePool;\r
257extern BOOLEAN gFullEnumeration;\r
258extern UINTN gPciHostBridgeNumber;\r
259extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
260extern UINT64 gAllOne;\r
261extern UINT64 gAllZero;\r
262\r
263extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
264\r
265#include "PciIo.h"\r
266#include "PciCommand.h"\r
267#include "PciDeviceSupport.h"\r
268#include "PciEnumerator.h"\r
269#include "PciEnumeratorSupport.h"\r
270#include "PciDriverOverride.h"\r
271#include "PciRomTable.h"\r
272#include "PciOptionRomSupport.h"\r
273#include "PciPowerManagement.h"\r
274#include "PciHotPlugSupport.h"\r
275#include "PciLib.h"\r
276\r
277//\r
278// PCI Bus Support Function Prototypes\r
279//\r
280EFI_STATUS\r
281EFIAPI\r
282PciBusDriverBindingSupported (\r
283 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
284 IN EFI_HANDLE Controller,\r
285 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
286 );\r
287\r
288EFI_STATUS\r
289EFIAPI\r
290PciBusDriverBindingStart (\r
291 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
292 IN EFI_HANDLE Controller,\r
293 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
294 );\r
295\r
296EFI_STATUS\r
297EFIAPI\r
298PciBusDriverBindingStop (\r
299 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
300 IN EFI_HANDLE Controller,\r
301 IN UINTN NumberOfChildren,\r
302 IN EFI_HANDLE *ChildHandleBuffer\r
303 );\r
304\r
305#endif\r