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Add PciBus Module
[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBus / Dxe / pcibus.h
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ead42efc 1/*++\r
2\r
3Copyright (c) 2006 - 2007, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12Module Name:\r
13\r
14 pcibus.h\r
15\r
16Abstract:\r
17\r
18 PCI Bus Driver\r
19\r
20Revision History\r
21\r
22--*/\r
23\r
24#ifndef _EFI_PCI_BUS_H\r
25#define _EFI_PCI_BUS_H\r
26\r
27//\r
28// The package level header files this module uses\r
29//\r
30#include <PiDxe.h>\r
31#include <Common/FrameworkStatusCode.h>\r
32//\r
33// The protocols, PPI and GUID defintions for this module\r
34//\r
35#include <Protocol/LoadedImage.h>\r
36#include <Protocol/PciHostBridgeResourceAllocation.h>\r
37#include <Protocol/PciIo.h>\r
38#include <Guid/PciHotplugDevice.h>\r
39#include <Protocol/PciRootBridgeIo.h>\r
40#include <Protocol/PciHotPlugRequest.h>\r
41#include <Protocol/DevicePath.h>\r
42#include <Protocol/PciPlatform.h>\r
43#include <Protocol/PciHotPlugInit.h>\r
44#include <Protocol/Decompress.h>\r
45#include <Guid/PciOptionRomTable.h>\r
46#include <Protocol/BusSpecificDriverOverride.h>\r
47#include <Protocol/UgaIo.h>\r
48//\r
49// The Library classes this module consumes\r
50//\r
51#include <Library/DebugLib.h>\r
52#include <Library/UefiDriverEntryPoint.h>\r
53#include <Library/BaseLib.h>\r
54#include <Library/UefiLib.h>\r
55#include <Library/BaseMemoryLib.h>\r
56#include <Library/ReportStatusCodeLib.h>\r
57#include <Library/MemoryAllocationLib.h>\r
58#include <Library/UefiBootServicesTableLib.h>\r
59#include <Library/DevicePathLib.h>\r
60#include <Library/PcdLib.h>\r
61#include <Library/PciIncompatibleDeviceSupportLib.h>\r
62\r
b1ef4015 63#include <IndustryStandard/Pci23.h>\r
64#include <IndustryStandard/PeImage.h>\r
ead42efc 65#include <IndustryStandard/Acpi.h>\r
66#include "ComponentName.h"\r
67\r
b1ef4015 68///\r
69/// Device handle Extended Data. Used for many\r
70/// errors and progress codes to point to the device.\r
71///\r
72typedef struct {\r
73 EFI_HANDLE Handle;\r
74} REPORT_STATUS_CODE_LIBRARY_DEVICE_HANDLE_EXTENDED_DATA;\r
75\r
76///\r
77/// Resource Allocation Failure Extended Error Data\r
78///\r
79typedef struct {\r
80 UINT32 Bar;\r
81 UINT16 DevicePathSize;\r
82 UINT16 ReqResSize;\r
83 UINT16 AllocResSize;\r
84 UINT8 *DevicePath;\r
85 UINT8 *ReqRes;\r
86 UINT8 *AllocRes;\r
87} REPORT_STATUS_CODE_LIBRARY_RESOURCE_ALLOC_FAILURE_ERROR_DATA;\r
88\r
89\r
ead42efc 90//\r
91// Driver Produced Protocol Prototypes\r
92//\r
93\r
94#define VGABASE1 0x3B0\r
95#define VGALIMIT1 0x3BB\r
96\r
97#define VGABASE2 0x3C0\r
98#define VGALIMIT2 0x3DF\r
99\r
100#define ISABASE 0x100\r
101#define ISALIMIT 0x3FF\r
102\r
103typedef enum {\r
104 PciBarTypeUnknown = 0,\r
105 PciBarTypeIo16,\r
106 PciBarTypeIo32,\r
107 PciBarTypeMem32,\r
108 PciBarTypePMem32,\r
109 PciBarTypeMem64,\r
110 PciBarTypePMem64,\r
111 PciBarTypeIo,\r
112 PciBarTypeMem,\r
113 PciBarTypeMaxType\r
114} PCI_BAR_TYPE;\r
115\r
116typedef struct {\r
117 UINT64 BaseAddress;\r
118 UINT64 Length;\r
119 UINT64 Alignment;\r
120 PCI_BAR_TYPE BarType;\r
121 BOOLEAN Prefetchable;\r
122 UINT8 MemType;\r
123 UINT8 Offset;\r
124} PCI_BAR;\r
125\r
126#define PPB_BAR_0 0\r
127#define PPB_BAR_1 1\r
128#define PPB_IO_RANGE 2\r
129#define PPB_MEM32_RANGE 3\r
130#define PPB_PMEM32_RANGE 4\r
131#define PPB_PMEM64_RANGE 5\r
132#define PPB_MEM64_RANGE 0xFF\r
133\r
134#define P2C_BAR_0 0\r
135#define P2C_MEM_1 1\r
136#define P2C_MEM_2 2\r
137#define P2C_IO_1 3\r
138#define P2C_IO_2 4\r
139\r
140#define PCI_IO_DEVICE_SIGNATURE EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')\r
141\r
142#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
143#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
144#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
145#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
146#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
147#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
148#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
149\r
150#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
151//\r
152// Define resource status constant\r
153//\r
154#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
155#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
156#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
157\r
158//\r
159// Define option for attribute\r
160//\r
161#define EFI_SET_SUPPORTS 0\r
162#define EFI_SET_ATTRIBUTES 1\r
163\r
164typedef struct _PCI_IO_DEVICE {\r
165 UINT32 Signature;\r
166 EFI_HANDLE Handle;\r
167 EFI_PCI_IO_PROTOCOL PciIo;\r
168 LIST_ENTRY Link;\r
169\r
170 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
171 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
172 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
173\r
174 //\r
175 // PCI configuration space header type\r
176 //\r
177 PCI_TYPE00 Pci;\r
178\r
179 //\r
180 // Bus number, Device number, Function number\r
181 //\r
182 UINT8 BusNumber;\r
183 UINT8 DeviceNumber;\r
184 UINT8 FunctionNumber;\r
185\r
186 //\r
187 // BAR for this PCI Device\r
188 //\r
189 PCI_BAR PciBar[PCI_MAX_BAR];\r
190\r
191 //\r
192 // The bridge device this pci device is subject to\r
193 //\r
194 struct _PCI_IO_DEVICE *Parent;\r
195\r
196 //\r
197 // A linked list for children Pci Device if it is bridge device\r
198 //\r
199 LIST_ENTRY ChildList;\r
200\r
201 //\r
202 // TURE if the PCI bus driver creates the handle for this PCI device\r
203 //\r
204 BOOLEAN Registered;\r
205\r
206 //\r
207 // TRUE if the PCI bus driver successfully allocates the resource required by\r
208 // this PCI device\r
209 //\r
210 BOOLEAN Allocated;\r
211\r
212 //\r
213 // The attribute this PCI device currently set\r
214 //\r
215 UINT64 Attributes;\r
216\r
217 //\r
218 // The attributes this PCI device actually supports\r
219 //\r
220 UINT64 Supports;\r
221\r
222 //\r
223 // The resource decode the bridge supports\r
224 //\r
225 UINT32 Decodes;\r
226\r
227 //\r
228 // The OptionRom Size\r
229 //\r
230 UINT64 RomSize;\r
231\r
232 //\r
233 // The OptionRom Size\r
234 //\r
235 UINT64 RomBase;\r
236\r
237 //\r
238 // TRUE if all OpROM (in device or in platform specific position) have been processed\r
239 //\r
240 BOOLEAN AllOpRomProcessed;\r
241\r
242 //\r
243 // TRUE if there is any EFI driver in the OptionRom\r
244 //\r
245 BOOLEAN BusOverride;\r
246\r
247 //\r
248 // A list tracking reserved resource on a bridge device\r
249 //\r
250 LIST_ENTRY ReservedResourceList;\r
251\r
252 //\r
253 // A list tracking image handle of platform specific overriding driver\r
254 //\r
255 LIST_ENTRY OptionRomDriverList;\r
256\r
257 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
258 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
259\r
260 BOOLEAN IsPciExp;\r
261\r
262} PCI_IO_DEVICE;\r
263\r
264\r
265#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
266 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
267\r
268#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
269 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
270\r
271#define PCI_IO_DEVICE_FROM_LINK(a) \\r
272 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
273\r
274//\r
275// Global Variables\r
276//\r
277extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
278extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
279extern LIST_ENTRY gPciDevicePool;\r
280extern BOOLEAN gFullEnumeration;\r
281extern UINTN gPciHostBridgeNumber;\r
282extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
283extern UINT64 gAllOne;\r
284extern UINT64 gAllZero;\r
285\r
286extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
287\r
288#include "PciIo.h"\r
289#include "PciCommand.h"\r
290#include "PciDeviceSupport.h"\r
291#include "PciEnumerator.h"\r
292#include "PciEnumeratorSupport.h"\r
293#include "PciDriverOverride.h"\r
294#include "PciRomTable.h"\r
295#include "PciOptionRomSupport.h"\r
296#include "PciPowerManagement.h"\r
297#include "PciHotPlugSupport.h"\r
298#include "PciLib.h"\r
299\r
300//\r
301// PCI Bus Support Function Prototypes\r
302//\r
303EFI_STATUS\r
304EFIAPI\r
305PciBusDriverBindingSupported (\r
306 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
307 IN EFI_HANDLE Controller,\r
308 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
309 );\r
310\r
311EFI_STATUS\r
312EFIAPI\r
313PciBusDriverBindingStart (\r
314 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
315 IN EFI_HANDLE Controller,\r
316 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
317 );\r
318\r
319EFI_STATUS\r
320EFIAPI\r
321PciBusDriverBindingStop (\r
322 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
323 IN EFI_HANDLE Controller,\r
324 IN UINTN NumberOfChildren,\r
325 IN EFI_HANDLE *ChildHandleBuffer\r
326 );\r
327\r
328#endif\r
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