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1 | /**@file\r |
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2 | \r |
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3 | Copyright (c) 2006, Intel Corporation\r |
4 | All rights reserved. This program and the accompanying materials\r |
5 | are licensed and made available under the terms and conditions of the BSD License\r |
6 | which accompanies this distribution. The full text of the license may be found at\r |
7 | http://opensource.org/licenses/bsd-license.php\r |
8 | \r |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
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11 | \r |
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12 | **/\r |
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13 | \r |
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14 | \r |
15 | #ifndef _EFI_PCI_BUS_H\r |
16 | #define _EFI_PCI_BUS_H\r |
17 | \r |
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18 | \r |
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19 | #include <FrameworkDxe.h>\r |
20 | \r |
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21 | \r |
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22 | #include <Protocol/LoadedImage.h>\r |
23 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r |
24 | #include <Protocol/PciIo.h>\r |
25 | #include <Guid/PciHotplugDevice.h>\r |
26 | #include <Protocol/PciRootBridgeIo.h>\r |
27 | #include <Protocol/PciHotPlugRequest.h>\r |
28 | #include <Protocol/DevicePath.h>\r |
29 | #include <Protocol/PciPlatform.h>\r |
30 | #include <Protocol/PciHotPlugInit.h>\r |
31 | #include <Protocol/Decompress.h>\r |
32 | #include <Guid/PciOptionRomTable.h>\r |
33 | #include <Protocol/BusSpecificDriverOverride.h>\r |
34 | #include <Protocol/UgaIo.h>\r |
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35 | #include <Protocol/IncompatiblePciDeviceSupport.h>\r |
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36 | \r |
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37 | #include <Library/DebugLib.h>\r |
38 | #include <Library/UefiDriverEntryPoint.h>\r |
39 | #include <Library/BaseLib.h>\r |
40 | #include <Library/UefiLib.h>\r |
41 | #include <Library/BaseMemoryLib.h>\r |
42 | #include <Library/ReportStatusCodeLib.h>\r |
43 | #include <Library/MemoryAllocationLib.h>\r |
44 | #include <Library/UefiBootServicesTableLib.h>\r |
45 | #include <Library/DevicePathLib.h>\r |
46 | #include <Library/PcdLib.h>\r |
47 | #include <Library/PciIncompatibleDeviceSupportLib.h>\r |
48 | \r |
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49 | #include <IndustryStandard/Pci.h>\r |
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50 | #include <IndustryStandard/PeImage.h>\r |
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51 | #include <IndustryStandard/Acpi.h>\r |
52 | #include "ComponentName.h"\r |
53 | \r |
54 | //\r |
55 | // Driver Produced Protocol Prototypes\r |
56 | //\r |
57 | \r |
58 | #define VGABASE1 0x3B0\r |
59 | #define VGALIMIT1 0x3BB\r |
60 | \r |
61 | #define VGABASE2 0x3C0\r |
62 | #define VGALIMIT2 0x3DF\r |
63 | \r |
64 | #define ISABASE 0x100\r |
65 | #define ISALIMIT 0x3FF\r |
66 | \r |
67 | typedef enum {\r |
68 | PciBarTypeUnknown = 0,\r |
69 | PciBarTypeIo16,\r |
70 | PciBarTypeIo32,\r |
71 | PciBarTypeMem32,\r |
72 | PciBarTypePMem32,\r |
73 | PciBarTypeMem64,\r |
74 | PciBarTypePMem64,\r |
75 | PciBarTypeIo,\r |
76 | PciBarTypeMem,\r |
77 | PciBarTypeMaxType\r |
78 | } PCI_BAR_TYPE;\r |
79 | \r |
80 | typedef struct {\r |
81 | UINT64 BaseAddress;\r |
82 | UINT64 Length;\r |
83 | UINT64 Alignment;\r |
84 | PCI_BAR_TYPE BarType;\r |
85 | BOOLEAN Prefetchable;\r |
86 | UINT8 MemType;\r |
87 | UINT8 Offset;\r |
88 | } PCI_BAR;\r |
89 | \r |
90 | #define PPB_BAR_0 0\r |
91 | #define PPB_BAR_1 1\r |
92 | #define PPB_IO_RANGE 2\r |
93 | #define PPB_MEM32_RANGE 3\r |
94 | #define PPB_PMEM32_RANGE 4\r |
95 | #define PPB_PMEM64_RANGE 5\r |
96 | #define PPB_MEM64_RANGE 0xFF\r |
97 | \r |
98 | #define P2C_BAR_0 0\r |
99 | #define P2C_MEM_1 1\r |
100 | #define P2C_MEM_2 2\r |
101 | #define P2C_IO_1 3\r |
102 | #define P2C_IO_2 4\r |
103 | \r |
104 | #define PCI_IO_DEVICE_SIGNATURE EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')\r |
105 | \r |
106 | #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r |
107 | #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r |
108 | #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r |
109 | #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r |
110 | #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r |
111 | #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r |
112 | #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r |
113 | \r |
114 | #define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r |
115 | //\r |
116 | // Define resource status constant\r |
117 | //\r |
118 | #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r |
119 | #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r |
120 | #define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r |
121 | \r |
122 | //\r |
123 | // Define option for attribute\r |
124 | //\r |
125 | #define EFI_SET_SUPPORTS 0\r |
126 | #define EFI_SET_ATTRIBUTES 1\r |
127 | \r |
128 | typedef struct _PCI_IO_DEVICE {\r |
129 | UINT32 Signature;\r |
130 | EFI_HANDLE Handle;\r |
131 | EFI_PCI_IO_PROTOCOL PciIo;\r |
132 | LIST_ENTRY Link;\r |
133 | \r |
134 | EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r |
135 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r |
136 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r |
137 | \r |
138 | //\r |
139 | // PCI configuration space header type\r |
140 | //\r |
141 | PCI_TYPE00 Pci;\r |
142 | \r |
143 | //\r |
144 | // Bus number, Device number, Function number\r |
145 | //\r |
146 | UINT8 BusNumber;\r |
147 | UINT8 DeviceNumber;\r |
148 | UINT8 FunctionNumber;\r |
149 | \r |
150 | //\r |
151 | // BAR for this PCI Device\r |
152 | //\r |
153 | PCI_BAR PciBar[PCI_MAX_BAR];\r |
154 | \r |
155 | //\r |
156 | // The bridge device this pci device is subject to\r |
157 | //\r |
158 | struct _PCI_IO_DEVICE *Parent;\r |
159 | \r |
160 | //\r |
161 | // A linked list for children Pci Device if it is bridge device\r |
162 | //\r |
163 | LIST_ENTRY ChildList;\r |
164 | \r |
165 | //\r |
166 | // TURE if the PCI bus driver creates the handle for this PCI device\r |
167 | //\r |
168 | BOOLEAN Registered;\r |
169 | \r |
170 | //\r |
171 | // TRUE if the PCI bus driver successfully allocates the resource required by\r |
172 | // this PCI device\r |
173 | //\r |
174 | BOOLEAN Allocated;\r |
175 | \r |
176 | //\r |
177 | // The attribute this PCI device currently set\r |
178 | //\r |
179 | UINT64 Attributes;\r |
180 | \r |
181 | //\r |
182 | // The attributes this PCI device actually supports\r |
183 | //\r |
184 | UINT64 Supports;\r |
185 | \r |
186 | //\r |
187 | // The resource decode the bridge supports\r |
188 | //\r |
189 | UINT32 Decodes;\r |
190 | \r |
191 | //\r |
192 | // The OptionRom Size\r |
193 | //\r |
194 | UINT64 RomSize;\r |
195 | \r |
196 | //\r |
197 | // The OptionRom Size\r |
198 | //\r |
199 | UINT64 RomBase;\r |
200 | \r |
201 | //\r |
202 | // TRUE if all OpROM (in device or in platform specific position) have been processed\r |
203 | //\r |
204 | BOOLEAN AllOpRomProcessed;\r |
205 | \r |
206 | //\r |
207 | // TRUE if there is any EFI driver in the OptionRom\r |
208 | //\r |
209 | BOOLEAN BusOverride;\r |
210 | \r |
211 | //\r |
212 | // A list tracking reserved resource on a bridge device\r |
213 | //\r |
214 | LIST_ENTRY ReservedResourceList;\r |
215 | \r |
216 | //\r |
217 | // A list tracking image handle of platform specific overriding driver\r |
218 | //\r |
219 | LIST_ENTRY OptionRomDriverList;\r |
220 | \r |
221 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r |
222 | EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r |
223 | \r |
224 | BOOLEAN IsPciExp;\r |
225 | \r |
226 | } PCI_IO_DEVICE;\r |
227 | \r |
228 | \r |
229 | #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r |
230 | CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r |
231 | \r |
232 | #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r |
233 | CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r |
234 | \r |
235 | #define PCI_IO_DEVICE_FROM_LINK(a) \\r |
236 | CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r |
237 | \r |
238 | //\r |
239 | // Global Variables\r |
240 | //\r |
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241 | extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r |
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242 | extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r |
243 | extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r |
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244 | extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r |
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245 | extern LIST_ENTRY gPciDevicePool;\r |
246 | extern BOOLEAN gFullEnumeration;\r |
247 | extern UINTN gPciHostBridgeNumber;\r |
248 | extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r |
249 | extern UINT64 gAllOne;\r |
250 | extern UINT64 gAllZero;\r |
251 | \r |
252 | extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r |
253 | \r |
254 | #include "PciIo.h"\r |
255 | #include "PciCommand.h"\r |
256 | #include "PciDeviceSupport.h"\r |
257 | #include "PciEnumerator.h"\r |
258 | #include "PciEnumeratorSupport.h"\r |
259 | #include "PciDriverOverride.h"\r |
260 | #include "PciRomTable.h"\r |
261 | #include "PciOptionRomSupport.h"\r |
262 | #include "PciPowerManagement.h"\r |
263 | #include "PciHotPlugSupport.h"\r |
264 | #include "PciLib.h"\r |
265 | \r |
266 | //\r |
267 | // PCI Bus Support Function Prototypes\r |
268 | //\r |
269 | EFI_STATUS\r |
270 | EFIAPI\r |
271 | PciBusDriverBindingSupported (\r |
272 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r |
273 | IN EFI_HANDLE Controller,\r |
274 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r |
275 | );\r |
276 | \r |
277 | EFI_STATUS\r |
278 | EFIAPI\r |
279 | PciBusDriverBindingStart (\r |
280 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r |
281 | IN EFI_HANDLE Controller,\r |
282 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r |
283 | );\r |
284 | \r |
285 | EFI_STATUS\r |
286 | EFIAPI\r |
287 | PciBusDriverBindingStop (\r |
288 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r |
289 | IN EFI_HANDLE Controller,\r |
290 | IN UINTN NumberOfChildren,\r |
291 | IN EFI_HANDLE *ChildHandleBuffer\r |
292 | );\r |
293 | \r |
294 | #endif\r |