]>
Commit | Line | Data |
---|---|---|
97404058 | 1 | /** @file\r |
a3b8e257 | 2 | This module implement Pci register operation interface for \r |
3 | Pci device.\r | |
4 | \r | |
3db51098 | 5 | Copyright (c) 2006, Intel Corporation \r |
6 | All rights reserved. This program and the accompanying materials \r | |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
ead42efc | 13 | \r |
3db51098 | 14 | **/\r |
ead42efc | 15 | \r |
ead42efc | 16 | \r |
19efd9ec | 17 | #include "PciBus.h"\r |
ead42efc | 18 | \r |
a3b8e257 | 19 | /**\r |
20 | Operate the PCI register via PciIo function interface.\r | |
21 | \r | |
22 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r | |
23 | @param Command Operator command\r | |
24 | @param Offset The address within the PCI configuration space for the PCI controller.\r | |
25 | @param Operation Type of Operation\r | |
26 | @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER\r | |
27 | \r | |
28 | @return status of PciIo operation\r | |
29 | **/\r | |
ead42efc | 30 | EFI_STATUS\r |
31 | PciOperateRegister (\r | |
32 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
33 | IN UINT16 Command,\r | |
34 | IN UINT8 Offset,\r | |
35 | IN UINT8 Operation,\r | |
36 | OUT UINT16 *PtrCommand\r | |
37 | )\r | |
ead42efc | 38 | {\r |
39 | UINT16 OldCommand;\r | |
40 | EFI_STATUS Status;\r | |
41 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
42 | \r | |
43 | OldCommand = 0;\r | |
44 | PciIo = &PciIoDevice->PciIo;\r | |
45 | \r | |
46 | if (Operation != EFI_SET_REGISTER) {\r | |
47 | Status = PciIoRead (\r | |
a3b8e257 | 48 | PciIo,\r |
49 | EfiPciIoWidthUint16,\r | |
50 | Offset,\r | |
51 | 1,\r | |
52 | &OldCommand\r | |
53 | );\r | |
ead42efc | 54 | \r |
55 | if (Operation == EFI_GET_REGISTER) {\r | |
56 | *PtrCommand = OldCommand;\r | |
57 | return Status;\r | |
58 | }\r | |
59 | }\r | |
60 | \r | |
61 | if (Operation == EFI_ENABLE_REGISTER) {\r | |
62 | OldCommand = (UINT16) (OldCommand | Command);\r | |
63 | } else if (Operation == EFI_DISABLE_REGISTER) {\r | |
64 | OldCommand = (UINT16) (OldCommand & ~(Command));\r | |
65 | } else {\r | |
66 | OldCommand = Command;\r | |
67 | }\r | |
68 | \r | |
69 | return PciIoWrite (\r | |
a3b8e257 | 70 | PciIo,\r |
71 | EfiPciIoWidthUint16,\r | |
72 | Offset,\r | |
73 | 1,\r | |
74 | &OldCommand\r | |
75 | );\r | |
ead42efc | 76 | }\r |
77 | \r | |
a3b8e257 | 78 | /**\r |
79 | check the cpability of this device supports\r | |
80 | \r | |
81 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE\r | |
82 | \r | |
83 | @retval TRUE Support\r | |
97404058 | 84 | @retval FALSE Not support.\r |
a3b8e257 | 85 | **/\r |
ead42efc | 86 | BOOLEAN\r |
87 | PciCapabilitySupport (\r | |
88 | IN PCI_IO_DEVICE *PciIoDevice\r | |
89 | )\r | |
ead42efc | 90 | {\r |
91 | \r | |
5326528b | 92 | if ((PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) != 0) {\r |
ead42efc | 93 | return TRUE;\r |
94 | }\r | |
95 | \r | |
96 | return FALSE;\r | |
97 | }\r | |
98 | \r | |
a3b8e257 | 99 | /**\r |
100 | Locate cap reg.\r | |
101 | \r | |
102 | @param PciIoDevice - A pointer to the PCI_IO_DEVICE.\r | |
103 | @param CapId - The cap ID.\r | |
104 | @param Offset - A pointer to the offset.\r | |
105 | @param NextRegBlock - A pointer to the next block.\r | |
106 | \r | |
107 | @retval EFI_UNSUPPORTED Pci device does not support\r | |
108 | @retval EFI_NOT_FOUND Pci device support but can not find register block.\r | |
109 | @retval EFI_SUCCESS Success to locate capability register block\r | |
110 | **/\r | |
ead42efc | 111 | EFI_STATUS\r |
112 | LocateCapabilityRegBlock (\r | |
113 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
114 | IN UINT8 CapId,\r | |
115 | IN OUT UINT8 *Offset,\r | |
116 | OUT UINT8 *NextRegBlock OPTIONAL\r | |
117 | )\r | |
ead42efc | 118 | {\r |
119 | UINT8 CapabilityPtr;\r | |
120 | UINT16 CapabilityEntry;\r | |
121 | UINT8 CapabilityID;\r | |
122 | \r | |
123 | //\r | |
124 | // To check the cpability of this device supports\r | |
125 | //\r | |
126 | if (!PciCapabilitySupport (PciIoDevice)) {\r | |
127 | return EFI_UNSUPPORTED;\r | |
128 | }\r | |
129 | \r | |
130 | if (*Offset != 0) {\r | |
131 | CapabilityPtr = *Offset;\r | |
132 | } else {\r | |
133 | \r | |
134 | CapabilityPtr = 0;\r | |
135 | if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r | |
136 | \r | |
137 | PciIoRead (\r | |
138 | &PciIoDevice->PciIo,\r | |
139 | EfiPciIoWidthUint8,\r | |
140 | EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r | |
141 | 1,\r | |
142 | &CapabilityPtr\r | |
143 | );\r | |
144 | } else {\r | |
145 | \r | |
146 | PciIoRead (\r | |
147 | &PciIoDevice->PciIo,\r | |
148 | EfiPciIoWidthUint8,\r | |
bc14bdb3 | 149 | PCI_CAPBILITY_POINTER_OFFSET,\r |
ead42efc | 150 | 1,\r |
151 | &CapabilityPtr\r | |
152 | );\r | |
153 | }\r | |
154 | }\r | |
155 | \r | |
f680f867 | 156 | while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r |
ead42efc | 157 | PciIoRead (\r |
158 | &PciIoDevice->PciIo,\r | |
159 | EfiPciIoWidthUint16,\r | |
160 | CapabilityPtr,\r | |
161 | 1,\r | |
162 | &CapabilityEntry\r | |
163 | );\r | |
164 | \r | |
165 | CapabilityID = (UINT8) CapabilityEntry;\r | |
166 | \r | |
167 | if (CapabilityID == CapId) {\r | |
168 | *Offset = CapabilityPtr;\r | |
169 | if (NextRegBlock != NULL) {\r | |
170 | *NextRegBlock = (UINT8) (CapabilityEntry >> 8);\r | |
171 | }\r | |
172 | \r | |
173 | return EFI_SUCCESS;\r | |
174 | }\r | |
175 | \r | |
176 | CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r | |
177 | }\r | |
178 | \r | |
179 | return EFI_NOT_FOUND;\r | |
180 | }\r | |
a3b8e257 | 181 | \r |