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1 | /**@file\r |
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2 | \r |
| 3 | Copyright (c) 2006, Intel Corporation \r |
| 4 | All rights reserved. This program and the accompanying materials \r |
| 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r |
| 7 | http://opensource.org/licenses/bsd-license.php \r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | \r |
| 3db51098 |
12 | **/\r |
| ead42efc |
13 | \r |
| ead42efc |
14 | \r |
| 15 | #ifndef _EFI_PCI_COMMAND_H\r |
| 16 | #define _EFI_PCI_COMMAND_H\r |
| 17 | \r |
| 18 | //\r |
| 19 | // The PCI Command register bits owned by PCI Bus driver.\r |
| 20 | //\r |
| 21 | // They should be cleared at the beginning. The other registers\r |
| 22 | // are owned by chipset, we should not touch them.\r |
| 23 | //\r |
| 24 | #define EFI_PCI_COMMAND_BITS_OWNED ( \\r |
| 25 | EFI_PCI_COMMAND_IO_SPACE | \\r |
| 26 | EFI_PCI_COMMAND_MEMORY_SPACE | \\r |
| 27 | EFI_PCI_COMMAND_BUS_MASTER | \\r |
| 28 | EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \\r |
| 29 | EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \\r |
| 30 | EFI_PCI_COMMAND_FAST_BACK_TO_BACK \\r |
| 31 | )\r |
| 32 | \r |
| 33 | //\r |
| 34 | // The PCI Bridge Control register bits owned by PCI Bus driver.\r |
| 35 | // \r |
| 36 | // They should be cleared at the beginning. The other registers\r |
| 37 | // are owned by chipset, we should not touch them.\r |
| 38 | //\r |
| 39 | #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \\r |
| 40 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r |
| 41 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r |
| 42 | EFI_PCI_BRIDGE_CONTROL_VGA_16 | \\r |
| 43 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r |
| 44 | )\r |
| 45 | \r |
| 46 | //\r |
| 47 | // The PCCard Bridge Control register bits owned by PCI Bus driver.\r |
| 48 | // \r |
| 49 | // They should be cleared at the beginning. The other registers\r |
| 50 | // are owned by chipset, we should not touch them.\r |
| 51 | //\r |
| 52 | #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \\r |
| 53 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r |
| 54 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r |
| 55 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r |
| 56 | )\r |
| 57 | \r |
| 58 | \r |
| 59 | #define EFI_GET_REGISTER 1\r |
| 60 | #define EFI_SET_REGISTER 2\r |
| 61 | #define EFI_ENABLE_REGISTER 3\r |
| 62 | #define EFI_DISABLE_REGISTER 4\r |
| 63 | \r |
| 64 | EFI_STATUS\r |
| 65 | PciOperateRegister (\r |
| 66 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 67 | IN UINT16 Command,\r |
| 68 | IN UINT8 Offset,\r |
| 69 | IN UINT8 Operation,\r |
| 70 | OUT UINT16 *PtrCommand\r |
| 71 | )\r |
| 72 | /*++\r |
| 73 | \r |
| 74 | Routine Description:\r |
| 75 | \r |
| 76 | TODO: Add function description\r |
| 77 | \r |
| 78 | Arguments:\r |
| 79 | \r |
| 80 | PciIoDevice - TODO: add argument description\r |
| 81 | Command - TODO: add argument description\r |
| 82 | Offset - TODO: add argument description\r |
| 83 | Operation - TODO: add argument description\r |
| 84 | PtrCommand - TODO: add argument description\r |
| 85 | \r |
| 86 | Returns:\r |
| 87 | \r |
| 88 | TODO: add return values\r |
| 89 | \r |
| 90 | --*/\r |
| 91 | ;\r |
| 92 | \r |
| 93 | BOOLEAN\r |
| 94 | PciCapabilitySupport (\r |
| 95 | IN PCI_IO_DEVICE *PciIoDevice\r |
| 96 | )\r |
| 97 | /*++\r |
| 98 | \r |
| 99 | Routine Description:\r |
| 100 | \r |
| 101 | TODO: Add function description\r |
| 102 | \r |
| 103 | Arguments:\r |
| 104 | \r |
| 105 | PciIoDevice - TODO: add argument description\r |
| 106 | \r |
| 107 | Returns:\r |
| 108 | \r |
| 109 | TODO: add return values\r |
| 110 | \r |
| 111 | --*/\r |
| 112 | ;\r |
| 113 | \r |
| 114 | EFI_STATUS\r |
| 115 | LocateCapabilityRegBlock (\r |
| 116 | IN PCI_IO_DEVICE *PciIoDevice,\r |
| 117 | IN UINT8 CapId,\r |
| 118 | IN OUT UINT8 *Offset,\r |
| 119 | OUT UINT8 *NextRegBlock OPTIONAL\r |
| 120 | )\r |
| 121 | /*++\r |
| 122 | \r |
| 123 | Routine Description:\r |
| 124 | \r |
| 125 | TODO: Add function description\r |
| 126 | \r |
| 127 | Arguments:\r |
| 128 | \r |
| 129 | PciIoDevice - TODO: add argument description\r |
| 130 | CapId - TODO: add argument description\r |
| 131 | Offset - TODO: add argument description\r |
| 132 | NextRegBlock - TODO: add argument description\r |
| 133 | \r |
| 134 | Returns:\r |
| 135 | \r |
| 136 | TODO: add return values\r |
| 137 | \r |
| 138 | --*/\r |
| 139 | ;\r |
| 140 | \r |
| 141 | \r |
| 142 | #define PciReadCommandRegister(a,b) \\r |
| 143 | PciOperateRegister (a,0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r |
| 144 | \r |
| 145 | #define PciSetCommandRegister(a,b) \\r |
| 146 | PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r |
| 147 | \r |
| 148 | #define PciEnableCommandRegister(a,b) \\r |
| 149 | PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r |
| 150 | \r |
| 151 | #define PciDisableCommandRegister(a,b) \\r |
| 152 | PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r |
| 153 | \r |
| 154 | #define PciReadBridgeControlRegister(a,b) \\r |
| 155 | PciOperateRegister (a,0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r |
| 156 | \r |
| 157 | #define PciSetBridgeControlRegister(a,b) \\r |
| 158 | PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r |
| 159 | \r |
| 160 | #define PciEnableBridgeControlRegister(a,b) \\r |
| 161 | PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r |
| 162 | \r |
| 163 | #define PciDisableBridgeControlRegister(a,b) \\r |
| 164 | PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r |
| 165 | \r |
| 166 | #endif\r |
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