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97404058 | 1 | /** @file\r |
8e8227d1 | 2 | PCI bus enumeration logic function declaration for PCI bus module.\r |
ead42efc | 3 | \r |
8e8227d1 | 4 | Copyright (c) 2006 - 2009, Intel Corporation\r |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
ead42efc | 12 | \r |
8e8227d1 | 13 | **/\r |
ead42efc | 14 | \r |
eeefcb9d | 15 | #ifndef _EFI_PCI_ENUMERATOR_H_\r |
16 | #define _EFI_PCI_ENUMERATOR_H_\r | |
ead42efc | 17 | \r |
18 | #include "PciResourceSupport.h"\r | |
19 | \r | |
a3b8e257 | 20 | /**\r |
21 | This routine is used to enumerate entire pci bus system\r | |
8e8227d1 | 22 | in a given platform.\r |
a3b8e257 | 23 | \r |
97404058 | 24 | @param Controller Parent controller handle.\r |
8e8227d1 | 25 | \r |
26 | @retval EFI_SUCCESS PCI enumeration finished successfully.\r | |
27 | @retval other Some error occurred when enumerating the pci bus system.\r | |
28 | \r | |
a3b8e257 | 29 | **/\r |
ead42efc | 30 | EFI_STATUS\r |
31 | PciEnumerator (\r | |
32 | IN EFI_HANDLE Controller\r | |
ed66e1bc | 33 | );\r |
ead42efc | 34 | \r |
a3b8e257 | 35 | /**\r |
8e8227d1 | 36 | Enumerate PCI root bridge.\r |
37 | \r | |
38 | @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r | |
97404058 | 39 | @param RootBridgeDev Instance of root bridge device.\r |
8e8227d1 | 40 | \r |
41 | @retval EFI_SUCCESS Successfully enumerated root bridge.\r | |
42 | @retval other Failed to enumerate root bridge.\r | |
43 | \r | |
a3b8e257 | 44 | **/\r |
ead42efc | 45 | EFI_STATUS\r |
46 | PciRootBridgeEnumerator (\r | |
47 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r | |
48 | IN PCI_IO_DEVICE *RootBridgeDev\r | |
ed66e1bc | 49 | );\r |
ead42efc | 50 | \r |
a3b8e257 | 51 | /**\r |
8e8227d1 | 52 | This routine is used to process all PCI devices' Option Rom\r |
53 | on a certain root bridge.\r | |
54 | \r | |
97404058 | 55 | @param Bridge Given parent's root bridge.\r |
56 | @param RomBase Base address of ROM driver loaded from.\r | |
8e8227d1 | 57 | @param MaxLength Maximum rom size.\r |
58 | \r | |
a3b8e257 | 59 | **/\r |
8e8227d1 | 60 | VOID\r |
ead42efc | 61 | ProcessOptionRom (\r |
62 | IN PCI_IO_DEVICE *Bridge,\r | |
63 | IN UINT64 RomBase,\r | |
64 | IN UINT64 MaxLength\r | |
ed66e1bc | 65 | );\r |
ead42efc | 66 | \r |
a3b8e257 | 67 | /**\r |
68 | This routine is used to assign bus number to the given PCI bus system\r | |
8e8227d1 | 69 | \r |
70 | @param Bridge Parent root bridge instance.\r | |
71 | @param StartBusNumber Number of beginning.\r | |
72 | @param SubBusNumber The number of sub bus.\r | |
73 | \r | |
74 | @retval EFI_SUCCESS Successfully assigned bus number.\r | |
75 | @retval EFI_DEVICE_ERROR Failed to assign bus number.\r | |
76 | \r | |
a3b8e257 | 77 | **/\r |
ead42efc | 78 | EFI_STATUS\r |
79 | PciAssignBusNumber (\r | |
80 | IN PCI_IO_DEVICE *Bridge,\r | |
81 | IN UINT8 StartBusNumber,\r | |
82 | OUT UINT8 *SubBusNumber\r | |
ed66e1bc | 83 | );\r |
ead42efc | 84 | \r |
a3b8e257 | 85 | /**\r |
86 | This routine is used to determine the root bridge attribute by interfacing\r | |
87 | the host bridge resource allocation protocol.\r | |
88 | \r | |
8e8227d1 | 89 | @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r |
90 | @param RootBridgeDev Root bridge instance\r | |
91 | \r | |
92 | @retval EFI_SUCCESS Successfully got root bridge's attribute.\r | |
93 | @retval other Failed to get attribute.\r | |
94 | \r | |
a3b8e257 | 95 | **/\r |
ead42efc | 96 | EFI_STATUS\r |
97 | DetermineRootBridgeAttributes (\r | |
98 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r | |
99 | IN PCI_IO_DEVICE *RootBridgeDev\r | |
ed66e1bc | 100 | );\r |
ead42efc | 101 | \r |
a3b8e257 | 102 | /**\r |
8e8227d1 | 103 | Get Max Option Rom size on specified bridge.\r |
104 | \r | |
105 | @param Bridge Given bridge device instance.\r | |
106 | \r | |
107 | @return Max size of option rom needed.\r | |
108 | \r | |
a3b8e257 | 109 | **/\r |
ead42efc | 110 | UINT64\r |
111 | GetMaxOptionRomSize (\r | |
112 | IN PCI_IO_DEVICE *Bridge\r | |
ed66e1bc | 113 | );\r |
ead42efc | 114 | \r |
a3b8e257 | 115 | /**\r |
116 | Process attributes of devices on this host bridge\r | |
8e8227d1 | 117 | \r |
118 | @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r | |
119 | \r | |
120 | @retval EFI_SUCCESS Successfully process attribute.\r | |
97404058 | 121 | @retval EFI_NOT_FOUND Can not find the specific root bridge device.\r |
8e8227d1 | 122 | @retval other Failed to determine the root bridge device's attribute.\r |
123 | \r | |
a3b8e257 | 124 | **/\r |
ead42efc | 125 | EFI_STATUS\r |
126 | PciHostBridgeDeviceAttribute (\r | |
127 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r | |
ed66e1bc | 128 | );\r |
ead42efc | 129 | \r |
a3b8e257 | 130 | /**\r |
8e8227d1 | 131 | Get resource allocation status from the ACPI resource descriptor.\r |
a3b8e257 | 132 | \r |
97404058 | 133 | @param AcpiConfig Point to Acpi configuration table.\r |
134 | @param IoResStatus Return the status of I/O resource.\r | |
135 | @param Mem32ResStatus Return the status of 32-bit Memory resource.\r | |
8e8227d1 | 136 | @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.\r |
97404058 | 137 | @param Mem64ResStatus Return the status of 64-bit Memory resource.\r |
8e8227d1 | 138 | @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.\r |
139 | \r | |
a3b8e257 | 140 | **/\r |
8e8227d1 | 141 | VOID\r |
ead42efc | 142 | GetResourceAllocationStatus (\r |
143 | VOID *AcpiConfig,\r | |
144 | OUT UINT64 *IoResStatus,\r | |
145 | OUT UINT64 *Mem32ResStatus,\r | |
146 | OUT UINT64 *PMem32ResStatus,\r | |
147 | OUT UINT64 *Mem64ResStatus,\r | |
148 | OUT UINT64 *PMem64ResStatus\r | |
ed66e1bc | 149 | );\r |
ead42efc | 150 | \r |
a3b8e257 | 151 | /**\r |
8e8227d1 | 152 | Remove a PCI device from device pool and mark its bar.\r |
153 | \r | |
97404058 | 154 | @param PciDevice Instance of Pci device.\r |
8e8227d1 | 155 | \r |
156 | @retval EFI_SUCCESS Successfully remove the PCI device.\r | |
157 | @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.\r | |
158 | \r | |
a3b8e257 | 159 | **/\r |
ead42efc | 160 | EFI_STATUS\r |
161 | RejectPciDevice (\r | |
162 | IN PCI_IO_DEVICE *PciDevice\r | |
ed66e1bc | 163 | );\r |
ead42efc | 164 | \r |
a3b8e257 | 165 | /**\r |
8e8227d1 | 166 | Determine whethter a PCI device can be rejected.\r |
167 | \r | |
168 | @param PciResNode Pointer to Pci resource node instance.\r | |
169 | \r | |
170 | @retval TRUE The PCI device can be rejected.\r | |
171 | @retval TRUE The PCI device cannot be rejected.\r | |
172 | \r | |
a3b8e257 | 173 | **/\r |
ead42efc | 174 | BOOLEAN\r |
175 | IsRejectiveDevice (\r | |
176 | IN PCI_RESOURCE_NODE *PciResNode\r | |
ed66e1bc | 177 | );\r |
ead42efc | 178 | \r |
a3b8e257 | 179 | /**\r |
8e8227d1 | 180 | Compare two resource nodes and get the larger resource consumer.\r |
181 | \r | |
182 | @param PciResNode1 resource node 1 want to be compared\r | |
183 | @param PciResNode2 resource node 2 want to be compared\r | |
184 | \r | |
185 | @return Larger resource node.\r | |
186 | \r | |
a3b8e257 | 187 | **/\r |
ead42efc | 188 | PCI_RESOURCE_NODE *\r |
189 | GetLargerConsumerDevice (\r | |
190 | IN PCI_RESOURCE_NODE *PciResNode1,\r | |
191 | IN PCI_RESOURCE_NODE *PciResNode2\r | |
ed66e1bc | 192 | );\r |
ead42efc | 193 | \r |
a3b8e257 | 194 | /**\r |
8e8227d1 | 195 | Get the max resource consumer in the host resource pool.\r |
196 | \r | |
97404058 | 197 | @param ResPool Pointer to resource pool node.\r |
8e8227d1 | 198 | \r |
199 | @return The max resource consumer in the host resource pool.\r | |
200 | \r | |
a3b8e257 | 201 | **/\r |
ead42efc | 202 | PCI_RESOURCE_NODE *\r |
203 | GetMaxResourceConsumerDevice (\r | |
204 | IN PCI_RESOURCE_NODE *ResPool\r | |
ed66e1bc | 205 | );\r |
ead42efc | 206 | \r |
a3b8e257 | 207 | /**\r |
208 | Adjust host bridge allocation so as to reduce resource requirement\r | |
8e8227d1 | 209 | \r |
97404058 | 210 | @param IoPool Pointer to instance of I/O resource Node.\r |
211 | @param Mem32Pool Pointer to instance of 32-bit memory resource Node.\r | |
8e8227d1 | 212 | @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.\r |
97404058 | 213 | @param Mem64Pool Pointer to instance of 64-bit memory resource node.\r |
8e8227d1 | 214 | @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.\r |
97404058 | 215 | @param IoResStatus Status of I/O resource Node.\r |
216 | @param Mem32ResStatus Status of 32-bit memory resource Node.\r | |
8e8227d1 | 217 | @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.\r |
97404058 | 218 | @param Mem64ResStatus Status of 64-bit memory resource node.\r |
8e8227d1 | 219 | @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.\r |
220 | \r | |
221 | @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.\r | |
222 | @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.\r | |
223 | \r | |
a3b8e257 | 224 | **/\r |
ead42efc | 225 | EFI_STATUS\r |
226 | PciHostBridgeAdjustAllocation (\r | |
227 | IN PCI_RESOURCE_NODE *IoPool,\r | |
228 | IN PCI_RESOURCE_NODE *Mem32Pool,\r | |
229 | IN PCI_RESOURCE_NODE *PMem32Pool,\r | |
230 | IN PCI_RESOURCE_NODE *Mem64Pool,\r | |
231 | IN PCI_RESOURCE_NODE *PMem64Pool,\r | |
232 | IN UINT64 IoResStatus,\r | |
233 | IN UINT64 Mem32ResStatus,\r | |
234 | IN UINT64 PMem32ResStatus,\r | |
235 | IN UINT64 Mem64ResStatus,\r | |
236 | IN UINT64 PMem64ResStatus\r | |
ed66e1bc | 237 | );\r |
ead42efc | 238 | \r |
a3b8e257 | 239 | /**\r |
240 | Summary requests for all resource type, and contruct ACPI resource\r | |
241 | requestor instance.\r | |
8e8227d1 | 242 | \r |
243 | @param Bridge detecting bridge\r | |
244 | @param IoNode Pointer to instance of I/O resource Node\r | |
245 | @param Mem32Node Pointer to instance of 32-bit memory resource Node\r | |
246 | @param PMem32Node Pointer to instance of 32-bit Pmemory resource node\r | |
247 | @param Mem64Node Pointer to instance of 64-bit memory resource node\r | |
248 | @param PMem64Node Pointer to instance of 64-bit Pmemory resource node\r | |
249 | @param Config Output buffer holding new constructed APCI resource requestor\r | |
250 | \r | |
251 | @retval EFI_SUCCESS Successfully constructed ACPI resource.\r | |
252 | @retval EFI_OUT_OF_RESOURCES No memory availabe.\r | |
253 | \r | |
a3b8e257 | 254 | **/\r |
ead42efc | 255 | EFI_STATUS\r |
256 | ConstructAcpiResourceRequestor (\r | |
257 | IN PCI_IO_DEVICE *Bridge,\r | |
258 | IN PCI_RESOURCE_NODE *IoNode,\r | |
259 | IN PCI_RESOURCE_NODE *Mem32Node,\r | |
260 | IN PCI_RESOURCE_NODE *PMem32Node,\r | |
261 | IN PCI_RESOURCE_NODE *Mem64Node,\r | |
262 | IN PCI_RESOURCE_NODE *PMem64Node,\r | |
c72216a6 | 263 | OUT VOID **Config\r |
ed66e1bc | 264 | );\r |
ead42efc | 265 | \r |
a3b8e257 | 266 | /**\r |
c72216a6 | 267 | Get resource base from an acpi configuration descriptor.\r |
8e8227d1 | 268 | \r |
269 | @param Config An acpi configuration descriptor.\r | |
270 | @param IoBase Output of I/O resource base address.\r | |
271 | @param Mem32Base Output of 32-bit memory base address.\r | |
272 | @param PMem32Base Output of 32-bit prefetchable memory base address.\r | |
273 | @param Mem64Base Output of 64-bit memory base address.\r | |
274 | @param PMem64Base Output of 64-bit prefetchable memory base address.\r | |
c72216a6 | 275 | \r |
a3b8e257 | 276 | **/\r |
8e8227d1 | 277 | VOID\r |
ead42efc | 278 | GetResourceBase (\r |
c72216a6 | 279 | IN VOID *Config,\r |
ead42efc | 280 | OUT UINT64 *IoBase,\r |
281 | OUT UINT64 *Mem32Base,\r | |
282 | OUT UINT64 *PMem32Base,\r | |
283 | OUT UINT64 *Mem64Base,\r | |
284 | OUT UINT64 *PMem64Base\r | |
ed66e1bc | 285 | );\r |
ead42efc | 286 | \r |
a3b8e257 | 287 | /**\r |
288 | Enumerate pci bridge, allocate resource and determine attribute\r | |
8e8227d1 | 289 | for devices on this bridge.\r |
290 | \r | |
291 | @param BridgeDev Pointer to instance of bridge device.\r | |
292 | \r | |
293 | @retval EFI_SUCCESS Successfully enumerated PCI bridge.\r | |
294 | @retval other Failed to enumerate.\r | |
295 | \r | |
a3b8e257 | 296 | **/\r |
ead42efc | 297 | EFI_STATUS\r |
298 | PciBridgeEnumerator (\r | |
299 | IN PCI_IO_DEVICE *BridgeDev\r | |
ed66e1bc | 300 | );\r |
ead42efc | 301 | \r |
a3b8e257 | 302 | /**\r |
8e8227d1 | 303 | Allocate all kinds of resource for PCI bridge.\r |
304 | \r | |
305 | @param Bridge Pointer to bridge instance.\r | |
306 | \r | |
307 | @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.\r | |
308 | @retval other Failed to allocate resource for bridge.\r | |
309 | \r | |
a3b8e257 | 310 | **/\r |
ead42efc | 311 | EFI_STATUS\r |
312 | PciBridgeResourceAllocator (\r | |
313 | IN PCI_IO_DEVICE *Bridge\r | |
ed66e1bc | 314 | );\r |
ead42efc | 315 | \r |
a3b8e257 | 316 | /**\r |
8e8227d1 | 317 | Get resource base address for a pci bridge device.\r |
318 | \r | |
319 | @param Bridge Given Pci driver instance.\r | |
320 | @param IoBase Output for base address of I/O type resource.\r | |
321 | @param Mem32Base Output for base address of 32-bit memory type resource.\r | |
322 | @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.\r | |
323 | @param Mem64Base Output for base address of 64-bit memory type resource.\r | |
324 | @param PMem64Base Output for base address of 64-bit Pmemory type resource.\r | |
325 | \r | |
326 | @retval EFI_SUCCESS Successfully got resource base address.\r | |
327 | @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.\r | |
328 | \r | |
a3b8e257 | 329 | **/\r |
ead42efc | 330 | EFI_STATUS\r |
331 | GetResourceBaseFromBridge (\r | |
332 | IN PCI_IO_DEVICE *Bridge,\r | |
333 | OUT UINT64 *IoBase,\r | |
334 | OUT UINT64 *Mem32Base,\r | |
335 | OUT UINT64 *PMem32Base,\r | |
336 | OUT UINT64 *Mem64Base,\r | |
337 | OUT UINT64 *PMem64Base\r | |
ed66e1bc | 338 | );\r |
ead42efc | 339 | \r |
a3b8e257 | 340 | /**\r |
341 | Process Option Rom on this host bridge\r | |
8e8227d1 | 342 | \r |
97404058 | 343 | @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r |
8e8227d1 | 344 | \r |
97404058 | 345 | @retval EFI_NOT_FOUND Can not find the root bridge instance.\r |
346 | @retval EFI_SUCCESS Success process.\r | |
a3b8e257 | 347 | **/\r |
ead42efc | 348 | EFI_STATUS\r |
349 | PciHostBridgeP2CProcess (\r | |
350 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r | |
ed66e1bc | 351 | );\r |
ead42efc | 352 | \r |
a3b8e257 | 353 | /**\r |
8e8227d1 | 354 | These are the notifications from the PCI bus driver that it is about to enter a certain\r |
a3b8e257 | 355 | phase of the PCI enumeration process.\r |
356 | \r | |
357 | This member function can be used to notify the host bridge driver to perform specific actions,\r | |
358 | including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r | |
359 | Eight notification points are defined at this time. See belows:\r | |
8e8227d1 | 360 | EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r |
a3b8e257 | 361 | structures. The PCI enumerator should issue this notification\r |
362 | before starting a fresh enumeration process. Enumeration cannot\r | |
363 | be restarted after sending any other notification such as\r | |
364 | EfiPciHostBridgeBeginBusAllocation.\r | |
8e8227d1 | 365 | EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r |
a3b8e257 | 366 | required here. This notification can be used to perform any\r |
367 | chipset-specific programming.\r | |
8e8227d1 | 368 | EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r |
a3b8e257 | 369 | specific action is required here. This notification can be used to\r |
370 | perform any chipset-specific programming.\r | |
8e8227d1 | 371 | EfiPciHostBridgeBeginResourceAllocation\r |
372 | The resource allocation phase is about to begin. No specific\r | |
373 | action is required here. This notification can be used to perform\r | |
374 | any chipset-specific programming.\r | |
375 | EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r | |
a3b8e257 | 376 | root bridges. These resource settings are returned on the next call to\r |
377 | GetProposedResources(). Before calling NotifyPhase() with a Phase of\r | |
8e8227d1 | 378 | EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r |
379 | for gathering I/O and memory requests for\r | |
a3b8e257 | 380 | all the PCI root bridges and submitting these requests using\r |
381 | SubmitResources(). This function pads the resource amount\r | |
382 | to suit the root bridge hardware, takes care of dependencies between\r | |
383 | the PCI root bridges, and calls the Global Coherency Domain (GCD)\r | |
384 | with the allocation request. In the case of padding, the allocated range\r | |
385 | could be bigger than what was requested.\r | |
8e8227d1 | 386 | EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r |
a3b8e257 | 387 | resources (proposed resources) for all the PCI root bridges. After the\r |
388 | hardware is programmed, reassigning resources will not be supported.\r | |
389 | The bus settings are not affected.\r | |
8e8227d1 | 390 | EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r |
a3b8e257 | 391 | root bridges and resets the I/O and memory apertures to their initial\r |
392 | state. The bus settings are not affected. If the request to allocate\r | |
393 | resources fails, the PCI enumerator can use this notification to\r | |
394 | deallocate previous resources, adjust the requests, and retry\r | |
395 | allocation.\r | |
8e8227d1 | 396 | EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r |
a3b8e257 | 397 | required here. This notification can be used to perform any chipsetspecific\r |
398 | programming.\r | |
8e8227d1 | 399 | \r |
97404058 | 400 | @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r |
a3b8e257 | 401 | @param[in] Phase The phase during enumeration\r |
8e8227d1 | 402 | \r |
a3b8e257 | 403 | @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r |
404 | is valid for a Phase of EfiPciHostBridgeAllocateResources if\r | |
405 | SubmitResources() has not been called for one or more\r | |
406 | PCI root bridges before this call\r | |
407 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r | |
408 | for a Phase of EfiPciHostBridgeSetResources.\r | |
409 | @retval EFI_INVALID_PARAMETER Invalid phase parameter\r | |
410 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
411 | This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r | |
412 | previously submitted resource requests cannot be fulfilled or\r | |
413 | were only partially fulfilled.\r | |
414 | @retval EFI_SUCCESS The notification was accepted without any errors.\r | |
ead42efc | 415 | \r |
bcd70414 | 416 | **/\r |
ead42efc | 417 | EFI_STATUS\r |
418 | NotifyPhase (\r | |
419 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,\r | |
420 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r | |
ed66e1bc | 421 | );\r |
ead42efc | 422 | \r |
a3b8e257 | 423 | /**\r |
8e8227d1 | 424 | Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r |
425 | stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r | |
426 | PCI controllers before enumeration.\r | |
427 | \r | |
428 | This function is called during the PCI enumeration process. No specific action is expected from this\r | |
429 | member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r | |
430 | enumeration.\r | |
431 | \r | |
432 | @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r | |
433 | @param Bus The bus number of the pci device.\r | |
434 | @param Device The device number of the pci device.\r | |
435 | @param Func The function number of the pci device.\r | |
436 | @param Phase The phase of the PCI device enumeration.\r | |
437 | \r | |
438 | @retval EFI_SUCCESS The requested parameters were returned.\r | |
439 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r | |
440 | @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r | |
441 | EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r | |
442 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r | |
a3b8e257 | 443 | not enumerate this device, including its child devices if it is a PCI-to-PCI\r |
444 | bridge.\r | |
ead42efc | 445 | \r |
bcd70414 | 446 | **/\r |
ead42efc | 447 | EFI_STATUS\r |
448 | PreprocessController (\r | |
449 | IN PCI_IO_DEVICE *Bridge,\r | |
450 | IN UINT8 Bus,\r | |
451 | IN UINT8 Device,\r | |
452 | IN UINT8 Func,\r | |
453 | IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r | |
ed66e1bc | 454 | );\r |
ead42efc | 455 | \r |
a3b8e257 | 456 | /**\r |
8e8227d1 | 457 | This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has\r |
458 | happened on the hot-plug controller. Currently, the operations include add operation and remove operation..\r | |
459 | \r | |
460 | @param This A pointer to the hot plug request protocol.\r | |
461 | @param Operation The operation the PCI bus driver is requested to make.\r | |
462 | @param Controller The handle of the hot-plug controller.\r | |
463 | @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.\r | |
464 | @param NumberOfChildren The number of child handles.\r | |
465 | For a add operation, it is an output parameter.\r | |
1910fbaf | 466 | For a remove operation, it's an input parameter.\r |
8e8227d1 | 467 | @param ChildHandleBuffer The buffer which contains the child handles.\r |
468 | \r | |
469 | @retval EFI_INVALID_PARAMETER Operation is not a legal value.\r | |
470 | Controller is NULL or not a valid handle.\r | |
471 | NumberOfChildren is NULL.\r | |
472 | ChildHandleBuffer is NULL while Operation is add.\r | |
473 | @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.\r | |
474 | @retval EFI_NOT_FOUND Can not find bridge according to controller handle.\r | |
475 | @retval EFI_SUCCESS The handles for the specified device have been created or destroyed\r | |
476 | as requested, and for an add operation, the new handles are\r | |
477 | returned in ChildHandleBuffer.\r | |
a3b8e257 | 478 | **/\r |
ead42efc | 479 | EFI_STATUS\r |
480 | EFIAPI\r | |
481 | PciHotPlugRequestNotify (\r | |
482 | IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,\r | |
483 | IN EFI_PCI_HOTPLUG_OPERATION Operation,\r | |
484 | IN EFI_HANDLE Controller,\r | |
485 | IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,\r | |
486 | IN OUT UINT8 *NumberOfChildren,\r | |
487 | IN OUT EFI_HANDLE * ChildHandleBuffer\r | |
ed66e1bc | 488 | );\r |
ead42efc | 489 | \r |
a3b8e257 | 490 | /**\r |
491 | Search hostbridge according to given handle\r | |
eeefcb9d | 492 | \r |
8e8227d1 | 493 | @param RootBridgeHandle Host bridge handle.\r |
494 | \r | |
495 | @retval TRUE Found host bridge handle.\r | |
496 | @retval FALSE Not found hot bridge handle.\r | |
497 | \r | |
a3b8e257 | 498 | **/\r |
ead42efc | 499 | BOOLEAN\r |
500 | SearchHostBridgeHandle (\r | |
501 | IN EFI_HANDLE RootBridgeHandle\r | |
ed66e1bc | 502 | );\r |
ead42efc | 503 | \r |
a3b8e257 | 504 | /**\r |
8e8227d1 | 505 | Add host bridge handle to global variable for enumerating.\r |
506 | \r | |
507 | @param HostBridgeHandle Host bridge handle.\r | |
508 | \r | |
509 | @retval EFI_SUCCESS Successfully added host bridge.\r | |
510 | @retval EFI_ABORTED Host bridge is NULL, or given host bridge\r | |
511 | has been in host bridge list.\r | |
512 | \r | |
a3b8e257 | 513 | **/\r |
ead42efc | 514 | EFI_STATUS\r |
515 | AddHostBridgeEnumerator (\r | |
516 | IN EFI_HANDLE HostBridgeHandle\r | |
ed66e1bc | 517 | );\r |
ead42efc | 518 | \r |
519 | #endif\r |