3dbba770 |
1 | /** @file\r |
ead42efc |
2 | \r |
3 | Copyright (c) 2006 - 2007, Intel Corporation\r |
4 | All rights reserved. This program and the accompanying materials\r |
5 | are licensed and made available under the terms and conditions of the BSD License\r |
6 | which accompanies this distribution. The full text of the license may be found at\r |
7 | http://opensource.org/licenses/bsd-license.php\r |
8 | \r |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
11 | \r |
12 | Module Name:\r |
13 | \r |
14 | PciLib.h\r |
15 | \r |
16 | Abstract:\r |
17 | \r |
18 | PCI Bus Driver Lib header file.\r |
19 | Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable\r |
20 | support hot plug.\r |
21 | \r |
22 | Revision History\r |
23 | \r |
3dbba770 |
24 | **/\r |
ead42efc |
25 | \r |
eeefcb9d |
26 | #ifndef _EFI_PCI_LIB_H_\r |
27 | #define _EFI_PCI_LIB_H_\r |
ead42efc |
28 | \r |
29 | //\r |
30 | // Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask\r |
31 | //\r |
32 | #define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01\r |
33 | #define PCI_INCOMPATIBLE_READ_SUPPORT 0x02\r |
34 | #define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04\r |
35 | #define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08\r |
36 | #define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a\r |
37 | \r |
a43264f4 |
38 | typedef struct {\r |
39 | EFI_HANDLE Handle;\r |
40 | } EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;\r |
41 | \r |
42 | typedef struct {\r |
43 | UINT32 Bar;\r |
44 | UINT16 DevicePathSize;\r |
45 | UINT16 ReqResSize;\r |
46 | UINT16 AllocResSize;\r |
47 | UINT8 *DevicePath;\r |
48 | UINT8 *ReqRes;\r |
49 | UINT8 *AllocRes;\r |
50 | } EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;\r |
51 | \r |
57076f45 |
52 | /**\r |
53 | Install protocol gEfiPciHotPlugRequestProtocolGuid\r |
54 | @param Status return status of protocol installation.\r |
55 | **/\r |
97404058 |
56 | VOID\r |
ead42efc |
57 | InstallHotPlugRequestProtocol (\r |
58 | IN EFI_STATUS *Status\r |
ed66e1bc |
59 | );\r |
ead42efc |
60 | \r |
57076f45 |
61 | /**\r |
eeefcb9d |
62 | Retrieve the BAR information via PciIo interface.\r |
57076f45 |
63 | \r |
eeefcb9d |
64 | @param PciIoDevice Pci device instance.\r |
57076f45 |
65 | **/\r |
ead42efc |
66 | VOID\r |
67 | GetBackPcCardBar (\r |
68 | IN PCI_IO_DEVICE *PciIoDevice\r |
ed66e1bc |
69 | );\r |
ead42efc |
70 | \r |
57076f45 |
71 | /**\r |
72 | Remove rejected pci device from specific root bridge\r |
73 | handle.\r |
74 | \r |
eeefcb9d |
75 | @param RootBridgeHandle specific parent root bridge handle.\r |
76 | @param Bridge Bridge device instance.\r |
57076f45 |
77 | \r |
78 | @retval EFI_SUCCESS Success operation.\r |
79 | **/\r |
ead42efc |
80 | EFI_STATUS\r |
81 | RemoveRejectedPciDevices (\r |
82 | EFI_HANDLE RootBridgeHandle,\r |
83 | IN PCI_IO_DEVICE *Bridge\r |
ed66e1bc |
84 | );\r |
ead42efc |
85 | \r |
57076f45 |
86 | /**\r |
87 | Wrapper function for allocating resource for pci host bridge.\r |
88 | \r |
eeefcb9d |
89 | @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r |
57076f45 |
90 | \r |
91 | **/\r |
ead42efc |
92 | EFI_STATUS\r |
93 | PciHostBridgeResourceAllocator (\r |
94 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r |
ed66e1bc |
95 | );\r |
ead42efc |
96 | \r |
eeefcb9d |
97 | /**\r |
98 | Wrapper function for allocating resource for pci host bridge without hotplug device support.\r |
99 | \r |
100 | @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r |
101 | \r |
102 | **/\r |
ead42efc |
103 | EFI_STATUS\r |
104 | PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r |
105 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r |
ed66e1bc |
106 | );\r |
ead42efc |
107 | \r |
eeefcb9d |
108 | /**\r |
109 | Wrapper function for allocating resource for pci host bridge with hotplug device support.\r |
110 | \r |
111 | @param PciResAlloc Point to protocol instance EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r |
112 | \r |
113 | **/\r |
ead42efc |
114 | EFI_STATUS\r |
115 | PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r |
116 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r |
ed66e1bc |
117 | );\r |
ead42efc |
118 | \r |
57076f45 |
119 | /**\r |
120 | Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r |
eeefcb9d |
121 | Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r |
57076f45 |
122 | \r |
eeefcb9d |
123 | @param Bridge Bridge device instance.\r |
124 | @param StartBusNumber start point.\r |
125 | @param SubBusNumber Point to sub bus number.\r |
126 | @param PaddedBusRange Customized bus number.\r |
57076f45 |
127 | \r |
eeefcb9d |
128 | @retval EFI_SUCCESS Success.\r |
129 | @retval EFI_DEVICE_ERROR Fail to scan bus.\r |
57076f45 |
130 | **/\r |
ead42efc |
131 | EFI_STATUS\r |
132 | PciScanBus (\r |
133 | IN PCI_IO_DEVICE *Bridge,\r |
134 | IN UINT8 StartBusNumber,\r |
135 | OUT UINT8 *SubBusNumber,\r |
136 | OUT UINT8 *PaddedBusRange\r |
ed66e1bc |
137 | );\r |
ead42efc |
138 | \r |
eeefcb9d |
139 | /**\r |
140 | Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r |
141 | Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r |
142 | \r |
143 | @param Bridge Bridge device instance.\r |
144 | @param StartBusNumber start point.\r |
145 | @param SubBusNumber Point to sub bus number.\r |
146 | @param PaddedBusRange Customized bus number.\r |
147 | \r |
148 | @retval EFI_SUCCESS Success.\r |
149 | @retval EFI_DEVICE_ERROR Fail to scan bus.\r |
150 | **/\r |
ead42efc |
151 | EFI_STATUS\r |
152 | PciScanBus_WithHotPlugDeviceSupport (\r |
153 | IN PCI_IO_DEVICE *Bridge,\r |
154 | IN UINT8 StartBusNumber,\r |
155 | OUT UINT8 *SubBusNumber,\r |
156 | OUT UINT8 *PaddedBusRange\r |
ed66e1bc |
157 | );\r |
ead42efc |
158 | \r |
eeefcb9d |
159 | /**\r |
160 | Wapper function of scanning pci bus and assign bus number to the given PCI bus system\r |
161 | Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug. \r |
162 | \r |
163 | @param Bridge Bridge device instance.\r |
164 | @param StartBusNumber start point.\r |
165 | @param SubBusNumber Point to sub bus number.\r |
166 | @param PaddedBusRange Customized bus number.\r |
167 | \r |
168 | @retval EFI_SUCCESS Success.\r |
169 | @retval EFI_DEVICE_ERROR Fail to scan bus.\r |
170 | **/\r |
ead42efc |
171 | EFI_STATUS\r |
172 | PciScanBus_WithoutHotPlugDeviceSupport (\r |
173 | IN PCI_IO_DEVICE *Bridge,\r |
174 | IN UINT8 StartBusNumber,\r |
175 | OUT UINT8 *SubBusNumber,\r |
176 | OUT UINT8 *PaddedBusRange\r |
ed66e1bc |
177 | );\r |
ead42efc |
178 | \r |
57076f45 |
179 | /**\r |
eeefcb9d |
180 | Process Option Rom on this host bridge.\r |
57076f45 |
181 | \r |
eeefcb9d |
182 | @param Bridge Pci bridge device instance.\r |
57076f45 |
183 | \r |
eeefcb9d |
184 | @retval EFI_SUCCESS Success.\r |
57076f45 |
185 | **/\r |
ead42efc |
186 | EFI_STATUS\r |
187 | PciRootBridgeP2CProcess (\r |
188 | IN PCI_IO_DEVICE *Bridge\r |
ed66e1bc |
189 | );\r |
ead42efc |
190 | \r |
57076f45 |
191 | /**\r |
eeefcb9d |
192 | Process Option Rom on this host bridge.\r |
57076f45 |
193 | \r |
eeefcb9d |
194 | @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r |
57076f45 |
195 | \r |
eeefcb9d |
196 | @retval EFI_NOT_FOUND Can not find the root bridge instance.\r |
197 | @retval EFI_SUCCESS Success process.\r |
57076f45 |
198 | **/\r |
ead42efc |
199 | EFI_STATUS\r |
200 | PciHostBridgeP2CProcess (\r |
201 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r |
ed66e1bc |
202 | );\r |
ead42efc |
203 | \r |
57076f45 |
204 | /**\r |
205 | This function is used to enumerate the entire host bridge\r |
eeefcb9d |
206 | in a given platform.\r |
ead42efc |
207 | \r |
57076f45 |
208 | @param PciResAlloc A pointer to the resource allocate protocol.\r |
ead42efc |
209 | \r |
eeefcb9d |
210 | @retval EFI_OUT_OF_RESOURCES no enough resource.\r |
211 | @retval EFI_SUCCESS Success.\r |
ead42efc |
212 | \r |
bcd70414 |
213 | **/\r |
ead42efc |
214 | EFI_STATUS\r |
215 | PciHostBridgeEnumerator (\r |
216 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r |
ed66e1bc |
217 | );\r |
ead42efc |
218 | \r |
219 | /**\r |
220 | Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r |
221 | \r |
222 | @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r |
223 | @param Width Signifies the width of the memory operations.\r |
eeefcb9d |
224 | @param Address The address within the PCI configuration space for the PCI controller.\r |
225 | @param Count The number of unit to be read.\r |
ead42efc |
226 | @param Buffer For read operations, the destination buffer to store the results. For\r |
227 | write operations, the source buffer to write data from.\r |
228 | \r |
229 | @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r |
230 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r |
231 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r |
232 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
233 | \r |
234 | **/\r |
235 | EFI_STATUS\r |
236 | PciIoRead (\r |
237 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
238 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
239 | IN UINT32 Address,\r |
240 | IN UINTN Count,\r |
241 | IN OUT VOID *Buffer\r |
242 | );\r |
243 | \r |
244 | /**\r |
245 | Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r |
246 | \r |
247 | @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r |
248 | @param Width Signifies the width of the memory operations.\r |
eeefcb9d |
249 | @param Address The address within the PCI configuration space for the PCI controller.\r |
250 | @param Count The number of unit to be write.\r |
ead42efc |
251 | @param Buffer For read operations, the destination buffer to store the results. For\r |
252 | write operations, the source buffer to write data from.\r |
253 | \r |
254 | @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r |
255 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r |
256 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r |
257 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
258 | \r |
259 | **/\r |
260 | EFI_STATUS\r |
261 | PciIoWrite (\r |
262 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r |
263 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r |
264 | IN UINT32 Address,\r |
265 | IN UINTN Count,\r |
266 | IN OUT VOID *Buffer\r |
267 | );\r |
268 | \r |
269 | /**\r |
270 | Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r |
271 | \r |
272 | @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r |
273 | @param Pci A pointer to PCI_TYPE00.\r |
274 | @param Width Signifies the width of the memory operations.\r |
eeefcb9d |
275 | @param Address The address within the PCI configuration space for the PCI controller.\r |
276 | @param Count The number of unit to be write.\r |
ead42efc |
277 | @param Buffer For read operations, the destination buffer to store the results. For\r |
278 | write operations, the source buffer to write data from.\r |
279 | \r |
280 | @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r |
281 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r |
282 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r |
283 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
284 | \r |
285 | **/\r |
286 | EFI_STATUS\r |
287 | PciRootBridgeIoWrite (\r |
288 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r |
289 | IN PCI_TYPE00 *Pci,\r |
290 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r |
291 | IN UINT64 Address,\r |
292 | IN UINTN Count,\r |
293 | IN OUT VOID *Buffer\r |
294 | );\r |
295 | \r |
296 | /**\r |
297 | Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r |
298 | \r |
299 | @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r |
300 | @param Pci A pointer to PCI_TYPE00.\r |
301 | @param Width Signifies the width of the memory operations.\r |
eeefcb9d |
302 | @param Address The address within the PCI configuration space for the PCI controller.\r |
303 | @param Count The number of unit to be read.\r |
ead42efc |
304 | @param Buffer For read operations, the destination buffer to store the results. For\r |
305 | write operations, the source buffer to write data from.\r |
306 | \r |
307 | @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r |
308 | @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r |
309 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r |
310 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
311 | \r |
312 | **/\r |
313 | EFI_STATUS\r |
314 | PciRootBridgeIoRead (\r |
315 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r |
eeefcb9d |
316 | IN PCI_TYPE00 *Pci, OPTIONAL\r |
ead42efc |
317 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r |
318 | IN UINT64 Address,\r |
319 | IN UINTN Count,\r |
320 | IN OUT VOID *Buffer\r |
321 | );\r |
322 | #endif\r |