fixed one typo.

[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciLib.h

/** @file\r
  Internal library declaration for PCI Bus module.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_PCI_LIB_H_\r
#define _EFI_PCI_LIB_H_\r
\r
//\r
// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask\r
//\r
#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT         0x01\r
#define PCI_INCOMPATIBLE_READ_SUPPORT                  0x02\r
#define PCI_INCOMPATIBLE_WRITE_SUPPORT                 0x04\r
#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT       0x08\r
#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT          0x10\r
\r
typedef struct {\r
  EFI_HANDLE            Handle;\r
} EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;\r
\r
typedef struct {\r
  UINT32                             Bar;\r
  UINT16                             DevicePathSize;\r
  UINT16                             ReqResSize;\r
  UINT16                             AllocResSize;\r
  UINT8                              *DevicePath;\r
  UINT8                              *ReqRes;\r
  UINT8                              *AllocRes;\r
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;\r
\r
\r
/**\r
  Retrieve the PCI Card device BAR information via PciIo interface.\r
\r
  @param PciIoDevice        PCI Card device instance.\r
\r
**/\r
VOID\r
GetBackPcCardBar (\r
  IN  PCI_IO_DEVICE                  *PciIoDevice\r
  );\r
\r
/**\r
  Remove rejected pci device from specific root bridge\r
  handle.\r
\r
  @param RootBridgeHandle  Specific parent root bridge handle.\r
  @param Bridge            Bridge device instance.\r
\r
**/\r
VOID\r
RemoveRejectedPciDevices (\r
  IN EFI_HANDLE        RootBridgeHandle,\r
  IN PCI_IO_DEVICE     *Bridge\r
  );\r
\r
/**\r
  Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
\r
  @param PciResAlloc  Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
\r
  @retval EFI_SUCCESS           Successfully finished resource allocation.\r
  @retval EFI_NOT_FOUND         Cannot get root bridge instance.\r
  @retval EFI_OUT_OF_RESOURCES  Platform failed to program the resources if no hot plug supported.\r
  @retval other                 Some error occurred when allocating resources for the PCI Host Bridge.\r
\r
  @note   Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeResourceAllocator (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
  );\r
\r
/**\r
  Scan pci bus and assign bus number to the given PCI bus system.\r
\r
  @param  Bridge           Bridge device instance.\r
  @param  StartBusNumber   start point.\r
  @param  SubBusNumber     Point to sub bus number.\r
  @param  PaddedBusRange   Customized bus number.\r
\r
  @retval EFI_SUCCESS      Successfully scanned and assigned bus number.\r
  @retval other            Some error occurred when scanning pci bus.\r
\r
  @note   Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
\r
**/\r
EFI_STATUS\r
PciScanBus (\r
  IN PCI_IO_DEVICE                      *Bridge,\r
  IN UINT8                              StartBusNumber,\r
  OUT UINT8                             *SubBusNumber,\r
  OUT UINT8                             *PaddedBusRange\r
  );\r
\r
/**\r
  Process Option Rom on the specified root bridge.\r
\r
  @param Bridge  Pci root bridge device instance.\r
\r
  @retval EFI_SUCCESS   Success process.\r
  @retval other         Some error occurred when processing Option Rom on the root bridge.\r
\r
**/\r
EFI_STATUS\r
PciRootBridgeP2CProcess (\r
  IN PCI_IO_DEVICE *Bridge\r
  );\r
\r
/**\r
  Process Option Rom on the specified host bridge.\r
\r
  @param PciResAlloc    Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
\r
  @retval EFI_SUCCESS   Success process.\r
  @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
  @retval other         Some error occurred when processing Option Rom on the host bridge.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeP2CProcess (\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
  );\r
\r
/**\r
  This function is used to enumerate the entire host bridge\r
  in a given platform.\r
\r
  @param PciResAlloc   A pointer to the PCI Host Resource Allocation protocol.\r
\r
  @retval EFI_SUCCESS            Successfully enumerated the host bridge.\r
  @retval EFI_OUT_OF_RESOURCES   No enough memory available.\r
  @retval other                  Some error occurred when enumerating the host bridge.\r
\r
**/\r
EFI_STATUS\r
PciHostBridgeEnumerator (\r
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc\r
  );\r
\r
/**\r
  Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
\r
  @param  PciIo               A pointer to the EFI_PCI_O_PROTOCOL.\r
  @param  Width               Signifies the width of the memory operations.\r
  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r
  @param  Count               The number of unit to be read.\r
  @param  Buffer              For read operations, the destination buffer to store the results. For\r
                              write operations, the source buffer to write data from.\r
\r
  @retval EFI_SUCCESS           The data was read from or written to the PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not\r
                                valid for the PCI configuration header of the PCI controller.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
PciIoRead (\r
  IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
  IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r
  IN       UINT32                                 Offset,\r
  IN       UINTN                                  Count,\r
  IN OUT   VOID                                   *Buffer\r
  );\r
\r
/**\r
  Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
\r
  If PCI incompatibility check is enabled, do incompatibility check.\r
\r
  @param  PciIo                 A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  Offset                The offset within the PCI configuration space for the PCI controller.\r
  @param  Count                 The number of PCI configuration operations to perform.\r
  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
                                operations, the source buffer to write data from.\r
\r
  @retval EFI_SUCCESS           The data was read from or written to the PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not\r
                                valid for the PCI configuration header of the PCI controller.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
PciIoWrite (\r
  IN       EFI_PCI_IO_PROTOCOL                    *PciIo,\r
  IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,\r
  IN       UINT32                                 Offset,\r
  IN       UINTN                                  Count,\r
  IN OUT   VOID                                   *Buffer\r
  );\r
\r
/**\r
  Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
\r
  @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Pci                 A pointer to PCI_TYPE00.\r
  @param  Width               Signifies the width of the memory operations.\r
  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r
  @param  Count               The number of unit to be read.\r
  @param  Buffer              For read operations, the destination buffer to store the results. For\r
                              write operations, the source buffer to write data from.\r
\r
  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
PciRootBridgeIoWrite (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
  IN       PCI_TYPE00                             *Pci,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN       UINT64                                 Offset,\r
  IN       UINTN                                  Count,\r
  IN OUT   VOID                                   *Buffer\r
  );\r
\r
/**\r
  Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
\r
  @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param  Pci                 A pointer to PCI_TYPE00.\r
  @param  Width               Signifies the width of the memory operations.\r
  @param  Offset              The offset within the PCI configuration space for the PCI controller.\r
  @param  Count               The number of unit to be read.\r
  @param  Buffer              For read operations, the destination buffer to store the results. For\r
                              write operations, the source buffer to write data from.\r
\r
  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
PciRootBridgeIoRead (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,\r
  IN       PCI_TYPE00                             *Pci,            OPTIONAL\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN       UINT64                                 Offset,\r
  IN       UINTN                                  Count,\r
  IN OUT   VOID                                   *Buffer\r
  );\r
\r
#endif\r