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03df1608 | 1 | /** @file |
e3e7f36a | 2 | The header file provides interface definitions exposed by CSM (Compatible Support Module).\r |
3 | \r | |
4 | The CSM provides compatibility support between the Framework and traditional, legacy BIOS code \r | |
5 | and allows booting a traditional OS or booting an EFI OS off a device that requires a traditional \r | |
6 | option ROM (OpROM). \r | |
03df1608 | 7 | |
e3e7f36a | 8 | These definitions are from Compatibility Support Module Spec Version 0.97.\r |
9 | ||
8d129536 | 10 | Copyright (c) 2007-2009, Intel Corporation |
11 | All rights reserved. This program and the accompanying materials | |
12 | are licensed and made available under the terms and conditions of the BSD License | |
13 | which accompanies this distribution. The full text of the license may be found at | |
14 | http://opensource.org/licenses/bsd-license.php | |
15 | ||
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
17 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
18 | ||
64419615 | 19 | @par Revision Reference: |
20 | These definitions are from Compatibility Support Module Spec | |
21 | Version 0.97. | |
22 | ||
8d129536 | 23 | **/ |
24 | ||
25 | #ifndef _FRAMEWORK_LEGACY_16_H_ | |
26 | #define _FRAMEWORK_LEGACY_16_H_ | |
27 | ||
8d129536 | 28 | #pragma pack(1) |
29 | ||
30 | typedef UINT8 SERIAL_MODE; | |
31 | typedef UINT8 PARALLEL_MODE; | |
32 | ||
33 | #define EFI_COMPATIBILITY16_TABLE_SIGNATURE SIGNATURE_32 ('I', 'F', 'E', '$') | |
34 | ||
03df1608 | 35 | /// |
e3e7f36a | 36 | /// There is a table located within the traditional BIOS in either the 0xF000:xxxx or 0xE000:xxxx\r |
37 | /// physical address range. It is located on a 16-byte boundary and provides the physical address of the\r | |
38 | /// entry point for the Compatibility16 functions. These functions provide the platform-specific\r | |
39 | /// information that is required by the generic EfiCompatibility code. The functions are invoked via\r | |
40 | /// thunking by using EFI_LEGACY_BIOS_PROTOCOL.FarCall86() with the 32-bit physical\r | |
41 | /// entry point.\r | |
42 | /// | |
03df1608 | 43 | typedef struct { |
e3e7f36a | 44 | ///\r |
45 | /// The string "$EFI" denotes the start of the EfiCompatibility table. Byte 0 is "I," byte\r | |
46 | /// 1 is "F," byte 2 is "E," and byte 3 is "$" and is normally accessed as a DWORD or UINT32.\r | |
47 | /// | |
03df1608 | 48 | UINT32 Signature; |
e3e7f36a | 49 | \r |
50 | ///\r | |
51 | /// The value required such that byte checksum of TableLength equals zero.\r | |
52 | /// | |
03df1608 | 53 | UINT8 TableChecksum; |
e3e7f36a | 54 | \r |
55 | ///\r | |
56 | /// The length of this table.\r | |
57 | /// | |
03df1608 | 58 | UINT8 TableLength; |
e3e7f36a | 59 | \r |
60 | ///\r | |
61 | /// The major EFI revision for which this table was generated.\r | |
62 | /// | |
03df1608 | 63 | UINT8 EfiMajorRevision; |
e3e7f36a | 64 | \r |
65 | ///\r | |
66 | /// The minor EFI revision for which this table was generated.\r | |
67 | /// | |
03df1608 | 68 | UINT8 EfiMinorRevision; |
e3e7f36a | 69 | \r |
70 | ///\r | |
71 | /// The major revision of this table.\r | |
72 | /// | |
03df1608 | 73 | UINT8 TableMajorRevision; |
e3e7f36a | 74 | \r |
75 | ///\r | |
76 | /// The minor revision of this table.\r | |
77 | /// | |
03df1608 | 78 | UINT8 TableMinorRevision; |
e3e7f36a | 79 | \r |
80 | ///\r | |
81 | /// Reserved for future usage.\r | |
82 | /// | |
03df1608 | 83 | UINT16 Reserved; |
e3e7f36a | 84 | \r |
85 | ///\r | |
86 | /// The segment of the entry point within the traditional BIOS for Compatibility16 functions.\r | |
87 | /// | |
03df1608 | 88 | UINT16 Compatibility16CallSegment; |
e3e7f36a | 89 | \r |
90 | ///\r | |
91 | /// The offset of the entry point within the traditional BIOS for Compatibility16 functions.\r | |
92 | /// | |
03df1608 | 93 | UINT16 Compatibility16CallOffset; |
e3e7f36a | 94 | \r |
95 | ///\r | |
96 | /// The segment of the entry point within the traditional BIOS for EfiCompatibility to invoke the PnP installation check.\r | |
97 | /// | |
03df1608 | 98 | UINT16 PnPInstallationCheckSegment; |
e3e7f36a | 99 | \r |
100 | ///\r | |
101 | /// The Offset of the entry point within the traditional BIOS for EfiCompatibility to invoke the PnP installation check.\r | |
102 | /// | |
03df1608 | 103 | UINT16 PnPInstallationCheckOffset; |
e3e7f36a | 104 | \r |
105 | ///\r | |
106 | /// EFI system resources table. Type EFI_SYSTEM_TABLE is defined in the IntelPlatform Innovation Framework for EFI \r | |
107 | /// Driver Execution Environment Core Interface Specification (DXE CIS).\r | |
108 | /// | |
109 | UINT32 EfiSystemTable; \r | |
110 | \r | |
111 | ///\r | |
112 | /// The address of an OEM-provided identifier string. The string is null terminated.\r | |
113 | /// | |
03df1608 | 114 | UINT32 OemIdStringPointer; |
e3e7f36a | 115 | \r |
116 | ///\r | |
117 | /// The 32-bit physical address where ACPI RSD PTR is stored within the traditional\r | |
118 | /// BIOS. The remained of the ACPI tables are located at their EFI addresses. The size\r | |
119 | /// reserved is the maximum for ACPI 2.0. The EfiCompatibility will fill in the ACPI\r | |
120 | /// RSD PTR with either the ACPI 1.0b or 2.0 values.\r | |
121 | /// | |
03df1608 | 122 | UINT32 AcpiRsdPtrPointer; |
e3e7f36a | 123 | \r |
124 | ///\r | |
125 | /// The OEM revision number. Usage is undefined but provided for OEM module usage.\r | |
126 | /// | |
03df1608 | 127 | UINT16 OemRevision; |
e3e7f36a | 128 | \r |
129 | ///\r | |
130 | /// The 32-bit physical address where INT15 E820 data is stored within the traditional\r | |
131 | /// BIOS. The EfiCompatibility code will fill in the E820Pointer value and copy the\r | |
132 | /// data to the indicated area.\r | |
133 | /// | |
03df1608 | 134 | UINT32 E820Pointer; |
e3e7f36a | 135 | \r |
136 | ///\r | |
137 | /// The length of the E820 data and is filled in by the EfiCompatibility code.\r | |
138 | /// | |
03df1608 | 139 | UINT32 E820Length; |
e3e7f36a | 140 | \r |
141 | ///\r | |
142 | /// The 32-bit physical address where the $PIR table is stored in the traditional BIOS.\r | |
143 | /// The EfiCompatibility code will fill in the IrqRoutingTablePointer value and\r | |
144 | /// copy the data to the indicated area.\r | |
145 | /// | |
03df1608 | 146 | UINT32 IrqRoutingTablePointer; |
e3e7f36a | 147 | \r |
148 | ///\r | |
149 | /// The length of the $PIR table and is filled in by the EfiCompatibility code.\r | |
150 | /// | |
03df1608 | 151 | UINT32 IrqRoutingTableLength; |
e3e7f36a | 152 | \r |
153 | ///\r | |
154 | /// The 32-bit physical address where the MP table is stored in the traditional BIOS.\r | |
155 | /// The EfiCompatibility code will fill in the MpTablePtr value and copy the data to the indicated area.\r | |
156 | /// | |
03df1608 | 157 | UINT32 MpTablePtr; |
e3e7f36a | 158 | \r |
159 | ///\r | |
160 | /// The length of the MP table and is filled in by the EfiCompatibility code.\r | |
161 | /// | |
03df1608 | 162 | UINT32 MpTableLength; |
e3e7f36a | 163 | \r |
164 | ///\r | |
8d303ef3 | 165 | /// The segment of the OEM-specific INT table/code.\r |
e3e7f36a | 166 | /// |
03df1608 | 167 | UINT16 OemIntSegment; |
e3e7f36a | 168 | \r |
169 | ///\r | |
8d303ef3 | 170 | /// The offset of the OEM-specific INT table/code.\r |
e3e7f36a | 171 | /// |
03df1608 | 172 | UINT16 OemIntOffset; |
e3e7f36a | 173 | \r |
174 | ///\r | |
175 | /// The segment of the OEM-specific 32-bit table/code.\r | |
176 | /// | |
03df1608 | 177 | UINT16 Oem32Segment; |
e3e7f36a | 178 | \r |
179 | ///\r | |
180 | /// The offset of the OEM-specific 32-bit table/code.\r | |
181 | /// | |
03df1608 | 182 | UINT16 Oem32Offset; |
8d303ef3 | 183 | \r |
184 | ///\r | |
185 | /// The segment of the OEM-specific 16-bit table/code.\r | |
186 | /// | |
03df1608 | 187 | UINT16 Oem16Segment; |
8d303ef3 | 188 | \r |
189 | ///\r | |
190 | /// The offset of the OEM-specific 16-bit table/code.\r | |
191 | /// | |
03df1608 | 192 | UINT16 Oem16Offset; |
8d303ef3 | 193 | \r |
194 | ///\r | |
195 | /// The segment of the TPM binary passed to 16-bit CSM.\r | |
196 | /// | |
03df1608 | 197 | UINT16 TpmSegment; |
8d303ef3 | 198 | \r |
199 | ///\r | |
200 | /// The offset of the TPM binary passed to 16-bit CSM.\r | |
201 | /// | |
03df1608 | 202 | UINT16 TpmOffset; |
e3e7f36a | 203 | \r |
204 | ///\r | |
205 | /// A pointer to a string identifying the independent BIOS vendor.\r | |
206 | /// | |
03df1608 | 207 | UINT32 IbvPointer; |
8d303ef3 | 208 | \r |
209 | ///\r | |
210 | /// This field is NULL for all systems not supporting PCI Express. This field is the base\r | |
211 | /// value of the start of the PCI Express memory-mapped configuration registers and\r | |
212 | /// must be filled in prior to EfiCompatibility code issuing the Compatibility16 function\r | |
213 | /// Compatibility16InitializeYourself().\r | |
214 | /// Compatibility16InitializeYourself() is defined in Compatability16\r | |
215 | /// Functions.\r | |
216 | /// | |
03df1608 | 217 | UINT32 PciExpressBase; |
8d303ef3 | 218 | \r |
219 | ///\r | |
220 | /// Maximum PCI bus number assigned.\r | |
221 | /// | |
8d129536 | 222 | UINT8 LastPciBus; |
223 | } EFI_COMPATIBILITY16_TABLE; | |
224 | ||
225 | /// | |
e3e7f36a | 226 | /// Functions provided by the CSM binary which communicate between the EfiCompatibility \r |
64419615 | 227 | /// and Compatability16 code.\r |
228 | ///\r | |
229 | /// Inconsistent with specification here: \r | |
230 | /// The member's name started with "Compatibility16" [defined in Intel Framework Compatibility Support Module Specification / 0.97 version] \r | |
231 | /// has been changed to "Legacy16" since keeping backward compatible.\r | |
232 | ///\r | |
03df1608 | 233 | typedef enum { |
e3e7f36a | 234 | ///\r |
235 | /// Causes the Compatibility16 code to do any internal initialization required.\r | |
236 | /// Input:\r | |
237 | /// AX = Compatibility16InitializeYourself\r | |
238 | /// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_INIT_TABLE\r | |
239 | /// Return:\r | |
240 | /// AX = Return Status codes\r | |
64419615 | 241 | ///\r |
242 | Legacy16InitializeYourself = 0x0000, | |
e3e7f36a | 243 | \r |
244 | ///\r | |
245 | /// Causes the Compatibility16 BIOS to perform any drive number translations to match the boot sequence.\r | |
246 | /// Input:\r | |
247 | /// AX = Compatibility16UpdateBbs\r | |
248 | /// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE\r | |
249 | /// Return:\r | |
250 | /// AX = Returned status codes\r | |
251 | /// | |
64419615 | 252 | Legacy16UpdateBbs = 0x0001, |
e3e7f36a | 253 | \r |
254 | ///\r | |
255 | /// Allows the Compatibility16 code to perform any final actions before booting. The Compatibility16\r | |
256 | /// code is read/write.\r | |
257 | /// Input:\r | |
258 | /// AX = Compatibility16PrepareToBoot\r | |
259 | /// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE structure \r | |
260 | /// Return:\r | |
261 | /// AX = Returned status codes\r | |
262 | /// | |
64419615 | 263 | Legacy16PrepareToBoot = 0x0002, |
e3e7f36a | 264 | \r |
265 | ///\r | |
266 | /// Causes the Compatibility16 BIOS to boot. The Compatibility16 code is Read/Only.\r | |
267 | /// Input:\r | |
268 | /// AX = Compatibility16Boot\r | |
269 | /// Output:\r | |
270 | /// AX = Returned status codes\r | |
271 | /// | |
64419615 | 272 | Legacy16Boot = 0x0003, |
e3e7f36a | 273 | \r |
274 | ///\r | |
275 | /// Allows the Compatibility16 code to get the last device from which a boot was attempted. This is\r | |
276 | /// stored in CMOS and is the priority number of the last attempted boot device.\r | |
277 | /// Input:\r | |
278 | /// AX = Compatibility16RetrieveLastBootDevice\r | |
279 | /// Output:\r | |
280 | /// AX = Returned status codes\r | |
281 | /// BX = Priority number of the boot device.\r | |
282 | /// | |
64419615 | 283 | Legacy16RetrieveLastBootDevice = 0x0004, |
e3e7f36a | 284 | \r |
285 | ///\r | |
286 | /// Allows the Compatibility16 code rehook INT13, INT18, and/or INT19 after dispatching a legacy OpROM.\r | |
287 | /// Input:\r | |
288 | /// AX = Compatibility16DispatchOprom\r | |
289 | /// ES:BX = Pointer to EFI_DISPATCH_OPROM_TABLE\r | |
290 | /// Output:\r | |
291 | /// AX = Returned status codes\r | |
292 | /// BX = Number of non-BBS-compliant devices found. Equals 0 if BBS compliant.\r | |
293 | /// | |
64419615 | 294 | Legacy16DispatchOprom = 0x0005, |
e3e7f36a | 295 | \r |
296 | ///\r | |
297 | /// Finds a free area in the 0xFxxxx or 0xExxxx region of the specified length and returns the address\r | |
298 | /// of that region.\r | |
299 | /// Input:\r | |
300 | /// AX = Compatibility16GetTableAddress\r | |
301 | /// BX = Allocation region\r | |
302 | /// 00 = Allocate from either 0xE0000 or 0xF0000 64 KB blocks.\r | |
303 | /// Bit 0 = 1 Allocate from 0xF0000 64 KB block\r | |
304 | /// Bit 1 = 1 Allocate from 0xE0000 64 KB block\r | |
305 | /// CX = Requested length in bytes.\r | |
306 | /// DX = Required address alignment. Bit mapped. First non-zero bit from the right is the alignment.\r | |
307 | /// Output:\r | |
308 | /// AX = Returned status codes\r | |
309 | /// DS:BX = Address of the region\r | |
310 | /// | |
64419615 | 311 | Legacy16GetTableAddress = 0x0006, |
e3e7f36a | 312 | \r |
313 | ///\r | |
314 | /// Enables the EfiCompatibility module to do any nonstandard processing of keyboard LEDs or state.\r | |
315 | /// Input:\r | |
316 | /// AX = Compatibility16SetKeyboardLeds\r | |
317 | /// CL = LED status.\r | |
e02a0e92 | 318 | /// Bit 0 Scroll Lock 0 = Off\r |
319 | /// Bit 1 NumLock\r | |
320 | /// Bit 2 Caps Lock\r | |
e3e7f36a | 321 | /// Output:\r |
322 | /// AX = Returned status codes\r | |
323 | /// | |
64419615 | 324 | Legacy16SetKeyboardLeds = 0x0007, |
e3e7f36a | 325 | \r |
326 | ///\r | |
327 | /// Enables the EfiCompatibility module to install an interrupt handler for PCI mass media devices that\r | |
328 | /// do not have an OpROM associated with them. An example is SATA.\r | |
329 | /// Input:\r | |
330 | /// AX = Compatibility16InstallPciHandler\r | |
331 | /// ES:BX = Pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure\r | |
332 | /// Output:\r | |
333 | /// AX = Returned status codes\r | |
334 | /// | |
64419615 | 335 | Legacy16InstallPciHandler = 0x0008 |
8d129536 | 336 | } EFI_COMPATIBILITY_FUNCTIONS; |
337 | ||
338 | ||
339 | /// | |
340 | /// EFI_DISPATCH_OPROM_TABLE | |
341 | /// | |
342 | typedef struct { | |
e3e7f36a | 343 | UINT16 PnPInstallationCheckSegment; ///< Pointer to the PnpInstallationCheck data structure. |
344 | UINT16 PnPInstallationCheckOffset; ///< Pointer to the PnpInstallationCheck data structure. | |
345 | UINT16 OpromSegment; ///< The segment where the OpROM was placed. Offset is assumed to be 3. | |
346 | UINT8 PciBus; ///< The PCI bus. | |
347 | UINT8 PciDeviceFunction; ///< The PCI device * 0x08 | PCI function. | |
03df1608 | 348 | UINT8 NumberBbsEntries; ///< The number of valid BBS table entries upon entry and exit. The IBV code may |
349 | ///< increase this number, if BBS-compliant devices also hook INTs in order to force the | |
e3e7f36a | 350 | ///< OpROM BIOS Setup to be executed. |
8d303ef3 | 351 | VOID *BbsTablePointer; ///< Pointer to the BBS table. |
64419615 | 352 | UINT16 RuntimeSegment; ///< The segment where the OpROM can be relocated to. If this value is 0x0000, this |
353 | ///< means that the relocation of this run time code is not supported.\r | |
354 | ///< Inconsistent with specification here: \r | |
355 | ///< The member's name "OpromDestinationSegment" [defined in Intel Framework Compatibility Support Module Specification / 0.97 version] \r | |
356 | ///< has been changed to "RuntimeSegment" since keeping backward compatible.\r | |
357 | ||
8d129536 | 358 | } EFI_DISPATCH_OPROM_TABLE; |
359 | ||
360 | /// | |
361 | /// EFI_TO_COMPATIBILITY16_INIT_TABLE | |
362 | /// | |
03df1608 | 363 | typedef struct { |
e3e7f36a | 364 | ///\r |
365 | /// Starting address of memory under 1 MB. The ending address is assumed to be 640 KB or 0x9FFFF.\r | |
366 | /// | |
03df1608 | 367 | UINT32 BiosLessThan1MB; |
e3e7f36a | 368 | \r |
369 | ///\r | |
370 | /// Starting address of the high memory block.\r | |
371 | /// | |
03df1608 | 372 | UINT32 HiPmmMemory; |
e3e7f36a | 373 | \r |
374 | ///\r | |
375 | /// Length of high memory block.\r | |
376 | /// | |
03df1608 | 377 | UINT32 HiPmmMemorySizeInBytes; |
e3e7f36a | 378 | \r |
379 | ///\r | |
380 | /// The segment of the reverse thunk call code.\r | |
381 | /// | |
03df1608 | 382 | UINT16 ReverseThunkCallSegment; |
e3e7f36a | 383 | \r |
384 | ///\r | |
385 | /// The offset of the reverse thunk call code.\r | |
386 | /// | |
03df1608 | 387 | UINT16 ReverseThunkCallOffset; |
e3e7f36a | 388 | \r |
389 | ///\r | |
390 | /// The number of E820 entries copied to the Compatibility16 BIOS.\r | |
391 | /// | |
03df1608 | 392 | UINT32 NumberE820Entries; |
e3e7f36a | 393 | \r |
394 | ///\r | |
395 | /// The amount of usable memory above 1 MB, e.g., E820 type 1 memory.\r | |
396 | /// | |
03df1608 | 397 | UINT32 OsMemoryAbove1Mb; |
e3e7f36a | 398 | \r |
399 | ///\r | |
400 | /// The start of thunk code in main memory. Memory cannot be used by BIOS or PMM.\r | |
401 | /// | |
03df1608 | 402 | UINT32 ThunkStart; |
e3e7f36a | 403 | \r |
404 | ///\r | |
405 | /// The size of the thunk code.\r | |
406 | /// | |
03df1608 | 407 | UINT32 ThunkSizeInBytes; |
8d303ef3 | 408 | \r |
409 | ///\r | |
410 | /// Starting address of memory under 1 MB.\r | |
411 | /// | |
03df1608 | 412 | UINT32 LowPmmMemory; |
8d303ef3 | 413 | \r |
414 | ///\r | |
415 | /// Length of low Memory block.\r | |
416 | /// | |
8d129536 | 417 | UINT32 LowPmmMemorySizeInBytes; |
418 | } EFI_TO_COMPATIBILITY16_INIT_TABLE; | |
419 | ||
420 | /// | |
03df1608 | 421 | /// DEVICE_PRODUCER_SERIAL |
8d129536 | 422 | /// |
423 | typedef struct { | |
e3e7f36a | 424 | UINT16 Address; ///< I/O address assigned to the serial port |
425 | UINT8 Irq; ///< IRQ assigned to the serial port. | |
426 | SERIAL_MODE Mode; ///< Mode of serial port. Values are defined below. | |
8d129536 | 427 | } DEVICE_PRODUCER_SERIAL; |
428 | ||
03df1608 | 429 | /// |
430 | /// DEVICE_PRODUCER_SERIAL's modes | |
431 | ///@{ | |
8d129536 | 432 | #define DEVICE_SERIAL_MODE_NORMAL 0x00 |
433 | #define DEVICE_SERIAL_MODE_IRDA 0x01 | |
434 | #define DEVICE_SERIAL_MODE_ASK_IR 0x02 | |
435 | #define DEVICE_SERIAL_MODE_DUPLEX_HALF 0x00 | |
436 | #define DEVICE_SERIAL_MODE_DUPLEX_FULL 0x10 | |
03df1608 | 437 | ///@) |
8d129536 | 438 | |
439 | /// | |
03df1608 | 440 | /// DEVICE_PRODUCER_PARALLEL |
8d129536 | 441 | /// |
442 | typedef struct { | |
e3e7f36a | 443 | UINT16 Address; ///< I/O address assigned to the parallel port |
444 | UINT8 Irq; ///< IRQ assigned to the parallel port. | |
445 | UINT8 Dma; ///< DMA assigned to the parallel port. | |
446 | PARALLEL_MODE Mode; ///< Mode of the parallel port. Values are defined below. | |
8d129536 | 447 | } DEVICE_PRODUCER_PARALLEL; |
448 | ||
03df1608 | 449 | /// |
450 | /// DEVICE_PRODUCER_PARALLEL's modes | |
451 | ///@{ | |
8d129536 | 452 | #define DEVICE_PARALLEL_MODE_MODE_OUTPUT_ONLY 0x00 |
453 | #define DEVICE_PARALLEL_MODE_MODE_BIDIRECTIONAL 0x01 | |
454 | #define DEVICE_PARALLEL_MODE_MODE_EPP 0x02 | |
455 | #define DEVICE_PARALLEL_MODE_MODE_ECP 0x03 | |
03df1608 | 456 | ///@} |
8d129536 | 457 | |
458 | /// | |
459 | /// DEVICE_PRODUCER_FLOPPY | |
460 | /// | |
461 | typedef struct { | |
e3e7f36a | 462 | UINT16 Address; ///< I/O address assigned to the floppy |
463 | UINT8 Irq; ///< IRQ assigned to the floppy. | |
464 | UINT8 Dma; ///< DMA assigned to the floppy. | |
465 | UINT8 NumberOfFloppy; ///< Number of floppies in the system. | |
8d129536 | 466 | } DEVICE_PRODUCER_FLOPPY; |
467 | ||
468 | /// | |
469 | /// LEGACY_DEVICE_FLAGS | |
470 | /// | |
471 | typedef struct { | |
e3e7f36a | 472 | UINT32 A20Kybd : 1; ///< A20 controller by keyboard controller. |
473 | UINT32 A20Port90 : 1; ///< A20 controlled by port 0x92. | |
474 | UINT32 Reserved : 30; ///< Reserved for future usage. | |
8d129536 | 475 | } LEGACY_DEVICE_FLAGS; |
476 | ||
477 | /// | |
478 | /// DEVICE_PRODUCER_DATA_HEADER | |
479 | /// | |
480 | typedef struct { | |
e3e7f36a | 481 | DEVICE_PRODUCER_SERIAL Serial[4]; ///< Data for serial port x. Type DEVICE_PRODUCER_SERIAL is defined below. |
482 | DEVICE_PRODUCER_PARALLEL Parallel[3]; ///< Data for parallel port x. Type DEVICE_PRODUCER_PARALLEL is defined below. | |
483 | DEVICE_PRODUCER_FLOPPY Floppy; ///< Data for floppy. Type DEVICE_PRODUCER_FLOPPY is defined below. | |
484 | UINT8 MousePresent; ///< Flag to indicate if mouse is present. | |
485 | LEGACY_DEVICE_FLAGS Flags; ///< Miscellaneous Boolean state information passed to CSM. | |
8d129536 | 486 | } DEVICE_PRODUCER_DATA_HEADER; |
487 | ||
488 | /// | |
489 | /// ATAPI_IDENTIFY | |
490 | /// | |
491 | typedef struct { | |
e3e7f36a | 492 | UINT16 Raw[256]; ///< Raw data from the IDE IdentifyDrive command. |
8d129536 | 493 | } ATAPI_IDENTIFY; |
494 | ||
495 | /// | |
03df1608 | 496 | /// HDD_INFO |
8d129536 | 497 | /// |
03df1608 | 498 | typedef struct { |
e3e7f36a | 499 | ///\r |
500 | /// Status of IDE device. Values are defined below. There is one HDD_INFO structure\r | |
501 | /// per IDE controller. The IdentifyDrive is per drive. Index 0 is master and index\r | |
502 | /// 1 is slave.\r | |
503 | /// | |
504 | UINT16 Status; \r | |
505 | \r | |
506 | ///\r | |
507 | /// PCI bus of IDE controller.\r | |
508 | /// | |
03df1608 | 509 | UINT32 Bus; |
e3e7f36a | 510 | \r |
511 | ///\r | |
512 | /// PCI device of IDE controller.\r | |
513 | /// | |
03df1608 | 514 | UINT32 Device; |
e3e7f36a | 515 | \r |
516 | ///\r | |
517 | /// PCI function of IDE controller.\r | |
518 | /// | |
03df1608 | 519 | UINT32 Function; |
e3e7f36a | 520 | \r |
521 | ///\r | |
522 | /// Command ports base address.\r | |
523 | /// | |
03df1608 | 524 | UINT16 CommandBaseAddress; |
e3e7f36a | 525 | \r |
526 | ///\r | |
527 | /// Control ports base address.\r | |
528 | /// | |
03df1608 | 529 | UINT16 ControlBaseAddress; |
e3e7f36a | 530 | \r |
531 | ///\r | |
532 | /// Bus master address\r | |
533 | /// | |
03df1608 | 534 | UINT16 BusMasterAddress; |
e3e7f36a | 535 | |
03df1608 | 536 | UINT8 HddIrq; |
e3e7f36a | 537 | \r |
538 | ///\r | |
539 | /// Data that identifies the drive data, one per possible attached drive\r | |
540 | /// | |
8d129536 | 541 | ATAPI_IDENTIFY IdentifyDrive[2]; |
542 | } HDD_INFO; | |
543 | ||
03df1608 | 544 | /// |
545 | /// HDD_INFO status bits | |
546 | /// | |
8d129536 | 547 | #define HDD_PRIMARY 0x01 |
548 | #define HDD_SECONDARY 0x02 | |
549 | #define HDD_MASTER_ATAPI_CDROM 0x04 | |
550 | #define HDD_SLAVE_ATAPI_CDROM 0x08 | |
551 | #define HDD_MASTER_IDE 0x20 | |
552 | #define HDD_SLAVE_IDE 0x40 | |
553 | #define HDD_MASTER_ATAPI_ZIPDISK 0x10 | |
554 | #define HDD_SLAVE_ATAPI_ZIPDISK 0x80 | |
555 | ||
556 | /// | |
557 | /// BBS_STATUS_FLAGS | |
558 | /// | |
559 | typedef struct { | |
e3e7f36a | 560 | UINT16 OldPosition : 4; ///< Prior priority. |
561 | UINT16 Reserved1 : 4; ///< Reserved for future use. | |
562 | UINT16 Enabled : 1; ///< If 0, ignore this entry. | |
563 | UINT16 Failed : 1; ///< 0 = Not known if boot failure occurred.\r | |
564 | ///< 1 = Boot attempted failed.\r | |
565 | \r | |
566 | ///\r | |
567 | /// State of media present.\r | |
568 | /// 00 = No bootable media is present in the device.\r | |
569 | /// 01 = Unknown if a bootable media present.\r | |
570 | /// 10 = Media is present and appears bootable.\r | |
571 | /// 11 = Reserved.\r | |
572 | /// | |
8d129536 | 573 | UINT16 MediaPresent : 2; |
e3e7f36a | 574 | UINT16 Reserved2 : 4; ///< Reserved for future use. |
8d129536 | 575 | } BBS_STATUS_FLAGS; |
576 | ||
577 | /// | |
578 | /// BBS_TABLE, device type values & boot priority values | |
579 | /// | |
03df1608 | 580 | typedef struct { |
e3e7f36a | 581 | ///\r |
582 | /// The boot priority for this boot device. Values are defined below.\r | |
583 | /// | |
03df1608 | 584 | UINT16 BootPriority; |
e3e7f36a | 585 | \r |
586 | ///\r | |
587 | /// The PCI bus for this boot device.\r | |
588 | /// | |
03df1608 | 589 | UINT32 Bus; |
e3e7f36a | 590 | \r |
591 | ///\r | |
592 | /// The PCI device for this boot device.\r | |
593 | /// | |
03df1608 | 594 | UINT32 Device; |
e3e7f36a | 595 | \r |
596 | ///\r | |
597 | /// The PCI function for the boot device.\r | |
598 | /// | |
03df1608 | 599 | UINT32 Function; |
e3e7f36a | 600 | \r |
601 | ///\r | |
602 | /// The PCI class for this boot device.\r | |
603 | /// | |
03df1608 | 604 | UINT8 Class; |
e3e7f36a | 605 | \r |
606 | ///\r | |
607 | /// The PCI Subclass for this boot device.\r | |
608 | /// | |
03df1608 | 609 | UINT8 SubClass; |
e3e7f36a | 610 | \r |
611 | ///\r | |
612 | /// Segment:offset address of an ASCIIZ description string describing the manufacturer.\r | |
613 | /// | |
03df1608 | 614 | UINT16 MfgStringOffset; |
e3e7f36a | 615 | \r |
616 | ///\r | |
617 | /// Segment:offset address of an ASCIIZ description string describing the manufacturer.\r | |
618 | /// | |
03df1608 | 619 | UINT16 MfgStringSegment; |
e3e7f36a | 620 | \r |
621 | ///\r | |
622 | /// BBS device type. BBS device types are defined below.\r | |
623 | /// | |
03df1608 | 624 | UINT16 DeviceType; |
e3e7f36a | 625 | \r |
626 | ///\r | |
627 | /// Status of this boot device. Type BBS_STATUS_FLAGS is defined below.\r | |
628 | /// | |
03df1608 | 629 | BBS_STATUS_FLAGS StatusFlags; |
e3e7f36a | 630 | \r |
631 | ///\r | |
632 | /// Segment:Offset address of boot loader for IPL devices or install INT13 handler for\r | |
633 | /// BCV devices.\r | |
634 | /// | |
03df1608 | 635 | UINT16 BootHandlerOffset; |
e3e7f36a | 636 | \r |
637 | ///\r | |
638 | /// Segment:Offset address of boot loader for IPL devices or install INT13 handler for\r | |
639 | /// BCV devices.\r | |
640 | /// | |
03df1608 | 641 | UINT16 BootHandlerSegment; |
e3e7f36a | 642 | \r |
643 | ///\r | |
644 | /// Segment:offset address of an ASCIIZ description string describing this device.\r | |
645 | /// | |
8d129536 | 646 | UINT16 DescStringOffset; |
e3e7f36a | 647 | \r |
648 | ///\r | |
649 | /// Segment:offset address of an ASCIIZ description string describing this device.\r | |
650 | ///\r | |
03df1608 | 651 | UINT16 DescStringSegment; |
e3e7f36a | 652 | \r |
653 | ///\r | |
654 | /// Reserved.\r | |
655 | /// | |
03df1608 | 656 | UINT32 InitPerReserved; |
e3e7f36a | 657 | \r |
658 | ///\r | |
659 | /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\r | |
660 | /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\r | |
661 | /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\r | |
662 | /// | |
03df1608 | 663 | UINT32 AdditionalIrq13Handler; |
e3e7f36a | 664 | \r |
665 | ///\r | |
666 | /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\r | |
667 | /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\r | |
668 | /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\r | |
669 | /// | |
03df1608 | 670 | UINT32 AdditionalIrq18Handler; |
e3e7f36a | 671 | \r |
672 | ///\r | |
673 | /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\r | |
674 | /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\r | |
675 | /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\r | |
676 | /// | |
03df1608 | 677 | UINT32 AdditionalIrq19Handler; |
e3e7f36a | 678 | \r |
679 | ///\r | |
680 | /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\r | |
681 | /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\r | |
682 | /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\r | |
683 | /// | |
8d129536 | 684 | UINT32 AdditionalIrq40Handler; |
685 | UINT8 AssignedDriveNumber; | |
686 | UINT32 AdditionalIrq41Handler; | |
687 | UINT32 AdditionalIrq46Handler; | |
688 | UINT32 IBV1; | |
689 | UINT32 IBV2; | |
690 | } BBS_TABLE; | |
691 | ||
03df1608 | 692 | /// |
693 | /// BBS device type values | |
694 | ///@{ | |
8d129536 | 695 | #define BBS_FLOPPY 0x01 |
696 | #define BBS_HARDDISK 0x02 | |
697 | #define BBS_CDROM 0x03 | |
698 | #define BBS_PCMCIA 0x04 | |
699 | #define BBS_USB 0x05 | |
700 | #define BBS_EMBED_NETWORK 0x06 | |
701 | #define BBS_BEV_DEVICE 0x80 | |
702 | #define BBS_UNKNOWN 0xff | |
03df1608 | 703 | ///@} |
8d129536 | 704 | |
03df1608 | 705 | /// |
706 | /// BBS boot priority values | |
707 | ///@{ | |
8d129536 | 708 | #define BBS_DO_NOT_BOOT_FROM 0xFFFC |
709 | #define BBS_LOWEST_PRIORITY 0xFFFD | |
710 | #define BBS_UNPRIORITIZED_ENTRY 0xFFFE | |
711 | #define BBS_IGNORE_ENTRY 0xFFFF | |
03df1608 | 712 | ///@} |
8d129536 | 713 | |
714 | /// | |
03df1608 | 715 | /// SMM_ATTRIBUTES |
8d129536 | 716 | /// |
03df1608 | 717 | typedef struct { |
e3e7f36a | 718 | ///\r |
719 | /// Access mechanism used to generate the soft SMI. Defined types are below. The other\r | |
720 | /// values are reserved for future usage.\r | |
721 | /// | |
03df1608 | 722 | UINT16 Type : 3; |
e3e7f36a | 723 | \r |
724 | ///\r | |
725 | /// Size of "port" in bits. Defined values are below.\r | |
726 | /// | |
03df1608 | 727 | UINT16 PortGranularity : 3; |
e3e7f36a | 728 | \r |
729 | ///\r | |
730 | /// Size of data in bits. Defined values are below.\r | |
731 | /// | |
03df1608 | 732 | UINT16 DataGranularity : 3; |
e3e7f36a | 733 | \r |
734 | ///\r | |
735 | /// Reserved for future use.\r | |
736 | /// | |
8d129536 | 737 | UINT16 Reserved : 7; |
738 | } SMM_ATTRIBUTES; | |
739 | ||
03df1608 | 740 | /// |
741 | /// SMM_ATTRIBUTES type values | |
742 | ///@{ | |
8d129536 | 743 | #define STANDARD_IO 0x00 |
744 | #define STANDARD_MEMORY 0x01 | |
03df1608 | 745 | ///@} |
8d129536 | 746 | |
03df1608 | 747 | /// |
748 | /// SMM_ATTRIBUTES port size constants | |
749 | ///@{ | |
8d129536 | 750 | #define PORT_SIZE_8 0x00 |
751 | #define PORT_SIZE_16 0x01 | |
752 | #define PORT_SIZE_32 0x02 | |
753 | #define PORT_SIZE_64 0x03 | |
03df1608 | 754 | ///@} |
8d129536 | 755 | |
03df1608 | 756 | /// |
757 | /// SMM_ATTRIBUTES data size constants | |
758 | ///@{ | |
8d129536 | 759 | #define DATA_SIZE_8 0x00 |
760 | #define DATA_SIZE_16 0x01 | |
761 | #define DATA_SIZE_32 0x02 | |
762 | #define DATA_SIZE_64 0x03 | |
03df1608 | 763 | ///@} |
8d129536 | 764 | |
765 | /// | |
766 | /// SMM_FUNCTION & relating constants | |
767 | /// | |
768 | typedef struct { | |
769 | UINT16 Function : 15; | |
770 | UINT16 Owner : 1; | |
771 | } SMM_FUNCTION; | |
772 | ||
03df1608 | 773 | /// |
774 | /// SMM_FUNCTION Function constants | |
775 | ///@{ | |
8d129536 | 776 | #define INT15_D042 0x0000 |
777 | #define GET_USB_BOOT_INFO 0x0001 | |
778 | #define DMI_PNP_50_57 0x0002 | |
03df1608 | 779 | ///@} |
8d129536 | 780 | |
03df1608 | 781 | /// |
782 | /// SMM_FUNCTION Owner constants | |
783 | ///@{ | |
8d129536 | 784 | #define STANDARD_OWNER 0x0 |
785 | #define OEM_OWNER 0x1 | |
03df1608 | 786 | ///@} |
8d129536 | 787 | |
788 | /** | |
789 | * SMM_ENTRY | |
790 | * | |
791 | * This structure assumes both port and data sizes are 1. SmmAttribute must be | |
792 | * properly to reflect that assumption. | |
793 | **/ | |
03df1608 | 794 | typedef struct { |
e3e7f36a | 795 | ///\r |
796 | /// Describes the access mechanism, SmmPort, and SmmData sizes. Type\r | |
797 | /// SMM_ATTRIBUTES is defined below.\r | |
798 | /// | |
03df1608 | 799 | SMM_ATTRIBUTES SmmAttributes; |
e3e7f36a | 800 | \r |
801 | ///\r | |
802 | /// Function Soft SMI is to perform. Type SMM_FUNCTION is defined below.\r | |
803 | /// | |
03df1608 | 804 | SMM_FUNCTION SmmFunction; |
e3e7f36a | 805 | \r |
806 | ///\r | |
807 | /// SmmPort size depends upon SmmAttributes and ranges from2 bytes to 16 bytes\r | |
808 | /// | |
03df1608 | 809 | UINT8 SmmPort; |
e3e7f36a | 810 | \r |
811 | ///\r | |
812 | /// SmmData size depends upon SmmAttributes and ranges from2 bytes to 16 bytes\r | |
813 | /// | |
8d129536 | 814 | UINT8 SmmData; |
815 | } SMM_ENTRY; | |
816 | ||
817 | /// | |
818 | /// SMM_TABLE | |
819 | /// | |
820 | typedef struct { | |
e3e7f36a | 821 | UINT16 NumSmmEntries; ///< Number of entries represented by SmmEntry. |
822 | SMM_ENTRY SmmEntry; ///< One entry per function. Type SMM_ENTRY is defined below. | |
8d129536 | 823 | } SMM_TABLE; |
824 | ||
825 | /// | |
826 | /// UDC_ATTRIBUTES | |
827 | /// | |
03df1608 | 828 | typedef struct { |
e3e7f36a | 829 | ///\r |
830 | /// This bit set indicates that the ServiceAreaData is valid.\r | |
831 | /// | |
03df1608 | 832 | UINT8 DirectoryServiceValidity : 1; |
e3e7f36a | 833 | \r |
834 | ///\r | |
835 | /// This bit set indicates to use the Reserve Area Boot Code Address (RACBA) only if\r | |
836 | /// DirectoryServiceValidity is 0.\r | |
837 | /// | |
03df1608 | 838 | UINT8 RabcaUsedFlag : 1; |
e3e7f36a | 839 | \r |
840 | ///\r | |
841 | /// This bit set indicates to execute hard disk diagnostics.\r | |
842 | /// | |
03df1608 | 843 | UINT8 ExecuteHddDiagnosticsFlag : 1; |
e3e7f36a | 844 | \r |
845 | ///\r | |
846 | /// Reserved for future use. Set to 0.\r | |
847 | /// | |
8d129536 | 848 | UINT8 Reserved : 5; |
849 | } UDC_ATTRIBUTES; | |
850 | ||
851 | /// | |
852 | /// UD_TABLE | |
853 | /// | |
03df1608 | 854 | typedef struct { |
e3e7f36a | 855 | ///\r |
856 | /// This field contains the bit-mapped attributes of the PARTIES information. Type\r | |
857 | /// UDC_ATTRIBUTES is defined below.\r | |
858 | /// | |
03df1608 | 859 | UDC_ATTRIBUTES Attributes; |
e3e7f36a | 860 | \r |
861 | ///\r | |
862 | /// This field contains the zero-based device on which the selected\r | |
863 | /// ServiceDataArea is present. It is 0 for master and 1 for the slave device. \r | |
864 | /// | |
03df1608 | 865 | UINT8 DeviceNumber; |
e3e7f36a | 866 | \r |
867 | ///\r | |
868 | /// This field contains the zero-based index into the BbsTable for the parent device.\r | |
869 | /// This index allows the user to reference the parent device information such as PCI\r | |
870 | /// bus, device function.\r | |
871 | /// | |
03df1608 | 872 | UINT8 BbsTableEntryNumberForParentDevice; |
e3e7f36a | 873 | \r |
874 | ///\r | |
875 | /// This field contains the zero-based index into the BbsTable for the boot entry.\r | |
876 | /// | |
03df1608 | 877 | UINT8 BbsTableEntryNumberForBoot; |
e3e7f36a | 878 | \r |
879 | ///\r | |
880 | /// This field contains the zero-based index into the BbsTable for the HDD diagnostics entry.\r | |
881 | /// | |
03df1608 | 882 | UINT8 BbsTableEntryNumberForHddDiag; |
e3e7f36a | 883 | \r |
884 | ///\r | |
885 | /// The raw Beer data.\r | |
886 | /// | |
03df1608 | 887 | UINT8 BeerData[128]; |
e3e7f36a | 888 | \r |
889 | ///\r | |
890 | /// The raw data of selected service area.\r | |
891 | /// | |
8d129536 | 892 | UINT8 ServiceAreaData[64]; |
893 | } UD_TABLE; | |
894 | ||
895 | #define EFI_TO_LEGACY_MAJOR_VERSION 0x02 | |
896 | #define EFI_TO_LEGACY_MINOR_VERSION 0x00 | |
897 | #define MAX_IDE_CONTROLLER 8 | |
898 | ||
899 | /// | |
900 | /// EFI_TO_COMPATIBILITY16_BOOT_TABLE | |
901 | /// | |
902 | typedef struct { | |
e3e7f36a | 903 | UINT16 MajorVersion; ///< The EfiCompatibility major version number. |
904 | UINT16 MinorVersion; ///< The EfiCompatibility minor version number. | |
905 | UINT32 AcpiTable; ///< Location of the RSDT ACPI table. < 4G range | |
906 | UINT32 SmbiosTable; ///< Location of the SMBIOS table in EFI memory. < 4G range | |
8d129536 | 907 | UINT32 SmbiosTableLength; |
908 | // | |
909 | // Legacy SIO state | |
910 | // | |
e3e7f36a | 911 | DEVICE_PRODUCER_DATA_HEADER SioData; ///< Standard traditional device information. |
912 | UINT16 DevicePathType; ///< The default boot type. | |
913 | UINT16 PciIrqMask; ///< Mask of which IRQs have been assigned to PCI. | |
914 | UINT32 NumberE820Entries; ///< Number of E820 entries. The number can change from the\r | |
915 | ///< Compatibility16InitializeYourself() function. | |
8d129536 | 916 | // |
917 | // Controller & Drive Identify[2] per controller information | |
918 | // | |
e3e7f36a | 919 | HDD_INFO HddInfo[MAX_IDE_CONTROLLER]; ///< Hard disk drive information, including raw Identify Drive data. |
920 | UINT32 NumberBbsEntries; ///< Number of entries in the BBS table | |
921 | UINT32 BbsTable; ///< Pointer to the BBS table. Type BBS_TABLE is defined below. | |
922 | UINT32 SmmTable; ///< Pointer to the SMM table. Type SMM_TABLE is defined below. | |
923 | UINT32 OsMemoryAbove1Mb; ///< The amount of usable memory above 1 MB, i.e. E820 type 1 memory. This value can\r | |
924 | ///< differ from the value in EFI_TO_COMPATIBILITY16_INIT_TABLE as more\r | |
925 | ///< memory may have been discovered. | |
926 | UINT32 UnconventionalDeviceTable; ///< Information to boot off an unconventional device like a PARTIES partition. Type\r | |
927 | ///< UD_TABLE is defined below. | |
8d129536 | 928 | } EFI_TO_COMPATIBILITY16_BOOT_TABLE; |
929 | ||
930 | /// | |
931 | /// EFI_LEGACY_INSTALL_PCI_HANDLER | |
932 | /// | |
933 | typedef struct { | |
e3e7f36a | 934 | UINT8 PciBus; ///< The PCI bus of the device. |
935 | UINT8 PciDeviceFun; ///< The PCI device in bits 7:3 and function in bits 2:0. | |
936 | UINT8 PciSegment; ///< The PCI segment of the device. | |
937 | UINT8 PciClass; ///< The PCI class code of the device. | |
938 | UINT8 PciSubclass; ///< The PCI subclass code of the device. | |
939 | UINT8 PciInterface; ///< The PCI interface code of the device. | |
8d129536 | 940 | // |
941 | // Primary section | |
942 | // | |
e3e7f36a | 943 | UINT8 PrimaryIrq; ///< The primary device IRQ. |
944 | UINT8 PrimaryReserved; ///< Reserved. | |
945 | UINT16 PrimaryControl; ///< The primary device control I/O base. | |
946 | UINT16 PrimaryBase; ///< The primary device I/O base. | |
947 | UINT16 PrimaryBusMaster; ///< The primary device bus master I/O base. | |
8d129536 | 948 | // |
949 | // Secondary Section | |
950 | // | |
e3e7f36a | 951 | UINT8 SecondaryIrq; ///< The secondary device IRQ. |
952 | UINT8 SecondaryReserved; ///< Reserved. | |
953 | UINT16 SecondaryControl; ///< The secondary device control I/O base. | |
954 | UINT16 SecondaryBase; ///< The secondary device I/O base. | |
955 | UINT16 SecondaryBusMaster; ///< The secondary device bus master I/O base. | |
8d129536 | 956 | } EFI_LEGACY_INSTALL_PCI_HANDLER; |
957 | ||
958 | // | |
959 | // Restore default pack value | |
960 | // | |
961 | #pragma pack() | |
962 | ||
963 | #endif /* _FRAMEWORK_LEGACY_16_H_ */ |