Minor code enhancement.
[mirror_edk2.git] / IntelFrameworkPkg / Include / Ppi / PciCfg.h
CommitLineData
caf45c98 1/** @file\r
5259c97d 2 This file declares the PciCfg PPI used to access the PCI configuration space in PEI\r
caf45c98 3\r
2bbaeb0d 4 Copyright (c) 2006 - 2009, Intel Corporation \r
caf45c98 5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
caf45c98 13 @par Revision Reference:\r
14 This PPI is defined in PEI CIS\r
15 Version 0.91.\r
16\r
17**/\r
18\r
19#ifndef __PEI_PCI_CFG_H__\r
20#define __PEI_PCI_CFG_H__\r
21\r
0e0eeeca 22#include <Ppi/PciCfg2.h>\r
24980534 23//\r
24// Get the common definitions for EFI_PEI_PCI_CFG_PPI_WIDTH.\r
25//\r
7459094d 26\r
caf45c98 27#define EFI_PEI_PCI_CFG_PPI_INSTALLED_GUID \\r
28 { \\r
29 0xe1f2eba0, 0xf7b9, 0x4a26, {0x86, 0x20, 0x13, 0x12, 0x21, 0x64, 0x2a, 0x90 } \\r
30 }\r
31\r
32typedef struct _EFI_PEI_PCI_CFG_PPI EFI_PEI_PCI_CFG_PPI;\r
33\r
34#define PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) ( \\r
35 (UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)) \\r
36 ) & 0x00000000ffffffff\r
37\r
38/**\r
39 PCI read and write operation.\r
40\r
41 @param PeiServices An indirect pointer to the PEI Services Table\r
42 published by the PEI Foundation.\r
43 @param This Pointer to local data for the interface.\r
44 @param Width The width of the access. Enumerated in bytes.\r
45 @param Address The physical address of the access.\r
46 @param Buffer A pointer to the buffer of data.\r
47\r
48 @retval EFI_SUCCESS The function completed successfully.\r
49 @retval EFI_NOT_YET_AVAILABLE The service has not been installed.\r
50\r
51**/\r
52typedef\r
53EFI_STATUS\r
69686d56 54(EFIAPI *EFI_PEI_PCI_CFG_PPI_IO)(\r
caf45c98 55 IN EFI_PEI_SERVICES **PeiServices,\r
56 IN EFI_PEI_PCI_CFG_PPI *This,\r
57 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
58 IN UINT64 Address,\r
59 IN OUT VOID *Buffer\r
60 );\r
61\r
62/**\r
63 PCI read-modify-write operation.\r
64\r
65 @param PeiServices An indirect pointer to the PEI Services Table\r
66 published by the PEI Foundation.\r
67 @param This Pointer to local data for the interface.\r
68 @param Width The width of the access. Enumerated in bytes.\r
69 @param Address The physical address of the access.\r
70 @param SetBits Value of the bits to set.\r
71 @param ClearBits Value of the bits to clear.\r
72\r
73 @retval EFI_SUCCESS The function completed successfully.\r
74\r
75**/\r
76typedef\r
77EFI_STATUS\r
69686d56 78(EFIAPI *EFI_PEI_PCI_CFG_PPI_RW)(\r
caf45c98 79 IN EFI_PEI_SERVICES **PeiServices,\r
80 IN EFI_PEI_PCI_CFG_PPI *This,\r
81 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
82 IN UINT64 Address,\r
83 IN UINTN SetBits,\r
84 IN UINTN ClearBits\r
85 );\r
86\r
87/**\r
caf45c98 88 The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI \r
89 controllers behind a PCI root bridge controller.\r
caf45c98 90**/\r
91struct _EFI_PEI_PCI_CFG_PPI {\r
2bbaeb0d 92 ///\r
93 /// PCI read services. See the Read() function description.\r
94 ///\r
caf45c98 95 EFI_PEI_PCI_CFG_PPI_IO Read;\r
2bbaeb0d 96 \r
97 ///\r
98 /// PCI write services. See the Write() function description.\r
99 ///\r
caf45c98 100 EFI_PEI_PCI_CFG_PPI_IO Write;\r
2bbaeb0d 101 \r
102 ///\r
103 /// PCI read-modify-write services. See the Modify() function description.\r
104 ///\r
caf45c98 105 EFI_PEI_PCI_CFG_PPI_RW Modify;\r
106};\r
107\r
108extern EFI_GUID gEfiPciCfgPpiInServiceTableGuid;\r
109\r
110#endif\r