caf45c98 |
1 | /** @file\r |
2 | This file declares PciCfg PPI used to access PCI configuration space in PEI\r |
3 | \r |
4 | Copyright (c) 2006, Intel Corporation \r |
5 | All rights reserved. This program and the accompanying materials \r |
6 | are licensed and made available under the terms and conditions of the BSD License \r |
7 | which accompanies this distribution. The full text of the license may be found at \r |
8 | http://opensource.org/licenses/bsd-license.php \r |
9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
12 | \r |
13 | Module Name: PciCfg.h\r |
14 | \r |
15 | @par Revision Reference:\r |
16 | This PPI is defined in PEI CIS\r |
17 | Version 0.91.\r |
18 | \r |
19 | **/\r |
20 | \r |
21 | #ifndef __PEI_PCI_CFG_H__\r |
22 | #define __PEI_PCI_CFG_H__\r |
23 | \r |
24 | #define EFI_PEI_PCI_CFG_PPI_INSTALLED_GUID \\r |
25 | { \\r |
26 | 0xe1f2eba0, 0xf7b9, 0x4a26, {0x86, 0x20, 0x13, 0x12, 0x21, 0x64, 0x2a, 0x90 } \\r |
27 | }\r |
28 | \r |
29 | typedef struct _EFI_PEI_PCI_CFG_PPI EFI_PEI_PCI_CFG_PPI;\r |
30 | \r |
31 | #define PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) ( \\r |
32 | (UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)) \\r |
33 | ) & 0x00000000ffffffff\r |
34 | \r |
35 | /**\r |
36 | PCI read and write operation.\r |
37 | \r |
38 | @param PeiServices An indirect pointer to the PEI Services Table\r |
39 | published by the PEI Foundation.\r |
40 | @param This Pointer to local data for the interface.\r |
41 | @param Width The width of the access. Enumerated in bytes.\r |
42 | @param Address The physical address of the access.\r |
43 | @param Buffer A pointer to the buffer of data.\r |
44 | \r |
45 | @retval EFI_SUCCESS The function completed successfully.\r |
46 | @retval EFI_NOT_YET_AVAILABLE The service has not been installed.\r |
47 | \r |
48 | **/\r |
49 | typedef\r |
50 | EFI_STATUS\r |
51 | (EFIAPI *EFI_PEI_PCI_CFG_PPI_IO) (\r |
52 | IN EFI_PEI_SERVICES **PeiServices,\r |
53 | IN EFI_PEI_PCI_CFG_PPI *This,\r |
54 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r |
55 | IN UINT64 Address,\r |
56 | IN OUT VOID *Buffer\r |
57 | );\r |
58 | \r |
59 | /**\r |
60 | PCI read-modify-write operation.\r |
61 | \r |
62 | @param PeiServices An indirect pointer to the PEI Services Table\r |
63 | published by the PEI Foundation.\r |
64 | @param This Pointer to local data for the interface.\r |
65 | @param Width The width of the access. Enumerated in bytes.\r |
66 | @param Address The physical address of the access.\r |
67 | @param SetBits Value of the bits to set.\r |
68 | @param ClearBits Value of the bits to clear.\r |
69 | \r |
70 | @retval EFI_SUCCESS The function completed successfully.\r |
71 | \r |
72 | **/\r |
73 | typedef\r |
74 | EFI_STATUS\r |
75 | (EFIAPI *EFI_PEI_PCI_CFG_PPI_RW) (\r |
76 | IN EFI_PEI_SERVICES **PeiServices,\r |
77 | IN EFI_PEI_PCI_CFG_PPI *This,\r |
78 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r |
79 | IN UINT64 Address,\r |
80 | IN UINTN SetBits,\r |
81 | IN UINTN ClearBits\r |
82 | );\r |
83 | \r |
84 | /**\r |
85 | @par Ppi Description:\r |
86 | The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI \r |
87 | controllers behind a PCI root bridge controller.\r |
88 | \r |
89 | @param Read\r |
90 | PCI read services. See the Read() function description.\r |
91 | \r |
92 | @param Write\r |
93 | PCI write services. See the Write() function description.\r |
94 | \r |
95 | @param Modify\r |
96 | PCI read-modify-write services. See the Modify() function description.\r |
97 | \r |
98 | **/\r |
99 | struct _EFI_PEI_PCI_CFG_PPI {\r |
100 | EFI_PEI_PCI_CFG_PPI_IO Read;\r |
101 | EFI_PEI_PCI_CFG_PPI_IO Write;\r |
102 | EFI_PEI_PCI_CFG_PPI_RW Modify;\r |
103 | };\r |
104 | \r |
105 | extern EFI_GUID gEfiPciCfgPpiInServiceTableGuid;\r |
106 | \r |
107 | #endif\r |