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1 | /** @file\r |
2 | This file declares the SMM CPU Save State protocol, which provides the processor\r |
3 | save-state information for IA-32 and Itanium processors.\r |
4 | \r |
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5 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
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6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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7 | \r |
8 | @par Revision Reference:\r |
9 | This Protocol is defined in Framework of EFI SMM Core Interface Spec\r |
10 | Version 0.91.\r |
11 | **/\r |
12 | \r |
13 | #ifndef _SMM_CPU_SAVE_STATE_H_\r |
14 | #define _SMM_CPU_SAVE_STATE_H_\r |
15 | \r |
16 | #define EFI_SMM_CPU_SAVE_STATE_PROTOCOL_GUID \\r |
17 | { \\r |
18 | 0x21f302ad, 0x6e94, 0x471b, {0x84, 0xbc, 0xb1, 0x48, 0x0, 0x40, 0x3a, 0x1d} \\r |
19 | }\r |
20 | \r |
21 | typedef struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL EFI_SMM_CPU_SAVE_STATE_PROTOCOL;\r |
22 | \r |
23 | #define EFI_SMM_MIN_REV_ID_x64 0x30006\r |
24 | \r |
25 | #pragma pack (1)\r |
26 | \r |
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27 | ///\r |
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28 | /// CPU save-state strcuture for IA32 and X64.\r |
29 | ///\r |
30 | /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because the\r |
31 | /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build\r |
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32 | /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]\r |
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33 | /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for\r |
34 | /// the layout and also maintains source comaptibility for access of all fields in this\r |
35 | /// union.\r |
36 | ///\r |
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37 | /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because\r |
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38 | /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These\r |
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39 | /// have been changed to use the base types defined in the UEFI Specification.\r |
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40 | ///\r |
41 | typedef struct {\r |
42 | UINT8 Reserved[0x200];\r |
43 | UINT8 Reserved1[0xf8]; // fe00h\r |
44 | UINT32 SMBASE; // fef8h\r |
45 | UINT32 SMMRevId; // fefch\r |
46 | UINT16 IORestart; // ff00h\r |
47 | UINT16 AutoHALTRestart; // ff02h\r |
48 | UINT32 IEDBASE; // ff04h\r |
49 | UINT8 Reserved2[0x98]; // ff08h\r |
50 | UINT32 IOMemAddr; // ffa0h\r |
51 | UINT32 IOMisc; // ffa4h\r |
52 | UINT32 _ES;\r |
53 | UINT32 _CS;\r |
54 | UINT32 _SS;\r |
55 | UINT32 _DS;\r |
56 | UINT32 _FS;\r |
57 | UINT32 _GS;\r |
58 | UINT32 _LDTBase;\r |
59 | UINT32 _TR;\r |
60 | UINT32 _DR7;\r |
61 | UINT32 _DR6;\r |
62 | UINT32 _EAX;\r |
63 | UINT32 _ECX;\r |
64 | UINT32 _EDX;\r |
65 | UINT32 _EBX;\r |
66 | UINT32 _ESP;\r |
67 | UINT32 _EBP;\r |
68 | UINT32 _ESI;\r |
69 | UINT32 _EDI;\r |
70 | UINT32 _EIP;\r |
71 | UINT32 _EFLAGS;\r |
72 | UINT32 _CR3;\r |
73 | UINT32 _CR0;\r |
74 | } EFI_SMM_CPU_STATE32;\r |
75 | \r |
76 | ///\r |
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77 | /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because\r |
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78 | /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These\r |
1c2f052d |
79 | /// have been changed to use the base types defined in the UEFI Specification.\r |
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80 | ///\r |
81 | typedef struct {\r |
82 | UINT8 Reserved1[0x1d0]; // fc00h\r |
83 | UINT32 GdtBaseHiDword; // fdd0h\r |
84 | UINT32 LdtBaseHiDword; // fdd4h\r |
85 | UINT32 IdtBaseHiDword; // fdd8h\r |
86 | UINT8 Reserved2[0xc]; // fddch\r |
87 | UINT64 IO_EIP; // fde8h\r |
88 | UINT8 Reserved3[0x50]; // fdf0h\r |
89 | UINT32 _CR4; // fe40h\r |
90 | UINT8 Reserved4[0x48]; // fe44h\r |
91 | UINT32 GdtBaseLoDword; // fe8ch\r |
92 | UINT32 GdtLimit; // fe90h\r |
93 | UINT32 IdtBaseLoDword; // fe94h\r |
94 | UINT32 IdtLimit; // fe98h\r |
95 | UINT32 LdtBaseLoDword; // fe9ch\r |
96 | UINT32 LdtLimit; // fea0h\r |
97 | UINT32 LdtInfo; // fea4h\r |
98 | UINT8 Reserved5[0x50]; // fea8h\r |
99 | UINT32 SMBASE; // fef8h\r |
100 | UINT32 SMMRevId; // fefch\r |
101 | UINT16 AutoHALTRestart; // ff00h\r |
102 | UINT16 IORestart; // ff02h\r |
103 | UINT32 IEDBASE; // ff04h\r |
104 | UINT8 Reserved6[0x14]; // ff08h\r |
105 | UINT64 _R15; // ff1ch\r |
106 | UINT64 _R14;\r |
107 | UINT64 _R13;\r |
108 | UINT64 _R12;\r |
109 | UINT64 _R11;\r |
110 | UINT64 _R10;\r |
111 | UINT64 _R9;\r |
112 | UINT64 _R8;\r |
113 | UINT64 _RAX; // ff5ch\r |
114 | UINT64 _RCX;\r |
115 | UINT64 _RDX;\r |
116 | UINT64 _RBX;\r |
117 | UINT64 _RSP;\r |
118 | UINT64 _RBP;\r |
119 | UINT64 _RSI;\r |
120 | UINT64 _RDI;\r |
121 | UINT64 IOMemAddr; // ff9ch\r |
122 | UINT32 IOMisc; // ffa4h\r |
123 | UINT32 _ES; // ffa8h\r |
124 | UINT32 _CS;\r |
125 | UINT32 _SS;\r |
126 | UINT32 _DS;\r |
127 | UINT32 _FS;\r |
128 | UINT32 _GS;\r |
129 | UINT32 _LDTR; // ffc0h\r |
130 | UINT32 _TR;\r |
131 | UINT64 _DR7; // ffc8h\r |
132 | UINT64 _DR6;\r |
133 | UINT64 _RIP; // ffd8h\r |
134 | UINT64 IA32_EFER; // ffe0h\r |
135 | UINT64 _RFLAGS; // ffe8h\r |
136 | UINT64 _CR3; // fff0h\r |
137 | UINT64 _CR0; // fff8h\r |
138 | } EFI_SMM_CPU_STATE64;\r |
139 | \r |
140 | ///\r |
141 | /// Union of CPU save-state strcutures for IA32 and X64.\r |
142 | ///\r |
143 | /// This union declaration does not exctly match the Framework SMM CIS 0.91 because the\r |
144 | /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build\r |
1c2f052d |
145 | /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]\r |
d7659786 |
146 | /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for\r |
147 | /// the layout and also maintains source comaptibility for access of all fields in this\r |
148 | /// union.\r |
149 | ///\r |
150 | typedef union {\r |
151 | EFI_SMM_CPU_STATE32 x86;\r |
152 | EFI_SMM_CPU_STATE64 x64;\r |
153 | } EFI_SMM_CPU_STATE;\r |
154 | \r |
155 | #pragma pack ()\r |
156 | \r |
157 | ///\r |
158 | /// Provides a programatic means to access SMM save state.\r |
159 | ///\r |
160 | struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL {\r |
161 | ///\r |
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162 | /// Reference to a list of save states.\r |
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163 | ///\r |
164 | EFI_SMM_CPU_STATE **CpuSaveState;\r |
165 | };\r |
166 | \r |
167 | extern EFI_GUID gEfiSmmCpuSaveStateProtocolGuid;\r |
168 | \r |
169 | #endif\r |