Remove the EDK prefix from library instance folder's name
[mirror_edk2.git] / IntelFrameworkPkg / Library / DxeIoLibCpuIo / IoLib.c
CommitLineData
79964ac8 1/** @file\r
2 I/O Library.\r
3\r
4 Copyright (c) 2006, Intel Corporation<BR>\r
5 All rights reserved. This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13 Module Name: IoLib.c\r
14\r
15**/\r
16\r
694363f8 17\r
79964ac8 18#include "DxeCpuIoLibInternal.h"\r
19\r
20//\r
21// Globle varible to cache pointer to CpuIo protocol.\r
22//\r
23STATIC EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;\r
24STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r
25\r
26/**\r
27 The constructor function caches the pointer to CpuIo protocol.\r
28\r
29 The constructor function locates CpuIo protocol from protocol database.\r
30 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r
31\r
32 @param ImageHandle The firmware allocated handle for the EFI image.\r
33 @param SystemTable A pointer to the EFI System Table.\r
34\r
35 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
36\r
37**/\r
38EFI_STATUS\r
39EFIAPI\r
40IoLibConstructor (\r
41 IN EFI_HANDLE ImageHandle,\r
42 IN EFI_SYSTEM_TABLE *SystemTable\r
43 )\r
44{\r
45 EFI_STATUS Status;\r
46\r
47 Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, &mPciRootBridgeIo);\r
48 if (EFI_ERROR (Status)) {\r
49 Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &mCpuIo);\r
50 }\r
51 ASSERT_EFI_ERROR (Status);\r
52\r
53 return Status;\r
54}\r
55\r
56/**\r
57 Reads registers in the EFI CPU I/O space.\r
58\r
59 Reads the I/O port specified by Port with registers width specified by Width.\r
60 The read value is returned. If such operations are not supported, then ASSERT().\r
61 This function must guarantee that all I/O read and write operations are serialized.\r
62\r
63 @param Port The base address of the I/O operation.\r
64 The caller is responsible for aligning the Address if required.\r
65 @param Width The width of the I/O operation.\r
66\r
67 @return Data read from registers in the EFI CPU I/O space.\r
68\r
69**/\r
70UINT64\r
71EFIAPI\r
72IoReadWorker (\r
73 IN UINTN Port,\r
74 IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
75 )\r
76{\r
77 EFI_STATUS Status;\r
78 UINT64 Data;\r
79\r
80 if (mPciRootBridgeIo != NULL) {\r
81 Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, Width, Port, 1, &Data);\r
82 } else {\r
83 Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r
84 }\r
85 ASSERT_EFI_ERROR (Status);\r
86\r
87 return Data;\r
88}\r
89\r
90/**\r
91 Writes registers in the EFI CPU I/O space.\r
92\r
93 Writes the I/O port specified by Port with registers width and value specified by Width\r
94 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
95 This function must guarantee that all I/O read and write operations are serialized.\r
96\r
97 @param Port The base address of the I/O operation.\r
98 The caller is responsible for aligning the Address if required.\r
99 @param Width The width of the I/O operation.\r
100 @param Data The value to write to the I/O port.\r
101\r
102 @return The paramter of Data.\r
103\r
104**/\r
105UINT64\r
106EFIAPI\r
107IoWriteWorker (\r
108 IN UINTN Port,\r
109 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
110 IN UINT64 Data\r
111 )\r
112{\r
113 EFI_STATUS Status;\r
114\r
115 if (mPciRootBridgeIo != NULL) {\r
116 Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, Width, Port, 1, &Data);\r
117 } else {\r
118 Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r
119 }\r
120 ASSERT_EFI_ERROR (Status);\r
121\r
122 return Data;\r
123}\r
124\r
125/**\r
126 Reads memory-mapped registers in the EFI system memory space.\r
127\r
128 Reads the MMIO registers specified by Address with registers width specified by Width.\r
129 The read value is returned. If such operations are not supported, then ASSERT().\r
130 This function must guarantee that all MMIO read and write operations are serialized.\r
131\r
132 @param Address The MMIO register to read.\r
133 The caller is responsible for aligning the Address if required.\r
134 @param Width The width of the I/O operation.\r
135\r
136 @return Data read from registers in the EFI system memory space.\r
137\r
138**/\r
139UINT64\r
140EFIAPI\r
141MmioReadWorker (\r
142 IN UINTN Address,\r
143 IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
144 )\r
145{\r
146 EFI_STATUS Status;\r
147 UINT64 Data;\r
148\r
149 if (mPciRootBridgeIo != NULL) {\r
53f93f7e 150 Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, Width, Address, 1, &Data);\r
79964ac8 151 } else {\r
152 Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r
153 }\r
154 ASSERT_EFI_ERROR (Status);\r
155\r
156 return Data;\r
157}\r
158\r
159/**\r
160 Writes memory-mapped registers in the EFI system memory space.\r
161\r
162 Writes the MMIO registers specified by Address with registers width and value specified by Width\r
163 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
164 This function must guarantee that all MMIO read and write operations are serialized.\r
165\r
166 @param Address The MMIO register to read.\r
167 The caller is responsible for aligning the Address if required.\r
168 @param Width The width of the I/O operation.\r
169\r
170 @return Data read from registers in the EFI system memory space.\r
171\r
172**/\r
173UINT64\r
174EFIAPI\r
175MmioWriteWorker (\r
176 IN UINTN Address,\r
177 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
178 IN UINT64 Data\r
179 )\r
180{\r
181 EFI_STATUS Status;\r
182\r
183 if (mPciRootBridgeIo != NULL) {\r
184 Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, Width, Address, 1, &Data);\r
185 } else {\r
186 Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r
187 }\r
188 ASSERT_EFI_ERROR (Status);\r
189\r
190 return Data;\r
191}\r
192\r
193/**\r
194 Reads an 8-bit I/O port.\r
195\r
196 Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
197 This function must guarantee that all I/O read and write operations are\r
198 serialized.\r
199\r
200 If 8-bit I/O port operations are not supported, then ASSERT().\r
201\r
202 @param Port The I/O port to read.\r
203\r
204 @return The value read.\r
205\r
206**/\r
207UINT8\r
208EFIAPI\r
209IoRead8 (\r
210 IN UINTN Port\r
211 )\r
212{\r
213 return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);\r
214}\r
215\r
216/**\r
217 Writes an 8-bit I/O port.\r
218\r
219 Writes the 8-bit I/O port specified by Port with the value specified by Value\r
220 and returns Value. This function must guarantee that all I/O read and write\r
221 operations are serialized.\r
222\r
223 If 8-bit I/O port operations are not supported, then ASSERT().\r
224\r
225 @param Port The I/O port to write.\r
226 @param Value The value to write to the I/O port.\r
227\r
228 @return The value written the I/O port.\r
229\r
230**/\r
231UINT8\r
232EFIAPI\r
233IoWrite8 (\r
234 IN UINTN Port,\r
235 IN UINT8 Value\r
236 )\r
237{\r
238 return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);\r
239}\r
240\r
241/**\r
242 Reads a 16-bit I/O port.\r
243\r
244 Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
245 This function must guarantee that all I/O read and write operations are\r
246 serialized.\r
247\r
248 If 16-bit I/O port operations are not supported, then ASSERT().\r
249\r
250 @param Port The I/O port to read.\r
251\r
252 @return The value read.\r
253\r
254**/\r
255UINT16\r
256EFIAPI\r
257IoRead16 (\r
258 IN UINTN Port\r
259 )\r
260{\r
261 //\r
262 // Make sure Port is aligned on a 16-bit boundary.\r
263 //\r
264 ASSERT ((Port & 1) == 0);\r
265 return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);\r
266}\r
267\r
268/**\r
269 Writes a 16-bit I/O port.\r
270\r
271 Writes the 16-bit I/O port specified by Port with the value specified by Value\r
272 and returns Value. This function must guarantee that all I/O read and write\r
273 operations are serialized.\r
274\r
275 If 16-bit I/O port operations are not supported, then ASSERT().\r
276\r
277 @param Port The I/O port to write.\r
278 @param Value The value to write to the I/O port.\r
279\r
280 @return The value written the I/O port.\r
281\r
282**/\r
283UINT16\r
284EFIAPI\r
285IoWrite16 (\r
286 IN UINTN Port,\r
287 IN UINT16 Value\r
288 )\r
289{\r
290 //\r
291 // Make sure Port is aligned on a 16-bit boundary.\r
292 //\r
293 ASSERT ((Port & 1) == 0);\r
294 return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);\r
295}\r
296\r
297/**\r
298 Reads a 32-bit I/O port.\r
299\r
300 Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
301 This function must guarantee that all I/O read and write operations are\r
302 serialized.\r
303\r
304 If 32-bit I/O port operations are not supported, then ASSERT().\r
305\r
306 @param Port The I/O port to read.\r
307\r
308 @return The value read.\r
309\r
310**/\r
311UINT32\r
312EFIAPI\r
313IoRead32 (\r
314 IN UINTN Port\r
315 )\r
316{\r
317 //\r
318 // Make sure Port is aligned on a 32-bit boundary.\r
319 //\r
320 ASSERT ((Port & 3) == 0);\r
321 return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);\r
322}\r
323\r
324/**\r
325 Writes a 32-bit I/O port.\r
326\r
327 Writes the 32-bit I/O port specified by Port with the value specified by Value\r
328 and returns Value. This function must guarantee that all I/O read and write\r
329 operations are serialized.\r
330\r
331 If 32-bit I/O port operations are not supported, then ASSERT().\r
332\r
333 @param Port The I/O port to write.\r
334 @param Value The value to write to the I/O port.\r
335\r
336 @return The value written the I/O port.\r
337\r
338**/\r
339UINT32\r
340EFIAPI\r
341IoWrite32 (\r
342 IN UINTN Port,\r
343 IN UINT32 Value\r
344 )\r
345{\r
346 //\r
347 // Make sure Port is aligned on a 32-bit boundary.\r
348 //\r
349 ASSERT ((Port & 3) == 0);\r
350 return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);\r
351}\r
352\r
353/**\r
354 Reads a 64-bit I/O port.\r
355\r
356 Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
357 This function must guarantee that all I/O read and write operations are\r
358 serialized.\r
359\r
360 If 64-bit I/O port operations are not supported, then ASSERT().\r
361\r
362 @param Port The I/O port to read.\r
363\r
364 @return The value read.\r
365\r
366**/\r
367UINT64\r
368EFIAPI\r
369IoRead64 (\r
370 IN UINTN Port\r
371 )\r
372{\r
373 //\r
374 // Make sure Port is aligned on a 64-bit boundary.\r
375 //\r
376 ASSERT ((Port & 7) == 0);\r
377 return IoReadWorker (Port, EfiCpuIoWidthUint64);\r
378}\r
379\r
380/**\r
381 Writes a 64-bit I/O port.\r
382\r
383 Writes the 64-bit I/O port specified by Port with the value specified by Value\r
384 and returns Value. This function must guarantee that all I/O read and write\r
385 operations are serialized.\r
386\r
387 If 64-bit I/O port operations are not supported, then ASSERT().\r
388\r
389 @param Port The I/O port to write.\r
390 @param Value The value to write to the I/O port.\r
391\r
392 @return The value written the I/O port.\r
393\r
394**/\r
395UINT64\r
396EFIAPI\r
397IoWrite64 (\r
398 IN UINTN Port,\r
399 IN UINT64 Value\r
400 )\r
401{\r
402 //\r
403 // Make sure Port is aligned on a 64-bit boundary.\r
404 //\r
405 ASSERT ((Port & 7) == 0);\r
406 return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);\r
407}\r
408\r
409/**\r
410 Reads an 8-bit MMIO register.\r
411\r
412 Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
413 returned. This function must guarantee that all MMIO read and write\r
414 operations are serialized.\r
415\r
416 If 8-bit MMIO register operations are not supported, then ASSERT().\r
417\r
418 @param Address The MMIO register to read.\r
419\r
420 @return The value read.\r
421\r
422**/\r
423UINT8\r
424EFIAPI\r
425MmioRead8 (\r
426 IN UINTN Address\r
427 )\r
428{\r
429 return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);\r
430}\r
431\r
432/**\r
433 Writes an 8-bit MMIO register.\r
434\r
435 Writes the 8-bit MMIO register specified by Address with the value specified\r
436 by Value and returns Value. This function must guarantee that all MMIO read\r
437 and write operations are serialized.\r
438\r
439 If 8-bit MMIO register operations are not supported, then ASSERT().\r
440\r
441 @param Address The MMIO register to write.\r
442 @param Value The value to write to the MMIO register.\r
443\r
444**/\r
445UINT8\r
446EFIAPI\r
447MmioWrite8 (\r
448 IN UINTN Address,\r
449 IN UINT8 Value\r
450 )\r
451{\r
452 return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);\r
453}\r
454\r
455/**\r
456 Reads a 16-bit MMIO register.\r
457\r
458 Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
459 returned. This function must guarantee that all MMIO read and write\r
460 operations are serialized.\r
461\r
462 If 16-bit MMIO register operations are not supported, then ASSERT().\r
463\r
464 @param Address The MMIO register to read.\r
465\r
466 @return The value read.\r
467\r
468**/\r
469UINT16\r
470EFIAPI\r
471MmioRead16 (\r
472 IN UINTN Address\r
473 )\r
474{\r
475 //\r
476 // Make sure Address is aligned on a 16-bit boundary.\r
477 //\r
478 ASSERT ((Address & 1) == 0);\r
479 return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);\r
480}\r
481\r
482/**\r
483 Writes a 16-bit MMIO register.\r
484\r
485 Writes the 16-bit MMIO register specified by Address with the value specified\r
486 by Value and returns Value. This function must guarantee that all MMIO read\r
487 and write operations are serialized.\r
488\r
489 If 16-bit MMIO register operations are not supported, then ASSERT().\r
490\r
491 @param Address The MMIO register to write.\r
492 @param Value The value to write to the MMIO register.\r
493\r
494**/\r
495UINT16\r
496EFIAPI\r
497MmioWrite16 (\r
498 IN UINTN Address,\r
499 IN UINT16 Value\r
500 )\r
501{\r
502 //\r
503 // Make sure Address is aligned on a 16-bit boundary.\r
504 //\r
505 ASSERT ((Address & 1) == 0);\r
506 return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);\r
507}\r
508\r
509/**\r
510 Reads a 32-bit MMIO register.\r
511\r
512 Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
513 returned. This function must guarantee that all MMIO read and write\r
514 operations are serialized.\r
515\r
516 If 32-bit MMIO register operations are not supported, then ASSERT().\r
517\r
518 @param Address The MMIO register to read.\r
519\r
520 @return The value read.\r
521\r
522**/\r
523UINT32\r
524EFIAPI\r
525MmioRead32 (\r
526 IN UINTN Address\r
527 )\r
528{\r
529 //\r
530 // Make sure Address is aligned on a 32-bit boundary.\r
531 //\r
532 ASSERT ((Address & 3) == 0);\r
533 return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);\r
534}\r
535\r
536/**\r
537 Writes a 32-bit MMIO register.\r
538\r
539 Writes the 32-bit MMIO register specified by Address with the value specified\r
540 by Value and returns Value. This function must guarantee that all MMIO read\r
541 and write operations are serialized.\r
542\r
543 If 32-bit MMIO register operations are not supported, then ASSERT().\r
544\r
545 @param Address The MMIO register to write.\r
546 @param Value The value to write to the MMIO register.\r
547\r
548**/\r
549UINT32\r
550EFIAPI\r
551MmioWrite32 (\r
552 IN UINTN Address,\r
553 IN UINT32 Value\r
554 )\r
555{\r
556 //\r
557 // Make sure Address is aligned on a 32-bit boundary.\r
558 //\r
559 ASSERT ((Address & 3) == 0);\r
560 return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);\r
561}\r
562\r
563/**\r
564 Reads a 64-bit MMIO register.\r
565\r
566 Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
567 returned. This function must guarantee that all MMIO read and write\r
568 operations are serialized.\r
569\r
570 If 64-bit MMIO register operations are not supported, then ASSERT().\r
571\r
572 @param Address The MMIO register to read.\r
573\r
574 @return The value read.\r
575\r
576**/\r
577UINT64\r
578EFIAPI\r
579MmioRead64 (\r
580 IN UINTN Address\r
581 )\r
582{\r
583 //\r
584 // Make sure Address is aligned on a 64-bit boundary.\r
585 //\r
586 ASSERT ((Address & 7) == 0);\r
587 return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);\r
588}\r
589\r
590/**\r
591 Writes a 64-bit MMIO register.\r
592\r
593 Writes the 64-bit MMIO register specified by Address with the value specified\r
594 by Value and returns Value. This function must guarantee that all MMIO read\r
595 and write operations are serialized.\r
596\r
597 If 64-bit MMIO register operations are not supported, then ASSERT().\r
598\r
599 @param Address The MMIO register to write.\r
600 @param Value The value to write to the MMIO register.\r
601\r
602**/\r
603UINT64\r
604EFIAPI\r
605MmioWrite64 (\r
606 IN UINTN Address,\r
607 IN UINT64 Value\r
608 )\r
609{\r
610 //\r
611 // Make sure Address is aligned on a 64-bit boundary.\r
612 //\r
613 ASSERT ((Address & 7) == 0);\r
614 return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);\r
615}\r