Fix typo in comment.
[mirror_edk2.git] / IntelFrameworkPkg / Library / DxeIoLibCpuIo / IoLib.c
CommitLineData
79964ac8 1/** @file\r
2 I/O Library.\r
c4fa3eac 3 The implementation of I/O operation for this library instance \r
4 are based on EFI_CPU_IO_PROTOCOL.\r
5 \r
79964ac8 6 Copyright (c) 2006, Intel Corporation<BR>\r
7 All rights reserved. This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15 Module Name: IoLib.c\r
16\r
17**/\r
18\r
694363f8 19\r
79964ac8 20#include "DxeCpuIoLibInternal.h"\r
21\r
22//\r
23// Globle varible to cache pointer to CpuIo protocol.\r
24//\r
25STATIC EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;\r
26STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r
27\r
28/**\r
29 The constructor function caches the pointer to CpuIo protocol.\r
30\r
31 The constructor function locates CpuIo protocol from protocol database.\r
32 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r
33\r
34 @param ImageHandle The firmware allocated handle for the EFI image.\r
35 @param SystemTable A pointer to the EFI System Table.\r
36\r
37 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
38\r
39**/\r
40EFI_STATUS\r
41EFIAPI\r
42IoLibConstructor (\r
43 IN EFI_HANDLE ImageHandle,\r
44 IN EFI_SYSTEM_TABLE *SystemTable\r
45 )\r
46{\r
47 EFI_STATUS Status;\r
48\r
856500d8 49 Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID **) &mPciRootBridgeIo);\r
79964ac8 50 if (EFI_ERROR (Status)) {\r
856500d8 51 Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **) &mCpuIo);\r
79964ac8 52 }\r
53 ASSERT_EFI_ERROR (Status);\r
54\r
55 return Status;\r
56}\r
57\r
58/**\r
59 Reads registers in the EFI CPU I/O space.\r
60\r
61 Reads the I/O port specified by Port with registers width specified by Width.\r
62 The read value is returned. If such operations are not supported, then ASSERT().\r
63 This function must guarantee that all I/O read and write operations are serialized.\r
64\r
65 @param Port The base address of the I/O operation.\r
66 The caller is responsible for aligning the Address if required.\r
67 @param Width The width of the I/O operation.\r
68\r
69 @return Data read from registers in the EFI CPU I/O space.\r
70\r
71**/\r
72UINT64\r
73EFIAPI\r
74IoReadWorker (\r
75 IN UINTN Port,\r
76 IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
77 )\r
78{\r
79 EFI_STATUS Status;\r
80 UINT64 Data;\r
81\r
82 if (mPciRootBridgeIo != NULL) {\r
856500d8 83 Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r
79964ac8 84 } else {\r
85 Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r
86 }\r
87 ASSERT_EFI_ERROR (Status);\r
88\r
89 return Data;\r
90}\r
91\r
92/**\r
93 Writes registers in the EFI CPU I/O space.\r
94\r
95 Writes the I/O port specified by Port with registers width and value specified by Width\r
96 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
97 This function must guarantee that all I/O read and write operations are serialized.\r
98\r
99 @param Port The base address of the I/O operation.\r
100 The caller is responsible for aligning the Address if required.\r
101 @param Width The width of the I/O operation.\r
102 @param Data The value to write to the I/O port.\r
103\r
104 @return The paramter of Data.\r
105\r
106**/\r
107UINT64\r
108EFIAPI\r
109IoWriteWorker (\r
110 IN UINTN Port,\r
111 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
112 IN UINT64 Data\r
113 )\r
114{\r
115 EFI_STATUS Status;\r
116\r
117 if (mPciRootBridgeIo != NULL) {\r
856500d8 118 Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Port, 1, &Data);\r
79964ac8 119 } else {\r
120 Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r
121 }\r
122 ASSERT_EFI_ERROR (Status);\r
123\r
124 return Data;\r
125}\r
126\r
127/**\r
128 Reads memory-mapped registers in the EFI system memory space.\r
129\r
130 Reads the MMIO registers specified by Address with registers width specified by Width.\r
131 The read value is returned. If such operations are not supported, then ASSERT().\r
132 This function must guarantee that all MMIO read and write operations are serialized.\r
133\r
134 @param Address The MMIO register to read.\r
135 The caller is responsible for aligning the Address if required.\r
136 @param Width The width of the I/O operation.\r
137\r
138 @return Data read from registers in the EFI system memory space.\r
139\r
140**/\r
141UINT64\r
142EFIAPI\r
143MmioReadWorker (\r
144 IN UINTN Address,\r
145 IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
146 )\r
147{\r
148 EFI_STATUS Status;\r
149 UINT64 Data;\r
150\r
151 if (mPciRootBridgeIo != NULL) {\r
856500d8 152 Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r
79964ac8 153 } else {\r
154 Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r
155 }\r
156 ASSERT_EFI_ERROR (Status);\r
157\r
158 return Data;\r
159}\r
160\r
161/**\r
162 Writes memory-mapped registers in the EFI system memory space.\r
163\r
164 Writes the MMIO registers specified by Address with registers width and value specified by Width\r
165 and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
166 This function must guarantee that all MMIO read and write operations are serialized.\r
167\r
168 @param Address The MMIO register to read.\r
169 The caller is responsible for aligning the Address if required.\r
170 @param Width The width of the I/O operation.\r
7459094d 171 @param Data The value to write to the I/O port.\r
172 \r
79964ac8 173 @return Data read from registers in the EFI system memory space.\r
174\r
175**/\r
176UINT64\r
177EFIAPI\r
178MmioWriteWorker (\r
179 IN UINTN Address,\r
180 IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
181 IN UINT64 Data\r
182 )\r
183{\r
184 EFI_STATUS Status;\r
185\r
186 if (mPciRootBridgeIo != NULL) {\r
856500d8 187 Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, Address, 1, &Data);\r
79964ac8 188 } else {\r
189 Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r
190 }\r
191 ASSERT_EFI_ERROR (Status);\r
192\r
193 return Data;\r
194}\r
195\r
196/**\r
197 Reads an 8-bit I/O port.\r
198\r
199 Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
200 This function must guarantee that all I/O read and write operations are\r
201 serialized.\r
202\r
203 If 8-bit I/O port operations are not supported, then ASSERT().\r
204\r
205 @param Port The I/O port to read.\r
206\r
207 @return The value read.\r
208\r
209**/\r
210UINT8\r
211EFIAPI\r
212IoRead8 (\r
213 IN UINTN Port\r
214 )\r
215{\r
216 return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);\r
217}\r
218\r
219/**\r
220 Writes an 8-bit I/O port.\r
221\r
222 Writes the 8-bit I/O port specified by Port with the value specified by Value\r
223 and returns Value. This function must guarantee that all I/O read and write\r
224 operations are serialized.\r
225\r
226 If 8-bit I/O port operations are not supported, then ASSERT().\r
227\r
228 @param Port The I/O port to write.\r
229 @param Value The value to write to the I/O port.\r
230\r
231 @return The value written the I/O port.\r
232\r
233**/\r
234UINT8\r
235EFIAPI\r
236IoWrite8 (\r
237 IN UINTN Port,\r
238 IN UINT8 Value\r
239 )\r
240{\r
241 return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);\r
242}\r
243\r
244/**\r
245 Reads a 16-bit I/O port.\r
246\r
247 Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
248 This function must guarantee that all I/O read and write operations are\r
249 serialized.\r
250\r
251 If 16-bit I/O port operations are not supported, then ASSERT().\r
252\r
253 @param Port The I/O port to read.\r
254\r
255 @return The value read.\r
256\r
257**/\r
258UINT16\r
259EFIAPI\r
260IoRead16 (\r
261 IN UINTN Port\r
262 )\r
263{\r
264 //\r
265 // Make sure Port is aligned on a 16-bit boundary.\r
266 //\r
267 ASSERT ((Port & 1) == 0);\r
268 return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);\r
269}\r
270\r
271/**\r
272 Writes a 16-bit I/O port.\r
273\r
274 Writes the 16-bit I/O port specified by Port with the value specified by Value\r
275 and returns Value. This function must guarantee that all I/O read and write\r
276 operations are serialized.\r
277\r
278 If 16-bit I/O port operations are not supported, then ASSERT().\r
279\r
280 @param Port The I/O port to write.\r
281 @param Value The value to write to the I/O port.\r
282\r
283 @return The value written the I/O port.\r
284\r
285**/\r
286UINT16\r
287EFIAPI\r
288IoWrite16 (\r
289 IN UINTN Port,\r
290 IN UINT16 Value\r
291 )\r
292{\r
293 //\r
294 // Make sure Port is aligned on a 16-bit boundary.\r
295 //\r
296 ASSERT ((Port & 1) == 0);\r
297 return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);\r
298}\r
299\r
300/**\r
301 Reads a 32-bit I/O port.\r
302\r
303 Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
304 This function must guarantee that all I/O read and write operations are\r
305 serialized.\r
306\r
307 If 32-bit I/O port operations are not supported, then ASSERT().\r
308\r
309 @param Port The I/O port to read.\r
310\r
311 @return The value read.\r
312\r
313**/\r
314UINT32\r
315EFIAPI\r
316IoRead32 (\r
317 IN UINTN Port\r
318 )\r
319{\r
320 //\r
321 // Make sure Port is aligned on a 32-bit boundary.\r
322 //\r
323 ASSERT ((Port & 3) == 0);\r
324 return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);\r
325}\r
326\r
327/**\r
328 Writes a 32-bit I/O port.\r
329\r
330 Writes the 32-bit I/O port specified by Port with the value specified by Value\r
331 and returns Value. This function must guarantee that all I/O read and write\r
332 operations are serialized.\r
333\r
334 If 32-bit I/O port operations are not supported, then ASSERT().\r
335\r
336 @param Port The I/O port to write.\r
337 @param Value The value to write to the I/O port.\r
338\r
339 @return The value written the I/O port.\r
340\r
341**/\r
342UINT32\r
343EFIAPI\r
344IoWrite32 (\r
345 IN UINTN Port,\r
346 IN UINT32 Value\r
347 )\r
348{\r
349 //\r
350 // Make sure Port is aligned on a 32-bit boundary.\r
351 //\r
352 ASSERT ((Port & 3) == 0);\r
353 return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);\r
354}\r
355\r
356/**\r
357 Reads a 64-bit I/O port.\r
358\r
359 Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
360 This function must guarantee that all I/O read and write operations are\r
361 serialized.\r
362\r
363 If 64-bit I/O port operations are not supported, then ASSERT().\r
364\r
365 @param Port The I/O port to read.\r
366\r
367 @return The value read.\r
368\r
369**/\r
370UINT64\r
371EFIAPI\r
372IoRead64 (\r
373 IN UINTN Port\r
374 )\r
375{\r
376 //\r
377 // Make sure Port is aligned on a 64-bit boundary.\r
378 //\r
379 ASSERT ((Port & 7) == 0);\r
380 return IoReadWorker (Port, EfiCpuIoWidthUint64);\r
381}\r
382\r
383/**\r
384 Writes a 64-bit I/O port.\r
385\r
386 Writes the 64-bit I/O port specified by Port with the value specified by Value\r
387 and returns Value. This function must guarantee that all I/O read and write\r
388 operations are serialized.\r
389\r
390 If 64-bit I/O port operations are not supported, then ASSERT().\r
391\r
392 @param Port The I/O port to write.\r
393 @param Value The value to write to the I/O port.\r
394\r
395 @return The value written the I/O port.\r
396\r
397**/\r
398UINT64\r
399EFIAPI\r
400IoWrite64 (\r
401 IN UINTN Port,\r
402 IN UINT64 Value\r
403 )\r
404{\r
405 //\r
406 // Make sure Port is aligned on a 64-bit boundary.\r
407 //\r
408 ASSERT ((Port & 7) == 0);\r
409 return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);\r
410}\r
411\r
412/**\r
413 Reads an 8-bit MMIO register.\r
414\r
415 Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
416 returned. This function must guarantee that all MMIO read and write\r
417 operations are serialized.\r
418\r
419 If 8-bit MMIO register operations are not supported, then ASSERT().\r
420\r
421 @param Address The MMIO register to read.\r
422\r
423 @return The value read.\r
424\r
425**/\r
426UINT8\r
427EFIAPI\r
428MmioRead8 (\r
429 IN UINTN Address\r
430 )\r
431{\r
432 return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);\r
433}\r
434\r
435/**\r
436 Writes an 8-bit MMIO register.\r
437\r
438 Writes the 8-bit MMIO register specified by Address with the value specified\r
439 by Value and returns Value. This function must guarantee that all MMIO read\r
440 and write operations are serialized.\r
441\r
442 If 8-bit MMIO register operations are not supported, then ASSERT().\r
443\r
444 @param Address The MMIO register to write.\r
445 @param Value The value to write to the MMIO register.\r
446\r
447**/\r
448UINT8\r
449EFIAPI\r
450MmioWrite8 (\r
451 IN UINTN Address,\r
452 IN UINT8 Value\r
453 )\r
454{\r
455 return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);\r
456}\r
457\r
458/**\r
459 Reads a 16-bit MMIO register.\r
460\r
461 Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
462 returned. This function must guarantee that all MMIO read and write\r
463 operations are serialized.\r
464\r
465 If 16-bit MMIO register operations are not supported, then ASSERT().\r
466\r
467 @param Address The MMIO register to read.\r
468\r
469 @return The value read.\r
470\r
471**/\r
472UINT16\r
473EFIAPI\r
474MmioRead16 (\r
475 IN UINTN Address\r
476 )\r
477{\r
478 //\r
479 // Make sure Address is aligned on a 16-bit boundary.\r
480 //\r
481 ASSERT ((Address & 1) == 0);\r
482 return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);\r
483}\r
484\r
485/**\r
486 Writes a 16-bit MMIO register.\r
487\r
488 Writes the 16-bit MMIO register specified by Address with the value specified\r
489 by Value and returns Value. This function must guarantee that all MMIO read\r
490 and write operations are serialized.\r
491\r
492 If 16-bit MMIO register operations are not supported, then ASSERT().\r
493\r
494 @param Address The MMIO register to write.\r
495 @param Value The value to write to the MMIO register.\r
496\r
497**/\r
498UINT16\r
499EFIAPI\r
500MmioWrite16 (\r
501 IN UINTN Address,\r
502 IN UINT16 Value\r
503 )\r
504{\r
505 //\r
506 // Make sure Address is aligned on a 16-bit boundary.\r
507 //\r
508 ASSERT ((Address & 1) == 0);\r
509 return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);\r
510}\r
511\r
512/**\r
513 Reads a 32-bit MMIO register.\r
514\r
515 Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
516 returned. This function must guarantee that all MMIO read and write\r
517 operations are serialized.\r
518\r
519 If 32-bit MMIO register operations are not supported, then ASSERT().\r
520\r
521 @param Address The MMIO register to read.\r
522\r
523 @return The value read.\r
524\r
525**/\r
526UINT32\r
527EFIAPI\r
528MmioRead32 (\r
529 IN UINTN Address\r
530 )\r
531{\r
532 //\r
533 // Make sure Address is aligned on a 32-bit boundary.\r
534 //\r
535 ASSERT ((Address & 3) == 0);\r
536 return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);\r
537}\r
538\r
539/**\r
540 Writes a 32-bit MMIO register.\r
541\r
542 Writes the 32-bit MMIO register specified by Address with the value specified\r
543 by Value and returns Value. This function must guarantee that all MMIO read\r
544 and write operations are serialized.\r
545\r
546 If 32-bit MMIO register operations are not supported, then ASSERT().\r
547\r
548 @param Address The MMIO register to write.\r
549 @param Value The value to write to the MMIO register.\r
550\r
551**/\r
552UINT32\r
553EFIAPI\r
554MmioWrite32 (\r
555 IN UINTN Address,\r
556 IN UINT32 Value\r
557 )\r
558{\r
559 //\r
560 // Make sure Address is aligned on a 32-bit boundary.\r
561 //\r
562 ASSERT ((Address & 3) == 0);\r
563 return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);\r
564}\r
565\r
566/**\r
567 Reads a 64-bit MMIO register.\r
568\r
569 Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
570 returned. This function must guarantee that all MMIO read and write\r
571 operations are serialized.\r
572\r
573 If 64-bit MMIO register operations are not supported, then ASSERT().\r
574\r
575 @param Address The MMIO register to read.\r
576\r
577 @return The value read.\r
578\r
579**/\r
580UINT64\r
581EFIAPI\r
582MmioRead64 (\r
583 IN UINTN Address\r
584 )\r
585{\r
586 //\r
587 // Make sure Address is aligned on a 64-bit boundary.\r
588 //\r
589 ASSERT ((Address & 7) == 0);\r
590 return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);\r
591}\r
592\r
593/**\r
594 Writes a 64-bit MMIO register.\r
595\r
596 Writes the 64-bit MMIO register specified by Address with the value specified\r
597 by Value and returns Value. This function must guarantee that all MMIO read\r
598 and write operations are serialized.\r
599\r
600 If 64-bit MMIO register operations are not supported, then ASSERT().\r
601\r
602 @param Address The MMIO register to write.\r
603 @param Value The value to write to the MMIO register.\r
604\r
605**/\r
606UINT64\r
607EFIAPI\r
608MmioWrite64 (\r
609 IN UINTN Address,\r
610 IN UINT64 Value\r
611 )\r
612{\r
613 //\r
614 // Make sure Address is aligned on a 64-bit boundary.\r
615 //\r
616 ASSERT ((Address & 7) == 0);\r
617 return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);\r
618}\r