projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| f2cdb268 CC |
1 | ## @file\r |
| 2 | # Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization.\r | |
| 3 | #\r | |
| 00aa71ce | 4 | # Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>\r |
| f2cdb268 CC |
5 | #\r |
| 6 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 7 | #\r | |
| 8 | ##\r | |
| 9 | \r | |
| 10 | [Defines]\r | |
| 11 | INF_VERSION = 0x00010005\r | |
| 12 | BASE_NAME = Fsp22SecCoreS\r | |
| 13 | FILE_GUID = DF0FCD70-264A-40BF-BBD4-06C76DB19CB1\r | |
| 14 | MODULE_TYPE = SEC\r | |
| 15 | VERSION_STRING = 1.0\r | |
| 16 | \r | |
| 17 | #\r | |
| 18 | # The following information is for reference only and not required by the build tools.\r | |
| 19 | #\r | |
| 00aa71ce | 20 | # VALID_ARCHITECTURES = IA32 X64\r |
| f2cdb268 CC |
21 | #\r |
| 22 | \r | |
| 23 | [Sources]\r | |
| 24 | SecFspApiChk.c\r | |
| 25 | SecFsp.h\r | |
| 26 | \r | |
| 27 | [Sources.IA32]\r | |
| 28 | Ia32/Stack.nasm\r | |
| 29 | Ia32/Fsp22ApiEntryS.nasm\r | |
| 30 | Ia32/FspApiEntryCommon.nasm\r | |
| 31 | Ia32/FspHelper.nasm\r | |
| 32 | \r | |
| 00aa71ce TK |
33 | [Sources.X64]\r |
| 34 | X64/Stack.nasm\r | |
| 35 | X64/Fsp22ApiEntryS.nasm\r | |
| 36 | X64/FspApiEntryCommon.nasm\r | |
| 37 | X64/FspHelper.nasm\r | |
| 38 | \r | |
| f2cdb268 CC |
39 | [Binaries.Ia32]\r |
| 40 | RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC\r | |
| 41 | \r | |
| 42 | [Packages]\r | |
| 43 | MdePkg/MdePkg.dec\r | |
| 44 | IntelFsp2Pkg/IntelFsp2Pkg.dec\r | |
| 45 | \r | |
| 46 | [LibraryClasses]\r | |
| 47 | BaseMemoryLib\r | |
| 48 | DebugLib\r | |
| 49 | BaseLib\r | |
| 50 | PciCf8Lib\r | |
| 51 | SerialPortLib\r | |
| 52 | FspSwitchStackLib\r | |
| 53 | FspCommonLib\r | |
| 54 | FspSecPlatformLib\r | |
| 55 | \r | |
| 56 | [Ppis]\r | |
| 57 | gEfiTemporaryRamSupportPpiGuid ## PRODUCES\r | |
| 58 | \r |