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cf1d4549 JY |
1 | /** @file\r |
2 | Intel FSP API definition from Intel Firmware Support Package External\r | |
f2cdb268 | 3 | Architecture Specification v2.0 - v2.2\r |
cf1d4549 | 4 | \r |
f2cdb268 | 5 | Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>\r |
9672cd30 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
cf1d4549 JY |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef _FSP_API_H_\r | |
11 | #define _FSP_API_H_\r | |
12 | \r | |
f2cdb268 CC |
13 | #include <Pi/PiStatusCode.h>\r |
14 | \r | |
19089568 GM |
15 | ///\r |
16 | /// FSP Reset Status code\r | |
17 | /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code\r | |
18 | /// @{\r | |
19 | #define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001\r | |
20 | #define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002\r | |
21 | #define FSP_STATUS_RESET_REQUIRED_3 0x40000003\r | |
22 | #define FSP_STATUS_RESET_REQUIRED_4 0x40000004\r | |
23 | #define FSP_STATUS_RESET_REQUIRED_5 0x40000005\r | |
24 | #define FSP_STATUS_RESET_REQUIRED_6 0x40000006\r | |
25 | #define FSP_STATUS_RESET_REQUIRED_7 0x40000007\r | |
26 | #define FSP_STATUS_RESET_REQUIRED_8 0x40000008\r | |
27 | /// @}\r | |
28 | \r | |
f2cdb268 CC |
29 | ///\r |
30 | /// FSP Event related definition.\r | |
31 | ///\r | |
32 | #define FSP_EVENT_CODE 0xF5000000\r | |
33 | #define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)\r | |
34 | \r | |
35 | /*\r | |
36 | FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.\r | |
37 | These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the\r | |
38 | status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3.\r | |
39 | \r | |
40 | @param[in] Type Indicates the type of event being reported.\r | |
41 | See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE.\r | |
42 | @param[in] Value Describes the current status of a hardware or software entity.\r | |
43 | This includes information about the class and subclass that is used to classify the entity as well as an operation.\r | |
44 | For progress events, the operation is the current activity. For error events, it is the exception.\r | |
45 | For debug events, it is not defined at this time.\r | |
46 | See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE.\r | |
47 | @param[in] Instance The enumeration of a hardware or software entity within the system.\r | |
48 | A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them.\r | |
49 | An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant.\r | |
50 | Valid instance numbers start with 1.\r | |
51 | @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event.\r | |
52 | This parameter may be NULL.\r | |
53 | @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data.\r | |
54 | For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages.\r | |
55 | This parameter is NULL when no additional data is provided.\r | |
56 | \r | |
57 | @retval EFI_SUCCESS The event was handled successfully.\r | |
58 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
59 | @retval EFI_DEVICE_ERROR The event handler failed.\r | |
60 | */\r | |
61 | typedef\r | |
62 | EFI_STATUS\r | |
63 | (EFIAPI *FSP_EVENT_HANDLER) (\r | |
64 | IN EFI_STATUS_CODE_TYPE Type,\r | |
65 | IN EFI_STATUS_CODE_VALUE Value,\r | |
66 | IN UINT32 Instance,\r | |
67 | IN OPTIONAL EFI_GUID *CallerId,\r | |
68 | IN OPTIONAL EFI_STATUS_CODE_DATA *Data\r | |
69 | );\r | |
70 | \r | |
71 | /*\r | |
72 | Handler for FSP-T debug log messages, provided by the bootloader.\r | |
73 | \r | |
74 | @param[in] DebugMessage A pointer to the debug message to be written to the log.\r | |
75 | @param[in] MessageLength Number of bytes to written to the debug log.\r | |
76 | \r | |
77 | @retval UINT32 The return value indicates the number of bytes actually written to\r | |
78 | the debug log. If the return value is less than MessageLength,\r | |
79 | an error occurred.\r | |
80 | */\r | |
81 | typedef\r | |
82 | UINT32\r | |
83 | (EFIAPI *FSP_DEBUG_HANDLER) (\r | |
84 | IN CHAR8* DebugMessage,\r | |
85 | IN UINT32 MessageLength\r | |
86 | );\r | |
87 | \r | |
cf1d4549 | 88 | #pragma pack(1)\r |
6d0ac988 JY |
89 | ///\r |
90 | /// FSP_UPD_HEADER Configuration.\r | |
91 | ///\r | |
cf1d4549 JY |
92 | typedef struct {\r |
93 | ///\r | |
94 | /// UPD Region Signature. This signature will be\r | |
95 | /// "XXXXXX_T" for FSP-T\r | |
96 | /// "XXXXXX_M" for FSP-M\r | |
97 | /// "XXXXXX_S" for FSP-S\r | |
98 | /// Where XXXXXX is an unique signature\r | |
99 | ///\r | |
100 | UINT64 Signature;\r | |
101 | ///\r | |
89f569ae CC |
102 | /// Revision of the Data structure.\r |
103 | /// For FSP spec 2.0/2.1 value is 1.\r | |
104 | /// For FSP spec 2.2 value is 2.\r | |
cf1d4549 JY |
105 | ///\r |
106 | UINT8 Revision;\r | |
107 | UINT8 Reserved[23];\r | |
108 | } FSP_UPD_HEADER;\r | |
109 | \r | |
89f569ae CC |
110 | ///\r |
111 | /// FSPT_ARCH_UPD Configuration.\r | |
112 | ///\r | |
113 | typedef struct {\r | |
114 | ///\r | |
115 | /// Revision Revision of the structure is 1 for this version of the specification.\r | |
116 | ///\r | |
117 | UINT8 Revision;\r | |
118 | UINT8 Reserved[3];\r | |
119 | ///\r | |
120 | /// Length Length of the structure in bytes. The current value for this field is 32.\r | |
121 | ///\r | |
122 | UINT32 Length;\r | |
123 | ///\r | |
124 | /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r | |
125 | /// occurring during FSP execution.\r | |
126 | ///\r | |
127 | FSP_DEBUG_HANDLER FspDebugHandler;\r | |
128 | UINT8 Reserved1[20];\r | |
129 | } FSPT_ARCH_UPD;\r | |
130 | \r | |
6d0ac988 JY |
131 | ///\r |
132 | /// FSPM_ARCH_UPD Configuration.\r | |
133 | ///\r | |
cf1d4549 JY |
134 | typedef struct {\r |
135 | ///\r | |
136 | /// Revision of the structure. For FSP v2.0 value is 1.\r | |
137 | ///\r | |
138 | UINT8 Revision;\r | |
139 | UINT8 Reserved[3];\r | |
140 | ///\r | |
141 | /// Pointer to the non-volatile storage (NVS) data buffer.\r | |
142 | /// If it is NULL it indicates the NVS data is not available.\r | |
143 | ///\r | |
144 | VOID *NvsBufferPtr;\r | |
145 | ///\r | |
146 | /// Pointer to the temporary stack base address to be\r | |
147 | /// consumed inside FspMemoryInit() API.\r | |
148 | ///\r | |
149 | VOID *StackBase;\r | |
150 | ///\r | |
151 | /// Temporary stack size to be consumed inside\r | |
152 | /// FspMemoryInit() API.\r | |
153 | ///\r | |
154 | UINT32 StackSize;\r | |
155 | ///\r | |
156 | /// Size of memory to be reserved by FSP below "top\r | |
157 | /// of low usable memory" for bootloader usage.\r | |
158 | ///\r | |
159 | UINT32 BootLoaderTolumSize;\r | |
160 | ///\r | |
161 | /// Current boot mode.\r | |
162 | ///\r | |
163 | UINT32 BootMode;\r | |
f2cdb268 CC |
164 | ///\r |
165 | /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r | |
166 | /// This value is only valid if Revision is >= 2.\r | |
167 | ///\r | |
168 | FSP_EVENT_HANDLER *FspEventHandler;\r | |
169 | UINT8 Reserved1[4];\r | |
cf1d4549 JY |
170 | } FSPM_ARCH_UPD;\r |
171 | \r | |
89f569ae CC |
172 | typedef struct {\r |
173 | ///\r | |
174 | /// Revision Revision of the structure is 1 for this version of the specification.\r | |
175 | ///\r | |
176 | UINT8 Revision;\r | |
177 | UINT8 Reserved[3];\r | |
178 | ///\r | |
179 | /// Length Length of the structure in bytes. The current value for this field is 32.\r | |
180 | ///\r | |
181 | UINT32 Length;\r | |
182 | ///\r | |
183 | /// FspEventHandler Optional event handler for the bootloader to be informed of events\r | |
184 | /// occurring during FSP execution.\r | |
185 | ///\r | |
186 | FSP_EVENT_HANDLER FspEventHandler;\r | |
187 | ///\r | |
188 | /// A FSP binary may optionally implement multi-phase silicon initialization,\r | |
189 | /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER\r | |
190 | /// is non-zero.\r | |
191 | /// To enable multi-phase silicon initialization, the bootloader must set\r | |
192 | /// EnableMultiPhaseSiliconInit to a non-zero value.\r | |
193 | ///\r | |
194 | UINT8 EnableMultiPhaseSiliconInit;\r | |
195 | UINT8 Reserved1[19];\r | |
196 | } FSPS_ARCH_UPD;\r | |
197 | \r | |
6d0ac988 JY |
198 | ///\r |
199 | /// FSPT_UPD_COMMON Configuration.\r | |
200 | ///\r | |
cf1d4549 | 201 | typedef struct {\r |
6d0ac988 JY |
202 | ///\r |
203 | /// FSP_UPD_HEADER Configuration.\r | |
204 | ///\r | |
cf1d4549 JY |
205 | FSP_UPD_HEADER FspUpdHeader;\r |
206 | } FSPT_UPD_COMMON;\r | |
207 | \r | |
89f569ae CC |
208 | ///\r |
209 | /// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r | |
210 | ///\r | |
211 | typedef struct {\r | |
212 | ///\r | |
213 | /// FSP_UPD_HEADER Configuration.\r | |
214 | ///\r | |
215 | FSP_UPD_HEADER FspUpdHeader;\r | |
216 | \r | |
217 | ///\r | |
218 | /// FSPT_ARCH_UPD Configuration.\r | |
219 | ///\r | |
220 | FSPT_ARCH_UPD FsptArchUpd;\r | |
221 | } FSPT_UPD_COMMON_FSP22;\r | |
222 | \r | |
6d0ac988 JY |
223 | ///\r |
224 | /// FSPM_UPD_COMMON Configuration.\r | |
225 | ///\r | |
cf1d4549 | 226 | typedef struct {\r |
6d0ac988 JY |
227 | ///\r |
228 | /// FSP_UPD_HEADER Configuration.\r | |
229 | ///\r | |
cf1d4549 | 230 | FSP_UPD_HEADER FspUpdHeader;\r |
6d0ac988 JY |
231 | ///\r |
232 | /// FSPM_ARCH_UPD Configuration.\r | |
233 | ///\r | |
cf1d4549 JY |
234 | FSPM_ARCH_UPD FspmArchUpd;\r |
235 | } FSPM_UPD_COMMON;\r | |
236 | \r | |
6d0ac988 JY |
237 | ///\r |
238 | /// FSPS_UPD_COMMON Configuration.\r | |
239 | ///\r | |
cf1d4549 | 240 | typedef struct {\r |
6d0ac988 JY |
241 | ///\r |
242 | /// FSP_UPD_HEADER Configuration.\r | |
243 | ///\r | |
cf1d4549 JY |
244 | FSP_UPD_HEADER FspUpdHeader;\r |
245 | } FSPS_UPD_COMMON;\r | |
246 | \r | |
89f569ae CC |
247 | ///\r |
248 | /// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above.\r | |
249 | ///\r | |
250 | typedef struct {\r | |
251 | ///\r | |
252 | /// FSP_UPD_HEADER Configuration.\r | |
253 | ///\r | |
254 | FSP_UPD_HEADER FspUpdHeader;\r | |
255 | \r | |
256 | ///\r | |
257 | /// FSPS_ARCH_UPD Configuration.\r | |
258 | ///\r | |
259 | FSPS_ARCH_UPD FspsArchUpd;\r | |
260 | } FSPS_UPD_COMMON_FSP22;\r | |
261 | \r | |
6d0ac988 JY |
262 | ///\r |
263 | /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.\r | |
264 | ///\r | |
cf1d4549 JY |
265 | typedef enum {\r |
266 | ///\r | |
267 | /// This stage is notified when the bootloader completes the\r | |
268 | /// PCI enumeration and the resource allocation for the\r | |
269 | /// PCI devices is complete.\r | |
270 | ///\r | |
271 | EnumInitPhaseAfterPciEnumeration = 0x20,\r | |
272 | ///\r | |
273 | /// This stage is notified just before the bootloader hand-off\r | |
274 | /// to the OS loader.\r | |
275 | ///\r | |
276 | EnumInitPhaseReadyToBoot = 0x40,\r | |
277 | ///\r | |
278 | /// This stage is notified just before the firmware/Preboot\r | |
279 | /// environment transfers management of all system resources\r | |
280 | /// to the OS or next level execution environment.\r | |
281 | ///\r | |
282 | EnumInitPhaseEndOfFirmware = 0xF0\r | |
283 | } FSP_INIT_PHASE;\r | |
284 | \r | |
6d0ac988 JY |
285 | ///\r |
286 | /// Definition of NOTIFY_PHASE_PARAMS.\r | |
287 | ///\r | |
cf1d4549 JY |
288 | typedef struct {\r |
289 | ///\r | |
290 | /// Notification phase used for NotifyPhase API\r | |
291 | ///\r | |
292 | FSP_INIT_PHASE Phase;\r | |
293 | } NOTIFY_PHASE_PARAMS;\r | |
294 | \r | |
f2cdb268 CC |
295 | ///\r |
296 | /// Action definition for FspMultiPhaseSiInit API\r | |
297 | ///\r | |
298 | typedef enum {\r | |
299 | EnumMultiPhaseGetNumberOfPhases = 0x0,\r | |
300 | EnumMultiPhaseExecutePhase = 0x1\r | |
301 | } FSP_MULTI_PHASE_ACTION;\r | |
302 | \r | |
303 | ///\r | |
304 | /// Data structure returned by FSP when bootloader calling\r | |
305 | /// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)\r | |
306 | ///\r | |
307 | typedef struct {\r | |
308 | UINT32 NumberOfPhases;\r | |
309 | UINT32 PhasesExecuted;\r | |
310 | } FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;\r | |
311 | \r | |
312 | ///\r | |
313 | /// FspMultiPhaseSiInit function parameter.\r | |
314 | ///\r | |
315 | /// For action 0 (EnumMultiPhaseGetNumberOfPhases):\r | |
316 | /// - PhaseIndex must be 0.\r | |
317 | /// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS.\r | |
318 | ///\r | |
319 | /// For action 1 (EnumMultiPhaseExecutePhase):\r | |
320 | /// - PhaseIndex will be the phase that will be executed by FSP.\r | |
321 | /// - MultiPhaseParamPtr shall be NULL.\r | |
322 | ///\r | |
323 | typedef struct {\r | |
324 | IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;\r | |
325 | IN UINT32 PhaseIndex;\r | |
326 | IN OUT VOID *MultiPhaseParamPtr;\r | |
327 | } FSP_MULTI_PHASE_PARAMS;\r | |
328 | \r | |
cf1d4549 JY |
329 | #pragma pack()\r |
330 | \r | |
331 | /**\r | |
332 | This FSP API is called soon after coming out of reset and before memory and stack is\r | |
333 | available. This FSP API will load the microcode update, enable code caching for the\r | |
334 | region specified by the boot loader and also setup a temporary stack to be used until\r | |
335 | main memory is initialized.\r | |
336 | \r | |
337 | A hardcoded stack can be set up with the following values, and the "esp" register\r | |
338 | initialized to point to this hardcoded stack.\r | |
339 | 1. The return address where the FSP will return control after setting up a temporary\r | |
340 | stack.\r | |
341 | 2. A pointer to the input parameter structure\r | |
342 | \r | |
343 | However, since the stack is in ROM and not writeable, this FSP API cannot be called\r | |
344 | using the "call" instruction, but needs to be jumped to.\r | |
345 | \r | |
346 | @param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure.\r | |
347 | \r | |
348 | @retval EFI_SUCCESS Temporary RAM was initialized successfully.\r | |
349 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
350 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
351 | @retval EFI_DEVICE_ERROR Temp RAM initialization failed.\r | |
352 | \r | |
353 | If this function is successful, the FSP initializes the ECX and EDX registers to point to\r | |
354 | a temporary but writeable memory range available to the boot loader and returns with\r | |
355 | FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary\r | |
356 | memory range and EDX points to the end of the range. Boot loader is free to use the\r | |
357 | whole range described. Typically the boot loader can reload the ESP register to point\r | |
358 | to the end of this returned range so that it can be used as a standard stack.\r | |
359 | **/\r | |
360 | typedef\r | |
361 | EFI_STATUS\r | |
362 | (EFIAPI *FSP_TEMP_RAM_INIT) (\r | |
363 | IN VOID *FsptUpdDataPtr\r | |
364 | );\r | |
365 | \r | |
366 | /**\r | |
367 | This FSP API is used to notify the FSP about the different phases in the boot process.\r | |
368 | This allows the FSP to take appropriate actions as needed during different initialization\r | |
369 | phases. The phases will be platform dependent and will be documented with the FSP\r | |
370 | release. The current FSP supports two notify phases:\r | |
371 | Post PCI enumeration\r | |
372 | Ready To Boot\r | |
373 | \r | |
374 | @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r | |
375 | \r | |
376 | @retval EFI_SUCCESS The notification was handled successfully.\r | |
377 | @retval EFI_UNSUPPORTED The notification was not called in the proper order.\r | |
378 | @retval EFI_INVALID_PARAMETER The notification code is invalid.\r | |
379 | **/\r | |
380 | typedef\r | |
381 | EFI_STATUS\r | |
382 | (EFIAPI *FSP_NOTIFY_PHASE) (\r | |
383 | IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r | |
384 | );\r | |
385 | \r | |
386 | /**\r | |
387 | This FSP API is called after TempRamInit and initializes the memory.\r | |
388 | This FSP API accepts a pointer to a data structure that will be platform dependent\r | |
389 | and defined for each FSP binary. This will be documented in Integration guide with\r | |
390 | each FSP release.\r | |
391 | After FspMemInit completes its execution, it passes the pointer to the HobList and\r | |
e37bb20c | 392 | returns to the boot loader from where it was called. BootLoader is responsible to\r |
91cc60ba | 393 | migrate its stack and data to Memory.\r |
cf1d4549 JY |
394 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r |
395 | complete the silicon initialization and provides bootloader an opportunity to get\r | |
396 | control after system memory is available and before the temporary RAM is torn down.\r | |
397 | \r | |
91cc60ba | 398 | @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure.\r |
cf1d4549 JY |
399 | @param[out] HobListPtr Pointer to receive the address of the HOB list.\r |
400 | \r | |
401 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r | |
402 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
403 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
404 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
405 | @retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met.\r | |
406 | @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3.\r | |
407 | **/\r | |
408 | typedef\r | |
409 | EFI_STATUS\r | |
410 | (EFIAPI *FSP_MEMORY_INIT) (\r | |
411 | IN VOID *FspmUpdDataPtr,\r | |
412 | OUT VOID **HobListPtr\r | |
413 | );\r | |
414 | \r | |
415 | \r | |
416 | /**\r | |
417 | This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary\r | |
418 | memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure\r | |
419 | that will be platform dependent and defined for each FSP binary. This will be\r | |
420 | documented in Integration Guide.\r | |
421 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r | |
422 | complete the silicon initialization and provides bootloader an opportunity to get\r | |
423 | control after system memory is available and before the temporary RAM is torn down.\r | |
424 | \r | |
425 | @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.\r | |
426 | This structure is normally defined in the Integration Guide.\r | |
427 | And if it is not defined in the Integration Guide, pass NULL.\r | |
428 | \r | |
429 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r | |
430 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
431 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
432 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
433 | **/\r | |
434 | typedef\r | |
435 | EFI_STATUS\r | |
436 | (EFIAPI *FSP_TEMP_RAM_EXIT) (\r | |
437 | IN VOID *TempRamExitParamPtr\r | |
438 | );\r | |
439 | \r | |
440 | \r | |
441 | /**\r | |
442 | This FSP API is called after TempRamExit API.\r | |
443 | FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the\r | |
444 | silicon initialization.\r | |
445 | \r | |
446 | @param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure.\r | |
447 | If NULL, FSP will use the default parameters.\r | |
448 | \r | |
449 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r | |
450 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
451 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
452 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
91cc60ba | 453 | @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r |
cf1d4549 JY |
454 | **/\r |
455 | typedef\r | |
456 | EFI_STATUS\r | |
457 | (EFIAPI *FSP_SILICON_INIT) (\r | |
458 | IN VOID *FspsUpdDataPtr\r | |
459 | );\r | |
460 | \r | |
f2cdb268 CC |
461 | /**\r |
462 | This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase.\r | |
463 | This FSP API provides multi-phase silicon initialization; which brings greater modularity\r | |
464 | beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an\r | |
465 | extra API to FSP-S. This allows the bootloader to add board specific initialization steps\r | |
466 | throughout the SiliconInit flow as needed.\r | |
467 | \r | |
468 | @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:\r | |
469 | FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain\r | |
470 | how many phases supported by FSP.\r | |
471 | For action - EnumMultiPhaseExecutePhase:\r | |
472 | FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.\r | |
473 | @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r | |
474 | @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r | |
475 | @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r | |
476 | @retval EFI_DEVICE_ERROR FSP initialization failed.\r | |
477 | @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r | |
478 | **/\r | |
479 | typedef\r | |
480 | EFI_STATUS\r | |
481 | (EFIAPI *FSP_MULTI_PHASE_SI_INIT) (\r | |
482 | IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr\r | |
483 | );\r | |
484 | \r | |
cf1d4549 | 485 | #endif\r |