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IntelFsp2WrapperPkg SecFspWrapperPlatformSecLibSample: Convert ASM to NASM
[mirror_edk2.git] / IntelFsp2WrapperPkg / Library / SecFspWrapperPlatformSecLibSample / Ia32 / SecEntry.nasm
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LG		 1;------------------------------------------------------------------------------\r
2;\r
3; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
4; This program and the accompanying materials\r
5; are licensed and made available under the terms and conditions of the BSD License\r
6; which accompanies this distribution. The full text of the license may be found at\r
7; http://opensource.org/licenses/bsd-license.php.\r
8;\r
9; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11;\r
12; Module Name:\r
13;\r
14; SecEntry.asm\r
15;\r
16; Abstract:\r
17;\r
18; This is the code that goes from real-mode to protected mode.\r
19; It consumes the reset vector, calls TempRamInit API from FSP binary.\r
20;\r
21;------------------------------------------------------------------------------\r
22\r
23#include "Fsp.h"\r
24\r
25SECTION .text\r
26\r
27extern ASM_PFX(CallPeiCoreEntryPoint)\r
28extern ASM_PFX(FsptUpdDataPtr)\r
29\r
30; Pcds\r
31extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))\r
32\r
33;----------------------------------------------------------------------------\r
34;\r
35; Procedure: _ModuleEntryPoint\r
36;\r
37; Input: None\r
38;\r
39; Output: None\r
40;\r
41; Destroys: Assume all registers\r
42;\r
43; Description:\r
44;\r
45; Transition to non-paged flat-model protected mode from a\r
46; hard-coded GDT that provides exactly two descriptors.\r
47; This is a bare bones transition to protected mode only\r
48; used for a while in PEI and possibly DXE.\r
49;\r
50; After enabling protected mode, a far jump is executed to\r
51; transfer to PEI using the newly loaded GDT.\r
52;\r
53; Return: None\r
54;\r
55; MMX Usage:\r
56; MM0 = BIST State\r
57; MM5 = Save time-stamp counter value high32bit\r
58; MM6 = Save time-stamp counter value low32bit.\r
59;\r
60;----------------------------------------------------------------------------\r
61\r
62BITS 16\r
63align 4\r
64global ASM_PFX(ModuleEntryPoint)\r
65ASM_PFX(ModuleEntryPoint):\r
66 fninit ; clear any pending Floating point exceptions\r
67 ;\r
68 ; Store the BIST value in mm0\r
69 ;\r
70 movd mm0, eax\r
71\r
72 ;\r
73 ; Save time-stamp counter value\r
74 ; rdtsc load 64bit time-stamp counter to EDX:EAX\r
75 ;\r
76 rdtsc\r
77 movd mm5, edx\r
78 movd mm6, eax\r
79\r
80 ;\r
81 ; Load the GDT table in GdtDesc\r
82 ;\r
83 mov esi, GdtDesc\r
84 DB 66h\r
85 lgdt [cs:si]\r
86\r
87 ;\r
88 ; Transition to 16 bit protected mode\r
89 ;\r
90 mov eax, cr0 ; Get control register 0\r
91 or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)\r
92 mov cr0, eax ; Activate protected mode\r
93\r
94 mov eax, cr4 ; Get control register 4\r
95 or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
96 mov cr4, eax\r
97\r
98 ;\r
99 ; Now we're in 16 bit protected mode\r
100 ; Set up the selectors for 32 bit protected mode entry\r
101 ;\r
102 mov ax, SYS_DATA_SEL\r
103 mov ds, ax\r
104 mov es, ax\r
105 mov fs, ax\r
106 mov gs, ax\r
107 mov ss, ax\r
108\r
109 ;\r
110 ; Transition to Flat 32 bit protected mode\r
111 ; The jump to a far pointer causes the transition to 32 bit mode\r
112 ;\r
113 mov esi, ProtectedModeEntryLinearAddress\r
114 jmp dword far [cs:si]\r
115\r
116;----------------------------------------------------------------------------\r
117;\r
118; Procedure: ProtectedModeEntryPoint\r
119;\r
120; Input: None\r
121;\r
122; Output: None\r
123;\r
124; Destroys: Assume all registers\r
125;\r
126; Description:\r
127;\r
128; This function handles:\r
129; Call two basic APIs from FSP binary\r
130; Initializes stack with some early data (BIST, PEI entry, etc)\r
131;\r
132; Return: None\r
133;\r
134;----------------------------------------------------------------------------\r
135\r
136BITS 32\r
137align 4\r
138ProtectedModeEntryPoint:\r
139\r
140 ; Find the fsp info header\r
141 mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]\r
142\r
143 mov eax, dword [edi + FVH_SIGINATURE_OFFSET]\r
144 cmp eax, FVH_SIGINATURE_VALID_VALUE\r
145 jnz FspHeaderNotFound\r
146\r
147 xor eax, eax\r
148 mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]\r
149 cmp ax, 0\r
150 jnz FspFvExtHeaderExist\r
151\r
152 xor eax, eax\r
153 mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header\r
154 add edi, eax\r
155 jmp FspCheckFfsHeader\r
156\r
157FspFvExtHeaderExist:\r
158 add edi, eax\r
159 mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header\r
160 add edi, eax\r
161\r
162 ; Round up to 8 byte alignment\r
163 mov eax, edi\r
164 and al, 07h\r
165 jz FspCheckFfsHeader\r
166\r
167 and edi, 0FFFFFFF8h\r
168 add edi, 08h\r
169\r
170FspCheckFfsHeader:\r
171 ; Check the ffs guid\r
172 mov eax, dword [edi]\r
173 cmp eax, FSP_HEADER_GUID_DWORD1\r
174 jnz FspHeaderNotFound\r
175\r
176 mov eax, dword [edi + 4]\r
177 cmp eax, FSP_HEADER_GUID_DWORD2\r
178 jnz FspHeaderNotFound\r
179\r
180 mov eax, dword [edi + 8]\r
181 cmp eax, FSP_HEADER_GUID_DWORD3\r
182 jnz FspHeaderNotFound\r
183\r
184 mov eax, dword [edi + 0Ch]\r
185 cmp eax, FSP_HEADER_GUID_DWORD4\r
186 jnz FspHeaderNotFound\r
187\r
188 add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header\r
189\r
190 ; Check the section type as raw section\r
191 mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]\r
192 cmp al, 019h\r
193 jnz FspHeaderNotFound\r
194\r
195 add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header\r
196 jmp FspHeaderFound\r
197\r
198FspHeaderNotFound:\r
199 jmp $\r
200\r
201FspHeaderFound:\r
202 ; Get the fsp TempRamInit Api address\r
203 mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]\r
204 add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]\r
205\r
206 ; Setup the hardcode stack\r
207 mov esp, TempRamInitStack\r
208\r
209 ; Call the fsp TempRamInit Api\r
210 jmp eax\r
211\r
212TempRamInitDone:\r
213 cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.\r
214 je CallSecFspInit ;If microcode not found, don't hang, but continue.\r
215\r
216 cmp eax, 0 ;Check if EFI_SUCCESS retuned.\r
217 jnz FspApiFailed\r
218\r
219 ; ECX: start of range\r
220 ; EDX: end of range\r
221CallSecFspInit:\r
222 xor eax, eax\r
223 mov esp, edx\r
224\r
225 ; Align the stack at DWORD\r
226 add esp, 3\r
227 and esp, 0FFFFFFFCh\r
228\r
229 push edx\r
230 push ecx\r
231 push eax ; zero - no hob list yet\r
232 call ASM_PFX(CallPeiCoreEntryPoint)\r
233\r
234FspApiFailed:\r
235 jmp $\r
236\r
237align 10h\r
238TempRamInitStack:\r
239 DD TempRamInitDone\r
240 DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams\r
241\r
242;\r
243; ROM-based Global-Descriptor Table for the Tiano PEI Phase\r
244;\r
245align 16\r
246global ASM_PFX(BootGdtTable)\r
247\r
248;\r
249; GDT[0]: 0x00: Null entry, never used.\r
250;\r
251NULL_SEL EQU $ - GDT_BASE ; Selector [0]\r
252GDT_BASE:\r
253ASM_PFX(BootGdtTable):\r
254 DD 0\r
255 DD 0\r
256;\r
257; Linear data segment descriptor\r
258;\r
259LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]\r
260 DW 0FFFFh ; limit 0xFFFFF\r
261 DW 0 ; base 0\r
262 DB 0\r
263 DB 092h ; present, ring 0, data, expand-up, writable\r
264 DB 0CFh ; page-granular, 32-bit\r
265 DB 0\r
266;\r
267; Linear code segment descriptor\r
268;\r
269LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]\r
270 DW 0FFFFh ; limit 0xFFFFF\r
271 DW 0 ; base 0\r
272 DB 0\r
273 DB 09Bh ; present, ring 0, data, expand-up, not-writable\r
274 DB 0CFh ; page-granular, 32-bit\r
275 DB 0\r
276;\r
277; System data segment descriptor\r
278;\r
279SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]\r
280 DW 0FFFFh ; limit 0xFFFFF\r
281 DW 0 ; base 0\r
282 DB 0\r
283 DB 093h ; present, ring 0, data, expand-up, not-writable\r
284 DB 0CFh ; page-granular, 32-bit\r
285 DB 0\r
286\r
287;\r
288; System code segment descriptor\r
289;\r
290SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]\r
291 DW 0FFFFh ; limit 0xFFFFF\r
292 DW 0 ; base 0\r
293 DB 0\r
294 DB 09Ah ; present, ring 0, data, expand-up, writable\r
295 DB 0CFh ; page-granular, 32-bit\r
296 DB 0\r
297;\r
298; Spare segment descriptor\r
299;\r
300SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]\r
301 DW 0FFFFh ; limit 0xFFFFF\r
302 DW 0 ; base 0\r
303 DB 0Eh ; Changed from F000 to E000.\r
304 DB 09Bh ; present, ring 0, code, expand-up, writable\r
305 DB 00h ; byte-granular, 16-bit\r
306 DB 0\r
307;\r
308; Spare segment descriptor\r
309;\r
310SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]\r
311 DW 0FFFFh ; limit 0xFFFF\r
312 DW 0 ; base 0\r
313 DB 0\r
314 DB 093h ; present, ring 0, data, expand-up, not-writable\r
315 DB 00h ; byte-granular, 16-bit\r
316 DB 0\r
317\r
318;\r
319; Spare segment descriptor\r
320;\r
321SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]\r
322 DW 0 ; limit 0\r
323 DW 0 ; base 0\r
324 DB 0\r
325 DB 0 ; present, ring 0, data, expand-up, writable\r
326 DB 0 ; page-granular, 32-bit\r
327 DB 0\r
328GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes\r
329\r
330;\r
331; GDT Descriptor\r
332;\r
333GdtDesc: ; GDT descriptor\r
334 DW GDT_SIZE - 1 ; GDT limit\r
335 DD GDT_BASE ; GDT base address\r
336\r
337\r
338ProtectedModeEntryLinearAddress:\r
339ProtectedModeEntryLinear:\r
340 DD ProtectedModeEntryPoint ; Offset of our 32 bit code\r
341 DW LINEAR_CODE_SEL\r
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