rename XXXDflt to XXXDefault (expand for better readability)

[mirror_edk2.git] / IntelFspPkg / Include / FspApi.h

/** @file\r
  Intel FSP API definition from Intel Firmware Support Package External\r
  Architecture Specification, April 2014, revision 001.\r
\r
  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _FSP_API_H_\r
#define _FSP_API_H_\r
\r
#define FSP_STATUS EFI_STATUS\r
#define FSPAPI EFIAPI\r
\r
/**\r
  FSP Init continuation function prototype.\r
  Control will be returned to this callback function after FspInit API call.\r
\r
  @param[in] Status Status of the FSP INIT API.\r
  @param[in] HobBufferPtr Pointer to the HOB data structure defined in the PI specification.\r
**/\r
typedef\r
VOID\r
(* CONTINUATION_PROC) (\r
  IN EFI_STATUS Status,\r
  IN VOID       *HobListPtr\r
  );\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
  ///\r
  /// Base address of the microcode region.\r
  ///\r
  UINT32              MicrocodeRegionBase;\r
  ///\r
  /// Length of the microcode region.\r
  ///\r
  UINT32              MicrocodeRegionLength;\r
  ///\r
  /// Base address of the cacheable flash region.\r
  ///\r
  UINT32              CodeRegionBase;\r
  ///\r
  /// Length of the cacheable flash region.\r
  ///\r
  UINT32              CodeRegionLength;\r
} FSP_TEMP_RAM_INIT_PARAMS;\r
\r
typedef struct {\r
  ///\r
  /// Non-volatile storage buffer pointer.\r
  ///\r
  VOID               *NvsBufferPtr;\r
  ///\r
  /// Runtime buffer pointer\r
  ///\r
  VOID               *RtBufferPtr;\r
  ///\r
  /// Continuation function address\r
  ///\r
  CONTINUATION_PROC   ContinuationFunc;\r
} FSP_INIT_PARAMS;\r
\r
typedef struct {\r
  ///\r
  /// Stack top pointer used by the bootloader.\r
  /// The new stack frame will be set up at this location after FspInit API call.\r
  ///\r
  UINT32             *StackTop;\r
  ///\r
  /// Current system boot mode.\r
  ///\r
  UINT32              BootMode;\r
  ///\r
  /// User platform configuraiton data region pointer.\r
  ///\r
  VOID               *UpdDataRgnPtr;\r
  ///\r
  /// Reserved\r
  ///\r
  UINT32              Reserved[7];\r
} FSP_INIT_RT_COMMON_BUFFER;\r
\r
typedef enum {\r
  ///\r
  /// Notification code for post PCI enuermation\r
  ///\r
  EnumInitPhaseAfterPciEnumeration = 0x20,\r
  ///\r
  /// Notification code before transfering control to the payload\r
  ///\r
  EnumInitPhaseReadyToBoot         = 0x40\r
} FSP_INIT_PHASE;\r
\r
typedef struct {\r
  ///\r
  /// Notification phase used for NotifyPhase API\r
  ///\r
  FSP_INIT_PHASE     Phase;\r
} NOTIFY_PHASE_PARAMS;\r
\r
typedef struct {\r
  ///\r
  /// Non-volatile storage buffer pointer.\r
  ///\r
  VOID               *NvsBufferPtr;\r
  ///\r
  /// Runtime buffer pointer\r
  ///\r
  VOID               *RtBufferPtr;\r
  ///\r
  /// Pointer to the HOB data structure defined in the PI specification\r
  ///\r
  VOID               **HobListPtr;\r
} FSP_MEMORY_INIT_PARAMS;\r
\r
#pragma pack()\r
\r
/**\r
  This FSP API is called soon after coming out of reset and before memory and stack is\r
  available. This FSP API will load the microcode update, enable code caching for the\r
  region specified by the boot loader and also setup a temporary stack to be used until\r
  main memory is initialized.\r
\r
  A hardcoded stack can be set up with the following values, and the "esp" register\r
  initialized to point to this hardcoded stack.\r
  1. The return address where the FSP will return control after setting up a temporary\r
     stack.\r
  2. A pointer to the input parameter structure\r
\r
  However, since the stack is in ROM and not writeable, this FSP API cannot be called\r
  using the "call" instruction, but needs to be jumped to.\r
\r
  @param[in] TempRaminitParamPtr Address pointer to the FSP_TEMP_RAM_INIT_PARAMS structure.\r
\r
  @retval EFI_SUCCESS           Temp RAM was initialized successfully.\r
  @retval EFI_INVALID_PARAMETER Input parameters are invalid..\r
  @retval EFI_NOT_FOUND         No valid microcode was found in the microcode region.\r
  @retval EFI_UNSUPPORTED       The FSP calling conditions were not met.\r
  @retval EFI_DEVICE_ERROR      Temp RAM initialization failed.\r
\r
  If this function is successful, the FSP initializes the ECX and EDX registers to point to\r
  a temporary but writeable memory range available to the boot loader and returns with\r
  FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary\r
  memory range and EDX points to the end of the range. Boot loader is free to use the\r
  whole range described. Typically the boot loader can reload the ESP register to point\r
  to the end of this returned range so that it can be used as a standard stack.\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *FSP_TEMP_RAM_INIT) (\r
  IN FSP_TEMP_RAM_INIT_PARAMS *FspTempRamInitPtr\r
  );\r
\r
/**\r
  This FSP API is called after TempRamInitEntry. This FSP API initializes the memory,\r
  the CPU and the chipset to enable normal operation of these devices. This FSP API\r
  accepts a pointer to a data structure that will be platform dependent and defined for\r
  each FSP binary. This will be documented in the Integration Guide for each FSP\r
  release.\r
  The boot loader provides a continuation function as a parameter when calling FspInit.\r
  After FspInit completes its execution, it does not return to the boot loader from where\r
  it was called but instead returns control to the boot loader by calling the continuation\r
  function which is passed to FspInit as an argument.\r
\r
  @param[in] FspInitParamPtr Address pointer to the FSP_INIT_PARAMS structure.\r
\r
  @retval EFI_SUCCESS           FSP execution environment was initialized successfully.\r
  @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
  @retval EFI_UNSUPPORTED       The FSP calling conditions were not met.\r
  @retval EFI_DEVICE_ERROR      FSP initialization failed.\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *FSP_INIT) (\r
  IN OUT FSP_INIT_PARAMS *FspInitParamPtr\r
  );\r
\r
#define FSP_FSP_INIT FSP_INIT\r
\r
/**\r
  This FSP API is used to notify the FSP about the different phases in the boot process.\r
  This allows the FSP to take appropriate actions as needed during different initialization\r
  phases. The phases will be platform dependent and will be documented with the FSP\r
  release. The current FSP supports two notify phases:\r
    Post PCI enumeration\r
    Ready To Boot\r
\r
  @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS\r
\r
  @retval EFI_SUCCESS           The notification was handled successfully.\r
  @retval EFI_UNSUPPORTED       The notification was not called in the proper order.\r
  @retval EFI_INVALID_PARAMETER The notification code is invalid.\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *FSP_NOTIFY_PHASE) (\r
  IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r
  );\r
\r
/**\r
  This FSP API is called after TempRamInit and initializes the memory.\r
  This FSP API accepts a pointer to a data structure that will be platform dependent\r
  and defined for each FSP binary. This will be documented in Integration guide with\r
  each FSP release.\r
  After FspMemInit completes its execution, it passes the pointer to the HobList and\r
  returns to the boot loader from where it was called. Bootloader is responsible to \r