Fsp1.1 update.
[mirror_edk2.git] / IntelFspPkg / IntelFspPkg.dec
CommitLineData
a33a2f62 1## @file\r
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2# Provides driver and definitions to build fsp in EDKII bios.\r
3#\r
b34eb190 4# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
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5# This program and the accompanying materials are licensed and made available under\r
6# the terms and conditions of the BSD License that accompanies this distribution.\r
7# The full text of the license may be found at\r
8# http://opensource.org/licenses/bsd-license.php.\r
9#\r
10# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12#\r
13##\r
14\r
15[Defines]\r
16 DEC_SPECIFICATION = 0x00010005\r
17 PACKAGE_NAME = IntelFspPkg\r
18 PACKAGE_GUID = 444C6CDF-55BD-4744-8F74-AE98B003B955\r
19 PACKAGE_VERSION = 0.1\r
20\r
21[Includes]\r
22 Include\r
c8ec22a2 23 Include/Private\r
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24 \r
25[LibraryClasses]\r
26 ## @libraryclass Provides cache-as-ram support.\r
27 CacheAsRamLib|IntelFspPkg/Include/Library/CacheAsRamLib.h\r
28\r
29 ## @libraryclass Provides cache setting on MTRR.\r
30 CacheLib|IntelFspPkg/Include/Library/CacheLib.h\r
31\r
32 ## @libraryclass Provides debug device abstraction.\r
33 DebugDeviceLib|IntelFspPkg/Include/Library/DebugDeviceLib.h\r
34\r
35 ## @libraryclass Provides FSP related services.\r
36 FspCommonLib|IntelFspPkg/Include/Library/FspCommonLib.h\r
37\r
38 ## @libraryclass Provides FSP platform related actions.\r
39 FspPlatformLib|IntelFspPkg/Include/Library/FspPlatformLib.h\r
40\r
41 ## @libraryclass Provides FSP switch stack function.\r
42 FspSwitchStackLib|IntelFspPkg/Include/Library/FspSwitchStackLib.h\r
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43\r
44[Guids]\r
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45 #\r
46 # GUID defined in package\r
47 #\r
48 gIntelFspPkgTokenSpaceGuid = { 0x834c0c5f, 0xadb3, 0x4372, { 0xae, 0xeb, 0x03, 0xe4, 0xe9, 0xe6, 0xc5, 0x91 } }\r
49\r
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50 # Guid define in FSP EAS\r
51 gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }\r
52 gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
53 gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
54 gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
55\r
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56 # Guid defined by platform\r
57 gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }\r
58 gFspReservedMemoryResourceHobGfxGuid = { 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } }\r
59 gFspReservedMemoryResourceHobMiscGuid = { 0x00d6b14b, 0x7dd0, 0x4062, { 0x88, 0x21, 0xe5, 0xf9, 0x6a, 0x2a, 0x1b, 0x00 } }\r
60\r
61[PcdsFixedAtBuild]\r
62 gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00108|UINT32|0x00000001\r
63 gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001\r
64 gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT32|0x10001002\r
65 gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x1000|UINT32|0x10001003\r
66 gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry | 32|UINT32|0x00002001\r
67 gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry | 5|UINT32|0x00002002\r
68\r
69[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]\r
70 gIntelFspPkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000\r
71 gIntelFspPkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT32|0x46530100\r