[mirror_edk2.git] / IntelSiliconPkg / Feature / VTd / PlatformVTdInfoSamplePei / PlatformVTdInfoSamplePei.c

/** @file\r
  Platform VTd Info Sample PEI driver.\r
\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <PiPei.h>\r
\r
#include <Ppi/VtdInfo.h>\r
\r
#include <Library/PeiServicesLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/IoLib.h>\r
\r
#define R_SA_MCHBAR               (0x48)\r
#define R_SA_GGC                  (0x50)\r
#define N_SKL_SA_GGC_GGMS_OFFSET  (0x6)\r
#define B_SKL_SA_GGC_GGMS_MASK    (0xc0)\r
#define N_SKL_SA_GGC_GMS_OFFSET   (0x8)\r
#define B_SKL_SA_GGC_GMS_MASK     (0xff00)\r
#define V_SKL_SA_GGC_GGMS_8MB     3\r
#define R_SA_TOLUD                (0xbc)\r
\r
#define R_SA_MCHBAR_VTD1_OFFSET  0x5400  ///< HW UNIT for IGD\r
#define R_SA_MCHBAR_VTD2_OFFSET  0x5410  ///< HW UNIT for all other - PEG, USB, SATA etc\r
\r
typedef struct {\r
  EFI_ACPI_DMAR_HEADER                         DmarHeader;\r
  //\r
  // VTd engine 1 - integrated graphic\r
  //\r
  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd1;\r
  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Drhd11;\r
  EFI_ACPI_DMAR_PCI_PATH                       Drhd111;\r
  //\r
  // VTd engine 2 - all rest\r
  //\r
  EFI_ACPI_DMAR_DRHD_HEADER                    Drhd2;\r
  //\r
  // RMRR 1 - integrated graphic\r
  //\r
  EFI_ACPI_DMAR_RMRR_HEADER                    Rmrr1;\r
  EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER  Rmrr11;\r
  EFI_ACPI_DMAR_PCI_PATH                       Rmrr111;\r
} MY_VTD_INFO_PPI;\r
\r
MY_VTD_INFO_PPI  mPlatformVTdSample = {\r
  { // DmarHeader\r
    { // Header\r
      EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
      sizeof(MY_VTD_INFO_PPI),\r
      EFI_ACPI_DMAR_REVISION,\r
    },\r
    0x26, // HostAddressWidth\r
  },\r
\r
  { // Drhd1\r
    { // Header\r
      EFI_ACPI_DMAR_TYPE_DRHD,\r
      sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
    },\r
    0, // Flags\r
    0, // Reserved\r
    0, // SegmentNumber\r
    0xFED90000 // RegisterBaseAddress -- TO BE PATCHED\r
  },\r
  { // Drhd11\r
    EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
    sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
      sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
    0, // Reserved2\r
    0, // EnumerationId\r
    0  // StartBusNumber\r
  },\r
  { // Drhd111\r
    2,  // Device\r
    0   // Function\r
  },\r
\r
  { // Drhd2\r
    { // Header\r
      EFI_ACPI_DMAR_TYPE_DRHD,\r
      sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
    },\r
    EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
    0, // Reserved\r
    0, // SegmentNumber\r
    0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
  },\r
\r
  { // Rmrr1\r
    { // Header\r
      EFI_ACPI_DMAR_TYPE_RMRR,\r
      sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
        sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
    },\r
    {0}, // Reserved\r
    0, // SegmentNumber\r
    0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED\r
    0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED\r
  },\r
  { // Rmrr11\r
    EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
    sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
      sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
    0, // Reserved2\r
    0, // EnumerationId\r
    0  // StartBusNumber\r
  },\r
  { // Rmrr111\r
    2,  // Device\r
    0   // Function\r
  },\r
};\r
\r
EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {\r
  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
  &gEdkiiVTdInfoPpiGuid,\r
  &mPlatformVTdSample\r
};\r
\r
/**\r
  Patch Graphic UMA address in RMRR and base address.\r
**/\r
VOID\r
PatchDmar (\r
  VOID\r
  )\r
{\r
  UINT32              MchBar;\r
  UINT16              IgdMode;\r
  UINT16              GttMode;\r
  UINT32              IgdMemSize;\r
  UINT32              GttMemSize;\r
\r
  ///\r
  /// Calculate IGD memsize\r
  ///\r
  IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;\r
  if (IgdMode < 0xF0) {\r
    IgdMemSize = IgdMode * 32 * (1024) * (1024);\r
  } else {\r
    IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);\r
  }\r
\r
  ///\r
  /// Calculate GTT mem size\r
  ///\r
  GttMemSize = 0;\r
  GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;\r
  if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {\r
    GttMemSize = (1 << GttMode) * (1024) * (1024);\r
  }\r
\r
  mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress  = (PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSize;\r
  mPlatformVTdSample.Rmrr1.ReservedMemoryRegionLimitAddress = mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;\r
\r
  ///\r
  /// Update DRHD structures of DmarTable\r
  ///\r
  MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
  mPlatformVTdSample.Drhd1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);\r
  mPlatformVTdSample.Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
}\r
\r
/**\r
  Platform VTd Info sample driver.\r
\r
  @param[in] FileHandle  Handle of the file being invoked.\r
  @param[in] PeiServices Describes the list of possible PEI Services.\r
\r
  @retval EFI_SUCCESS if it completed successfully.\r
**/\r
EFI_STATUS\r
EFIAPI\r
PlatformVTdInfoSampleInitialize (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  PatchDmar ();\r
\r
  Status = PeiServicesInstallPpi (&mPlatformVTdInfoSampleDesc);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r
Commit	Line	Data
53269009 JY	1	/** @file\r
	2	Platform VTd Info Sample PEI driver.\r
	3	\r
	4	Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#include <PiPei.h>\r
	16	\r
4084ccfa	17	#include <Ppi/VtdInfo.h>\r
53269009 JY	18	\r
	19	#include <Library/PeiServicesLib.h>\r
	20	#include <Library/DebugLib.h>\r
70dc3ec5 JY	21	#include <Library/PciLib.h>\r
	22	#include <Library/IoLib.h>\r
	23	\r
	24	#define R_SA_MCHBAR (0x48)\r
	25	#define R_SA_GGC (0x50)\r
	26	#define N_SKL_SA_GGC_GGMS_OFFSET (0x6)\r
	27	#define B_SKL_SA_GGC_GGMS_MASK (0xc0)\r
	28	#define N_SKL_SA_GGC_GMS_OFFSET (0x8)\r
	29	#define B_SKL_SA_GGC_GMS_MASK (0xff00)\r
	30	#define V_SKL_SA_GGC_GGMS_8MB 3\r
	31	#define R_SA_TOLUD (0xbc)\r
	32	\r
	33	#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT for IGD\r
	34	#define R_SA_MCHBAR_VTD2_OFFSET 0x5410 ///< HW UNIT for all other - PEG, USB, SATA etc\r
53269009 JY	35	\r
53269009 JY	36	typedef struct {\r
70dc3ec5 JY	37	EFI_ACPI_DMAR_HEADER DmarHeader;\r
	38	//\r
	39	// VTd engine 1 - integrated graphic\r
	40	//\r
	41	EFI_ACPI_DMAR_DRHD_HEADER Drhd1;\r
	42	EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Drhd11;\r
	43	EFI_ACPI_DMAR_PCI_PATH Drhd111;\r
	44	//\r
	45	// VTd engine 2 - all rest\r
	46	//\r
	47	EFI_ACPI_DMAR_DRHD_HEADER Drhd2;\r
	48	//\r
	49	// RMRR 1 - integrated graphic\r
	50	//\r
	51	EFI_ACPI_DMAR_RMRR_HEADER Rmrr1;\r
	52	EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Rmrr11;\r
	53	EFI_ACPI_DMAR_PCI_PATH Rmrr111;\r
53269009 JY	54	} MY_VTD_INFO_PPI;\r
	55	\r
	56	MY_VTD_INFO_PPI mPlatformVTdSample = {\r
70dc3ec5 JY	57	{ // DmarHeader\r
	58	{ // Header\r
	59	EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE,\r
	60	sizeof(MY_VTD_INFO_PPI),\r
	61	EFI_ACPI_DMAR_REVISION,\r
	62	},\r
	63	0x26, // HostAddressWidth\r
	64	},\r
	65	\r
	66	{ // Drhd1\r
	67	{ // Header\r
	68	EFI_ACPI_DMAR_TYPE_DRHD,\r
	69	sizeof(EFI_ACPI_DMAR_DRHD_HEADER) +\r
	70	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	71	sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
	72	},\r
	73	0, // Flags\r
	74	0, // Reserved\r
	75	0, // SegmentNumber\r
	76	0xFED90000 // RegisterBaseAddress -- TO BE PATCHED\r
	77	},\r
	78	{ // Drhd11\r
	79	EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
	80	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	81	sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
	82	0, // Reserved2\r
	83	0, // EnumerationId\r
	84	0 // StartBusNumber\r
	85	},\r
	86	{ // Drhd111\r
	87	2, // Device\r
	88	0 // Function\r
	89	},\r
	90	\r
	91	{ // Drhd2\r
	92	{ // Header\r
	93	EFI_ACPI_DMAR_TYPE_DRHD,\r
	94	sizeof(EFI_ACPI_DMAR_DRHD_HEADER)\r
	95	},\r
	96	EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags\r
	97	0, // Reserved\r
	98	0, // SegmentNumber\r
	99	0xFED91000 // RegisterBaseAddress -- TO BE PATCHED\r
	100	},\r
	101	\r
	102	{ // Rmrr1\r
	103	{ // Header\r
	104	EFI_ACPI_DMAR_TYPE_RMRR,\r
	105	sizeof(EFI_ACPI_DMAR_RMRR_HEADER) +\r
	106	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	107	sizeof(EFI_ACPI_DMAR_PCI_PATH)\r
	108	},\r
	109	{0}, // Reserved\r
	110	0, // SegmentNumber\r
	111	0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED\r
	112	0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED\r
	113	},\r
	114	{ // Rmrr11\r
	115	EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT,\r
	116	sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) +\r
	117	sizeof(EFI_ACPI_DMAR_PCI_PATH),\r
	118	0, // Reserved2\r
	119	0, // EnumerationId\r
	120	0 // StartBusNumber\r
121	},\r
122	{ // Rmrr111\r
123	2, // Device\r
124	0 // Function\r
125	},\r
53269009 JY	126	};\r
	127	\r
	128	EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc = {\r
	129	(EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
	130	&gEdkiiVTdInfoPpiGuid,\r
	131	&mPlatformVTdSample\r
	132	};\r
	133	\r
70dc3ec5 JY	134	/**\r
	135	Patch Graphic UMA address in RMRR and base address.\r
	136	**/\r
	137	VOID\r
	138	PatchDmar (\r
	139	VOID\r
	140	)\r
	141	{\r
	142	UINT32 MchBar;\r
	143	UINT16 IgdMode;\r
	144	UINT16 GttMode;\r
	145	UINT32 IgdMemSize;\r
	146	UINT32 GttMemSize;\r
	147	\r
	148	///\r
	149	/// Calculate IGD memsize\r
	150	///\r
	151	IgdMode = ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;\r
	152	if (IgdMode < 0xF0) {\r
	153	IgdMemSize = IgdMode * 32 * (1024) * (1024);\r
	154	} else {\r
	155	IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);\r
	156	}\r
	157	\r
	158	///\r
	159	/// Calculate GTT mem size\r
	160	///\r
	161	GttMemSize = 0;\r
c13cb4ae	162	GttMode = (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;\r
70dc3ec5 JY	163	if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {\r
	164	GttMemSize = (1 << GttMode) * (1024) * (1024);\r
	165	}\r
	166	\r
	167	mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress = (PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemSize;\r
	168	mPlatformVTdSample.Rmrr1.ReservedMemoryRegionLimitAddress = mPlatformVTdSample.Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1;\r
	169	\r
	170	///\r
	171	/// Update DRHD structures of DmarTable\r
	172	///\r
	173	MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;\r
	174	mPlatformVTdSample.Drhd1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);\r
	175	mPlatformVTdSample.Drhd2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);\r
	176	}\r
	177	\r
53269009 JY	178	/**\r
	179	Platform VTd Info sample driver.\r
	180	\r
	181	@param[in] FileHandle Handle of the file being invoked.\r
	182	@param[in] PeiServices Describes the list of possible PEI Services.\r
	183	\r
	184	@retval EFI_SUCCESS if it completed successfully.\r
	185	**/\r
	186	EFI_STATUS\r
	187	EFIAPI\r
	188	PlatformVTdInfoSampleInitialize (\r
	189	IN EFI_PEI_FILE_HANDLE FileHandle,\r
	190	IN CONST EFI_PEI_SERVICES **PeiServices\r
	191	)\r
	192	{\r
	193	EFI_STATUS Status;\r
	194	\r
70dc3ec5 JY	195	PatchDmar ();\r
70dc3ec5 JY	196	\r
53269009 JY	197	Status = PeiServicesInstallPpi (&mPlatformVTdInfoSampleDesc);\r
	198	ASSERT_EFI_ERROR (Status);\r
	199	\r
	200	return Status;\r
	201	}\r