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7e74fd57 JY |
1 | /** @file\r |
2 | IGD OpRegion definition from Intel Integrated Graphics Device OpRegion\r | |
3 | Specification.\r | |
4 | \r | |
5 | https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf\r | |
6 | \r | |
7 | There are some mismatch between the specification and the implementation.\r | |
8 | The definition follows the latest implementation.\r | |
9 | 1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]\r | |
10 | 2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]\r | |
11 | 3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]\r | |
5c66efd0 | 12 | 4) INTEL_IGD_OPREGION_VBT.RVBT[0x1800] Size is 6KB\r |
7e74fd57 JY |
13 | \r |
14 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
15 | This program and the accompanying materials\r | |
16 | are licensed and made available under the terms and conditions of the BSD License\r | |
17 | which accompanies this distribution. The full text of the license may be found at\r | |
18 | http://opensource.org/licenses/bsd-license.php\r | |
19 | \r | |
20 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
21 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
22 | \r | |
23 | **/\r | |
24 | #ifndef _IGD_OPREGION_H_\r | |
25 | #define _IGD_OPREGION_H_\r | |
26 | \r | |
27 | /**\r | |
5c66efd0 MG |
28 | OpRegion structures:\r |
29 | Sub-structures define the different parts of the OpRegion followed by the\r | |
30 | main structure representing the entire OpRegion.\r | |
7e74fd57 | 31 | \r |
5c66efd0 MG |
32 | @note: These structures are packed to 1 byte offsets because the exact\r |
33 | data location is required by the supporting design specification due to\r | |
34 | the fact that the data is used by ASL and Graphics driver code compiled\r | |
35 | separately.\r | |
7e74fd57 JY |
36 | **/\r |
37 | #pragma pack(1)\r | |
38 | ///\r | |
5c66efd0 MG |
39 | /// OpRegion header (mailbox 0) structure. The OpRegion Header is used to\r |
40 | /// identify a block of memory as the graphics driver OpRegion.\r | |
7e74fd57 JY |
41 | ///\r |
42 | typedef struct {\r | |
5c66efd0 MG |
43 | CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature\r |
44 | UINT32 SIZE; ///< Offset 0x10 OpRegion Size\r | |
45 | UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version\r | |
46 | UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version\r | |
47 | UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version\r | |
48 | UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version\r | |
49 | UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes\r | |
50 | UINT32 DMOD; ///< Offset 0x5C Driver Model\r | |
51 | UINT8 RSV1[0xA0]; ///< Offset 0x60 Reserved\r | |
7e74fd57 JY |
52 | } INTEL_IGD_OPREGION_HEADER;\r |
53 | \r | |
54 | ///\r | |
5c66efd0 | 55 | /// OpRegion mailbox 1 (public ACPI Methods)\r |
7e74fd57 JY |
56 | ///\r |
57 | typedef struct {\r | |
5c66efd0 MG |
58 | UINT32 DRDY; ///< Offset 0x100 Driver Readiness\r |
59 | UINT32 CSTS; ///< Offset 0x104 Status\r | |
60 | UINT32 CEVT; ///< Offset 0x108 Current Event\r | |
61 | UINT8 RSV2[0x14]; ///< Offset 0x10C Reserved\r | |
62 | UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List\r | |
63 | UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List\r | |
64 | UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List\r | |
65 | UINT32 NADL[8]; ///< Offset 0x180 Next Active Devices List\r | |
66 | UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out\r | |
67 | UINT32 TIDX; ///< Offset 0x1A4 Toggle Table Index\r | |
68 | UINT32 CHPD; ///< Offset 0x1A8 Current Hotplug Enable Indicator\r | |
69 | UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator\r | |
70 | UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator\r | |
71 | UINT32 SXSW; ///< Offset 0x1B4 Display Switch Notification on Sx State Resume\r | |
72 | UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL\r | |
73 | UINT32 CNOT; ///< Offset 0x1BC Current OS Notification\r | |
74 | UINT32 NRDY; ///< Offset 0x1C0 Driver Status\r | |
75 | UINT8 RSV3[0x3C]; ///< Offset 0x1C4 - 0x1FF Reserved\r | |
7e74fd57 JY |
76 | } INTEL_IGD_OPREGION_MBOX1;\r |
77 | \r | |
78 | ///\r | |
79 | /// OpRegion mailbox 2 (Software SCI Interface).\r | |
80 | ///\r | |
81 | typedef struct {\r | |
5c66efd0 MG |
82 | UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data\r |
83 | UINT32 PARM; ///< Offset 0x204 Software SCI Parameters\r | |
84 | UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out\r | |
85 | UINT8 RSV4[0xF4]; ///< Offset 0x20C - 0x2FF Reserved\r | |
7e74fd57 JY |
86 | } INTEL_IGD_OPREGION_MBOX2;\r |
87 | \r | |
88 | ///\r | |
89 | /// OpRegion mailbox 3 (BIOS/Driver Communication - ASLE Support).\r | |
90 | ///\r | |
91 | typedef struct {\r | |
5c66efd0 MG |
92 | UINT32 ARDY; ///< Offset 0x300 Driver Readiness\r |
93 | UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status\r | |
94 | UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator\r | |
95 | UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading\r | |
96 | UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness\r | |
97 | UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request\r | |
98 | UINT32 CBLV; ///< Offset 0x318 Current Brightness Level\r | |
99 | UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table\r | |
100 | UINT32 CPFM; ///< Offset 0x344 Current Panel Fitting Mode\r | |
101 | UINT32 EPFM; ///< Offset 0x348 Enabled Panel Fitting Modes\r | |
102 | UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier\r | |
103 | UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness\r | |
104 | UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values\r | |
105 | UINT8 RSV5[0x62]; ///< Offset 0x39E - 0x3FF Reserved\r | |
7e74fd57 JY |
106 | } INTEL_IGD_OPREGION_MBOX3;\r |
107 | \r | |
108 | ///\r | |
109 | /// OpRegion mailbox 4 (VBT).\r | |
110 | ///\r | |
111 | typedef struct {\r | |
5c66efd0 | 112 | UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data\r |
7e74fd57 JY |
113 | } INTEL_IGD_OPREGION_VBT;\r |
114 | \r | |
115 | ///\r | |
116 | /// IGD OpRegion Structure\r | |
117 | ///\r | |
118 | typedef struct {\r | |
5c66efd0 MG |
119 | INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)\r |
120 | INTEL_IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)\r | |
121 | INTEL_IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)\r | |
122 | INTEL_IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Communication (Offset 0x300, Size 0x100)\r | |
123 | INTEL_IGD_OPREGION_VBT VBT; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1200)\r | |
9fb16e21 JY |
124 | } IGD_IGD_OPREGION_STRUCTURE;\r |
125 | #pragma pack()\r | |
126 | \r | |
127 | #endif\r |